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Functional Description

COMX-P4080-2G-ENP2 Installation and Use (6806800P63B

)

GPIO18, 19, 20, 23, 24 and 26 are multiplexed with other functional blocks. The pins should be
configured as GPIO in RCW data.

GPIO18/19: RCW [DMA1]=1b

GPIO20: RCW [DMA2]=10b

GPIO23/24/26: RCW [IRQ]=1b

CPU_GPIO24

Clock generator of bank 2 frequency
selection

CPU_GPIO26

Clock generator of bank 3 frequency
selection

IOEXT_GPI5

GPI5 of COME connectors

IOEXT_GPI6

GPI6 of COME connectors

IOEXT_GPI7

GPI7 of COME connectors

IOEXT_GPI8

GPI8 of COME connectors

IOEXT_GPO5

GPO5 of COME connectors

IOEXT_GPO6

GPO6 of COME connectors

IOEXT_GPO7

GPO7 of COME connectors

IOEXT_GPO8

GPO8 of COME connectors

Table 4-6 GPIO

GPIO Name

Function

Summary of Contents for COMX-P4080-2G-ENP2

Page 1: ...COMX P4080 2G ENP2 Installation and Use P N 6806800P63B August 2014 ...

Page 2: ...hanges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without ...

Page 3: ...s 25 2 2 Unpacking and Inspecting the Board 27 2 3 Installing and Removing the Module on the Carrier Board 28 3 Controls LEDs and Connectors 31 3 1 Connectors and Switches 31 3 1 1 On board Connectors 31 3 2 On board LEDs 31 4 Functional Description 33 4 1 Processor Core and Cache Memory Complex 34 4 2 Integrated Memory Controller 34 4 3 Local Bus 34 4 4 Clock 35 4 5 NOR FLASH 35 4 6 NAND Flash 37...

Page 4: ...vice EEPROM 52 4 18 3 I2C Device WDT 52 4 18 4 I2C Device RTC 52 4 18 5 I2C Device Clock Generator 53 4 18 6 I2C Device USB 53 5 Clock Structure 55 6 On Boards Power Domains 57 6 1 Power Controlling Sequence 58 7 BSP 59 7 1 BSP Build Requirements 59 7 1 1 Installing Build Tool on SDK1 0 59 7 2 BSP Source Code Package 60 7 2 1 De Compose Source Code Package 60 7 2 2 Setup Build Environment 61 7 3 B...

Page 5: ...ontents COMX P4080 2G ENP2 Installation and Use 6806800P63B 5 7 4 Deploy BSP Image 64 7 4 1 Pre deployment Steps 65 7 4 2 Deploying BSP Image on NOR FLASH 66 7 5 RAMBOOT 67 7 6 NORBOOT 67 7 7 NFSBOOT 67 ...

Page 6: ...COMX P4080 2G ENP2 Installation and Use 6806800P63B Contents 6 Contents Contents ...

Page 7: ...LED and statements of the system 32 Table 4 1 NOR FLASH Map 36 Table 4 2 NAND FLASH Map 37 Table 4 3 Options of the SERDES routed to COM Express Connectors 37 Table 4 4 Memory Capacities 42 Table 4 5 Memory Map 42 Table 4 6 GPIO 43 Table 4 7 SD or Micro SD card on the Carrier 46 Table 4 8 Real Time Clock 48 Table 4 9 WDT 48 Table 4 10 USB PHY 49 Table 4 11 USB HUB 49 Table 4 12 I2C Interface 50 Ta...

Page 8: ...COMX P4080 2G ENP2 Installation and Use 6806800P63B 8 List of Tables ...

Page 9: ...4 Figure 4 1 COMX P4080 2G ENP2 Function Block Diagram 33 Figure 4 2 Distribution of Local Bus 35 Figure 4 3 Distribution of SERDES Lanes 39 Figure 4 4 Board Thermal Management 40 Figure 4 5 Memory Interface 41 Figure 4 6 Distribution of GPIO 45 Figure 4 7 Distribution of SPI Bus 46 Figure 4 8 Distribution of I2C buses 50 Figure 5 1 Clock Distribution 55 Figure 6 1 Power Tree 57 Figure 6 2 Power S...

Page 10: ...COMX P4080 2G ENP2 Installation and Use 6806800P63B 10 List of Figures ...

Page 11: ...various components on the board Chapter 5 Clock Structure on page 55 describes the clock distribution in the COMX P4080 2GENP2 and the setup utility used to configure the product Chapter6 On BoardsPowerDomains onpage57describesthepowersupplysystemforthe module Chapter 7 BSP on page 59 describe how to build COMX P4080 2G ENP2 Basic Support Package BSP and deploy the built images on COMX P4080 2G EN...

Page 12: ...itter ECC Error Correction Code EEPROM Electrically Erasable Programmable Read Only Memory EPROM Erasable Programmable Read Only Memory FCC Federal Communications Commission FEC Fast Ethernet Controller FIFO First In First Out F W Firmware FPBGA Flip Chip Plastic Ball Grid Array GB GigaBytes Gbit Gigabit Gbps Gigabits Per Second GPI General Purpose Input GPIO General Purpose Input Output GPO Gener...

Page 13: ...rtz OS Operating System PCB Printed Circuit Board PCI Peripheral Component Interconnect PCIe Peripheral Component Interconnect Express PIC Programmable Interrupt Controller RAM Random Access Memory RCW Root Configuration Word ROM Read Only Memory RTC Real Time Clock RTM Rear Transition Module SATA Serial Advanced Technology Attachment SDRAM Synchronous Dynamic Random Access Memory SGMII Serial Gig...

Page 14: ...T Watchdog Timer XAUI 4 Lane 10GbE Interface According to IEEE802 3ak Abbreviation Definition Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Usedforon screenoutputandcoderelatedelements or commands in body text Courier Bo...

Page 15: ... command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to...

Page 16: ...About this Manual 16 About this Manual Summary of Changes This manual has been revised and replaces all prior editions Part Number Publication Date Description 6806800P63A August 2012 Initial Version 6806800P63B August 2014 Re branded to Artesyn template ...

Page 17: ...rtesyn representative The product has been designed to meet the standard industrial safety requirements It must only be used in its specific area of office telecommunication industry and industrial control Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is m...

Page 18: ...COMX P4080 2G ENP2 Installation and Use 6806800P63B Safety Notes 18 ...

Page 19: ...X P4080 2G ENP2 Form Factor Basic 95mm x 125mm Bullet list 2 P4080 CPU supported Boot Options 16 bits width NOR flash from local bus standard product default NAND flash from local bus I2C EEPROM Operating System Linux VxWorks P4080 dual channel laid down DDR3 1GB per channel ECC with option to populate only one channel top at 2GB P4080 16 lanes of SERDES routed to COME connectors which can be conf...

Page 20: ...rd RTC and WDT device Provide both remote and local thermal sensor JTAG connector on module Aurora testing points on module On board regulators supply required voltages to devices on the module 12V and 5V standby power supplied to module from ATX type or other type power supply through COME connectors 1 2 Standard Compliances This product meets the following standards Table 1 1 Standard Compliance...

Page 21: ...han City Guangdong PRC Declares that the following product in accordance with the requirements of 2004 108 EC 2006 95 EC 2011 65 EU and their amending directives Product Ruggedized and extended temperature COM Express modules with Freescale QorIQ processing power Model Name Number SCP P4040 4G ENP2 COMX P4080 2G ENP2 has been designed and manufactured to the following specifications EN55022 2010 C...

Page 22: ...d Use 6806800P63B 22 1 3 Mechanical Data The following figures are the top and bottom view of the board Figure 1 2 COMX P4080 2G ENP2 Mechanical Dimensions Top and side views Table 1 2 PCB Dimensions Characteristics Value Height 95 mm Length 125 mm ...

Page 23: ... date of this manual this guide supports the board models listed in the following table Thickness 2 mm Mounting height top side component side 1 Mounting height bottom side component side 2 Table 1 2 PCB Dimensions Characteristics Value Order Number Description COMX P4080 2G ENP2 QorIQ P4080 with 2GB memory ENP2 COM Express Basic size ...

Page 24: ...roduction COMX P4080 2G ENP2 Installation and Use 6806800P63B 24 1 5 Product Identification The following figure shows the location of the board s serial number Figure 1 3 Location of Product Serial Number ...

Page 25: ...merson 12 CFM system airflow volume at 71o C is needed for the heat sink to keep sufficient cooling to the COMXP4080 2G ENP2 Contact your Emerson sales representative for current information on the detailed thermal information of the COMX P4080 2G ENP2 Operating temperatures refer to the temperature of air circulation around the board but not the component temperature Table 2 1 Environmental Requi...

Page 26: ...CPU 105 Tj Memory SDRAM 2GB 3 95 Tc System Overheating Colling Vents Improper cooling can lead to system damage and an void the manufacturer s warranty To ensure proper cooling and undisturbed airflow through the system do into obstruct the ventilation openings of the system Make sure that the fresh air supply is not mixed with hot exhaust from other devices Personal Injury During operation hot su...

Page 27: ... 2 Check for damage and report any damage or differences to customer service Table 2 3 Power Requirement with solder down memory chips State 12v VCC_RCT Idle 2 81A 100 uA Full Loading Linux 2 91A 100 uA 1 Total power dissipation W 34 92 Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life Before touching the prod...

Page 28: ...e sure that the interconnectors are properly aligned and that the five standoffs on the module have contact with the top of the carrier board 3 From the bottom side of the carrier board locate the screw holes on module and carrier board 4 Use the screws to fasten the module to the carrier board Removing the COM module from the carrier board 1 From the back side of the carrier locate the five screw...

Page 29: ...OMX P4080 2G ENP2 Installation and Use 6806800P63B 29 3 While holding the edges pull the module from the carrier board This installation procedure is only for reference Assemble the heat sink and the module based on your own thermal solution ...

Page 30: ...Hardware Preparation and Installation COMX P4080 2G ENP2 Installation and Use 6806800P63B 30 ...

Page 31: ...AG Header The following table lists the Pin out of JTAG connector 3 2 On board LEDs There are several LEDs provided on the module to denote the statements of the system Table 3 1 JTAG connector Pin out Pin Number Signal Name 1 GND 2 CKSTP OUTPUT 3 NC 4 HRST 5 NC 6 SRST 7 NC 8 TMS 9 CKSTP INPUT 10 TCK 11 VDDSENSE 12 RUNSTOP 13 TRST 14 TDI 15 NC 16 TDO ...

Page 32: ...ED and statements of the system LED ID Statement of the system D17 Thermal issue D18 D19 Debug LED 1 2 D3 System asleep D7 DDR3 power OK D4 3 3V power OK D5 2 5V power OK D6 1 8V power OK D13 CORE power OK D9 PLATFORM power OK D10 1 5V power OK D1 USB hub 1 active D2 USB hub 1 high speed D15 USB hub 2 active D16 USB hub 2 high speed ...

Page 33: ... so on This board is designed to support the QorIQ P4080 integrated processor running at the speed of 1 2GHz The QorIQ P4080 integrated communication processor combines eight Power Architecture processor cores with high performance data path acceleration logic network and peripheral bus interfaces required for networking tele communication data communication wireless infrastructure and military ae...

Page 34: ... Hypervisor instruction level privileges APU classic double precision floating point unit 128 Kbyte private L2 cache running at the same frequency of CPU 2 Mbyte of shared L3 CoreNet platform cache CPC 4 2 Integrated Memory Controller The P4080 consists of two DDR controllers that support DDR2 and DDR3 SDRAM It can support a maximum of 64GByte of main memory It is capable of ECC detects and correc...

Page 35: ...system boots must be connected to CS0 Local bus with 16 bits data bus DQ0 DQ15 are directly routed to COM Express connectors A low state is required to enable local bus output and a high state or 1 is required to disable The following figure illustrates the distribution of local bus on P4080 4 4 Clock The eLBC clock is generated by platform clock The divisor is configured by CLKDIV in Clock Ratio ...

Page 36: ...07 FFFF 128 KB RCW Option Data3 Static 4 1 0008 0000 0009 0000 128 KB RCW Option Data4 Static 5 1 000A 0000 000B FFFF 128 KB RCW Option Data5 Static 6 1 000C 0000 000D FFFF 128 KB RCW Option Data6 Static 7 1 000E 0000 000F FFFF 128 KB RCW Option Data7 Static 8 1 0010 0000 0011 FFFF 128 KB RCW Option Data8 Static 9 1 0012 0000 0013 FFFF 128 KB RCW Option Data9 Static 10 1 0014 0000 0015 FFFF 128 KB...

Page 37: ...ES0 7 of bank 1 and SERDES16 SERDES19 SERDES10 13 of bank 2 SERDES8 SERDES9 of bank 1 are used for Aurora debugger defined as Aurora0 1 The remaining 4 lanes of bank 3 are not used in P4080 TheprotocolrunningateachlaneoreachgroupoflanesroutedtoCOMExpressconnectorsare configured by the RCW available options are shown in the following table Table 4 2 NAND FLASH Map Start Address End Address Size Des...

Page 38: ... 1 25 Gbps 8 SRIO2 x4 3 125Gbps SRIO1 x4 3 125Gbps PEX3 x4 5Gbps 0x19 4x SGMII 1 25 Gbps 9 SRIO2 x4 2 5Gbps SRIO1 x4 2 5Gbps XAUI 3 125Gbps 0x13 XAUI 10 SRIO2 x4 3 125Gbps SRIO1 x4 3 125Gbps SGMII x 4 1 25Gbps 0x16 4x SGMII 1 25 Gbps 11 PEX1 x4 2 5Gbps SRIO1 x4 2 5Gbps XAUI 3 125Gbps 0x22 XAUI 12 PEX1 x4 5Gbps SRIO1 x4 2 5Gbps XAUI 3 125Gbps 0x22 XAUI Table 4 3 Options of the SERDES routed to COM ...

Page 39: ...Functional Description COMX P4080 2G ENP2 Installation and Use 6806800P63B 39 The following figure illustrates the distribution of SERDES lanes on P4080 Figure 4 3 Distribution of SERDES Lanes ...

Page 40: ...gement strategy A thermal diode is integrated in P40x0 which connects to a thermal sensor ADT7411 The CPU can get the junction temperature via I2C When the junction temperature goes up to105o C ADT7411 drives INT to low indicates an interrupt to CPU A red LED D17 can show the interrupt status Figure 4 4 Board Thermal Management LED Definition Definition Description D17 INT signal is active ON The ...

Page 41: ...gistered memory subsystem schemes are supported Themodulesupports2GBDDR31066MHzECCmemoriesperchannel 1GBeachchannel one on top assembly and another at bottom of the PCB Each channel contains 9x SDRAM chips on the module Total bottom height limit is specified as xx mm while the SDRAM s height is 1 2mm max The memory interface includes all the necessary termination and IO powers The following figure...

Page 42: ... 0000 C 0000 0000 2000 0000 512MB PCIE1 MEM 3 A000 0000 C 2000 0000 2000 0000 512MB PCIE2 MEM NOTE2 4 A000 0000 C 2000 0000 1000 0000 256MB RIO1 MEM NOTE2 5 B000 0000 C 3000 0000 1000 0000 256MB RIO2 MEM NOTE2 6 C000 0000 C 4000 0000 0800 0000 512MB PCIE3 MEM 7 E000 0000 F E000 0000 1000 0000 256MB LBC NOR FLASH 8 F000 0000 F F000 0000 0040 0000 4MB DCSR 9 F400 0000 F F400 0000 0020 0000 2MB BMAN ...

Page 43: ...ddress 4 and 5 is used instead of address 3 if RIO is configured Table 4 5 Memory Map Address 32 bit Effective Base Address 36 bit Physical Base Address Size Description Table 4 6 GPIO GPIO Name Function CPU_GPIO0 GPI0 of COME connectors CPU_GPIO1 GPI1 of COME connectors CPU_GPIO2 GPI3 of COME connectors CPU_GPIO3 GPI4 of COME connectors CPU_GPIO4 GPO0 of COME connectors CPU_GPIO5 GPO1 of COME con...

Page 44: ...23 24 26 RCW IRQ 1b CPU_GPIO24 Clock generator of bank 2 frequency selection CPU_GPIO26 Clock generator of bank 3 frequency selection IOEXT_GPI5 GPI5 of COME connectors IOEXT_GPI6 GPI6 of COME connectors IOEXT_GPI7 GPI7 of COME connectors IOEXT_GPI8 GPI8 of COME connectors IOEXT_GPO5 GPO5 of COME connectors IOEXT_GPO6 GPO6 of COME connectors IOEXT_GPO7 GPO7 of COME connectors IOEXT_GPO8 GPO8 of CO...

Page 45: ...set the direction for all GPIOs are set to input So all the GPIOs used as output needs to be reconfigured 4 12 SDHC COMX P4080 2G ENP2 provides an SD MMC interface to the COM Express connector and there should be a SD card connector provided on the carrier Figure 4 6 Distribution of GPIO ...

Page 46: ...s The following figure illustrates the distribution of SPI bus 4 14 LAN This module provides 1 GE port with LED controlling signals routing to the COM Express connectors and the magnetic must be placed on carrier board The interface used between MAC and PHY BCM5482 is the RGMII bus in P4080 which is multiplexed with USB1 ULPI bus so RCW EC1 should be set to 00 as RGMII protocol U boot should provi...

Page 47: ...r the communication between 10GEC and PHY 4 14 2 PHY dTSEC0 FMan1 is connected to BCM5482 via RGMII There are totally two ports included in the GE PHY BCM5482 and only first port is used The MDIO address for the first port is 0x01 and the second is 0x02 The MDIO addresses for 4 SGMII PHYs are 0x1C 0x1D 0x1E and 0x1F when SerDes option 5 6 or 10 is applied 4 15 UART INTERFACE COMX P4080 2G ENP2 con...

Page 48: ...upplied by the VCC_BAT pin on the COME connectors 4 17 USB This module consists of one USB PHY USB3315 and one 4 ports USB4 USB7 USB hub USB2514 The interface between the USB controller and USB PHY is ULPI bus the second group of multiplexing interface RGMII ULPI So the RCW should be properly set for the using of the second group of ULPI bus Table 4 8 Real Time Clock Characteristic Value Vendor ST...

Page 49: ...hub One is hub active indicating LED and the other is hub high speed indicating LED 4 17 1 Four USB Ports All four USB interfaces are directly connected to the COM Express connector All the four USB ports signals with two over current detecting signals USB_OC_0_1_N and USB_OC_2_3_N are routed to the COM Express connectors USB_OC_0_1_N is for USB0 and USB1 USB_OC_2_3_N is for USB2 and USB3 Table 4 ...

Page 50: ...C bus and remaining I2C buses are routed to COM Express connectors There is only one device attached to the second I2C bus I2C2 and there are 6 devices attached to the first I2C bus I2C1 The following figure illustrates the distribution of the I2C buses Figure 4 8 Distribution of I2C buses Table 4 12 I2C Interface Address Bus Component Function Oracle Number 0xD0 I2C1 9FG104DGILFT Clock Generator ...

Page 51: ...output signals when on chip or remote temperature is out of range The THERM output is a comparator output that allows on off control of a cooling fan The ALERT output can be reconfigured as a second THERM output if required By default u boot should mask THERM and ALERT output set the temperature measurement range from 0o C to 127o C For setting operation mode and fetching the monitoring temperatur...

Page 52: ...edge As long as the EEPROM receives an acknowledge it will continue to increment the data word address and serially clock out sequential data words When the memory address limit is reached the data word address will roll over and the sequential read will continue AT24C02 s 32K EEPROM was internally organized with 32 pages of 8 bytes each A page write is initiated the same as a byte write but the m...

Page 53: ...us control By default strap pins work For COMX P4080 2G ENP2 the input clock for ICS9FG104 is 25 MHz and three differential outputpairsareprovided FirstpairareconnectedtoSerDesBank1 secondpairareconnected to x2 Aurora Connector and third pair are connected to COM Express connector The forth output pairs are not connected When using strap pins to select output frequency SEL14M_25M FS3 is attached t...

Page 54: ...EPROM or by internal default setting In all cases the configuration method will be determined by the CFG_SEL2 CFG_SEL1 and CFG_SEL0 pins immediately after RESET_N negation In SMBus case the CFG_SEL1 and CFG_SEL0 pins must be 01 so that Hub can be configured as an SMBus slave for external download of user defined descriptors U boot should initialize USB hub during boot up and provide u boot command...

Page 55: ... are not mounted the following signals connects to COM Express connector and will be up to carrier to configure them Figure 5 1 Clock Distribution SERDES bank 1 reference clock select pin B97 on COME SERDES bank 2 reference clock select pin B98 on COME SERDES bank 2 reference clock select pin B98 on COME Bank1_SEL_FS0 0 100MHz Bank2_SEL_S1 0 100MHz Bank2_SEL_S1 0 100MHz Bank1_SEL_FS0 1 125MHz Bank...

Page 56: ...et as 125 MHz and at the speed besides 3 125 Gbps it should be set as 100 MHz For example if lanes in bank 1 are configured as PCIE then the bank 1 reference clock should be set as 100 MHz and if XAUI then should be set as 125 MHz SERDES bank 1 reference clock SERDES bank 2 reference clock SERDES bank 3 reference clock Default 100MHz Default 125MHz Default 125MHz Table 5 1 Configuration of the fre...

Page 57: ...er Domains This subsection describes the power supply system for the module Power is supplied to module from ATX type using Emerson carrier power supply through COM Express connectors and on board regulators supply required voltages to devices on the module Figure 6 1 Power Tree ...

Page 58: ...ng of COMX P4080 2G ENP2 differs between secure boot mode and non secure boot mode For secure boot mode POVDD should be set to 1 5V DC and is powered at least 100 system clock cycles after the rising edge of power on reset signal For non secure boot mode POVDD should be set to GND Figure 6 2 Power Sequence of COMX P4080 2G ENP2 ...

Page 59: ...ild tools of SDK1 0 from Freescale SDK on host computer 1 Login to the Linux host as a non root user user_name 2 Copy the QorIQ DPAA SDK 20110609 systembuilder iso file to this Linux host 3 Runt the ISO file using the following command sudo mount o loop QorIQ DPAA SDK 20110609 systembuilder iso mnt 4 Create a opt freescale directory and update access privileges using the following command sudo mkd...

Page 60: ... 2 BSP Source Code Package 7 2 1 De Compose Source Code Package Copy the COMX P4080 2G ENP2 released BSP source code package COMX_P4080_SRC_ Version Number tar gz to the build host and un compress it in current directory tar xzvf COMX_P4080_SRC_ Version Number tar gz There will be a newly created folder named P4080 which contains SCP P4080 2G ENP2 source code Do not interrupt the installation proc...

Page 61: ...te this directory and provide full privileges for all users to access Use the following commands to create directory and provide privileges linux linux directory contains Linux kernel rootfs and rootfs building scripts Makefile Top makefile for building cleaning all of BSP images for BSP release ItcallsMakefilesandscriptslocatedinsub directoriesto perform the operations Makefile p4080ds Topmakefil...

Page 62: ...gz package The COMX_P4080_ Version_Number tar gz package contains comx dtb Device Tree Blob fsl_fman_ucode_P3_P4_P5_101_8 bin FMAN uCode rcw bin RCW rcw codewarrior bin RCW used for codewarrior to burn image to NOR Flash rootfs_ext2 img RAMDISK image rootfs_nfs tar gz NFS rootfs u boot bin U Boot uImage Linux kernel image 7 3 1 Build U Boot The U Boot is based on SDK1 0 whose version is U Boot 201...

Page 63: ... SDK1 0 whose version is 2 6 34 6 Commands 1 Build by default make kernel dtb 2 Build Targets supported for Linux kernel config default copies the COMX P4080 default configuration to current configuration kernel config configures the kernel based on current configuration kernel compiles kernel with current configuration kernel clean cleans the kernel dtb compiles device tree binary Output The buil...

Page 64: ...and rootfs_nfs tar gz in the current working directory 7 3 4 Build Misc Firmware Misc Firmware for SCP P4080 2G ENP2 includes FMAN uCode and RCW image FMAN uCode is misc fman_ucode fsl_fman_ucode_P3_P4_P5_101_8 bin RCW image is misc rcw rcw bin 7 4 Deploy BSP Image This section explains how to deploy BSP images Assuming that you have built a BSP release package COMX_P4080_V100B00 tar gz by running...

Page 65: ...p the tar gz file to the current directory The following files are extracted to the COMX_P4080_V100B00 comx dtb rcw bin rcw codewarrior bin rootfs_ext2 img rootfs_nfs tar gz uImage fsl_fman_ucode_P3_P4_P5_101_8 bin u boot bin 7 Unzip the rootfs_nfs tar gz file to the tftpboot comx_p4080 location using the sudo tar xzvf COMX_P4080_V100B00 rootfs_nfs tar gz 8 Add tftpboot comx_p4080 rootfs_nfs to NF...

Page 66: ...tenv ubootfile comx_p4080 COMX_P4080_V100B00 u boot bin setenv rootpath tftpboot comx_p4080 rootfs_nfs 13 Test that the network and filename settings can download the files successfully Example tftpboot loadaddr rcwfile tftpboot loadaddr fmanfile tftpboot loadaddr bootfile tftpboot loadaddr norfsfile tftpboot loadaddr fdtfile tftpboot loadaddr ubootfile 7 4 2 Deploying BSP Image on NOR FLASH Follo...

Page 67: ...OT Run run norboot in U Boot norboot will load RAMDISK Linux kernel and DTB from NOR FLASH into RAM and then boot For details please refer to SCP P4080 2G ENP2 User Manual 7 7 NFSBOOT Run run nfsboot in U Boot nfsboot will load Linux kernel and DTB into RAM via network by TFTP and then boot And then mounting NFS on remote server as rootfs For details please refer to SCP P4080 2G ENP2 User Manual ...

Page 68: ...BSP COMX P4080 2G ENP2 Installation and Use 6806800P63B 68 ...

Page 69: ......

Page 70: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc ...

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