MAX1000 User Guide
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Page | 17
July 2017
Note: If you use bank 1A for ADC, you cannot use the bank for GPIO (includes all AIN[0..7] pins)
Board Reference
FPGA Pin No. Description
MKR Header/Pin
I/O Standard
AREF
PIN_D3
Analogue Reference
J1 / 1
N/A
AIN0
PIN_E1
Analogue In Channel 8 of
ADC or GPIO
J1 / 2
3.3 V
AIN1
PIN_C2
Analogue In Channel 2 of
ADC or GPIO
J1 / 3
3.3 V
AIN2
PIN_C1
Analogue In Channel 5 of
ADC or GPIO
J1 / 4
3.3 V
AIN3
PIN_D1
Analogue In Channel 1 of
ADC or GPIO
J1 / 5
3.3 V
AIN4
PIN_E3
Analogue In Channel 3 of
ADC or GPIO
J1 / 6
3.3 V
AIN5
PIN_F1
Analogue In Channel 7 of
ADC or GPIO
J1 / 7
3.3 V
AIN6
PIN_E4
Analogue In Channel 4 of
ADC or GPIO
J1 / 8
3.3 V
D0
PIN_H8
Digital In[0]
J1 / 9
3.3 V
D1
PIN_K10
Digital In[1]
J1 / 10
3.3 V
D2
PIN_H5
Digital In[2]
J1 / 11
3.3 V
D3
PIN_H4
Digital In[3]
J1 / 12
3.3 V
D4
PIN_J1
Digital In[4]
J1 / 13
3.3 V
D5
PIN_J2
Digital In[5]
J1 / 14
3.3 V
D6
PIN_L12
Digital In[6]
J2 / 1
3.3 V
D7
PIN_J12
Digital In[7]
J2 / 2
3.3 V
D8
PIN_J13
Digital In[8]
J2 / 3
3.3 V
D9
PIN_K11
Digital In[9]
J2 / 4
3.3 V
D10
PIN_K12
Digital In[10]
J2 / 5
3.3 V
D11
PIN_J10
Digital In[11]
J2 / 6
3.3 V
D12
PIN_H10
Digital In[12]
J2 / 7
3.3 V
D13
PIN_H13
Digital In[13]
J2 / 8
3.3 V
D14
PIN_G12
Digital In[14]
J2 / 9
3.3 V
D11_R
PIN_B11
Digital In[11] with pull-up
resistor
J2 / 6
3.3 V
D12_R
PIN_G13
Digital In[12] with pull-up
resistor
J2 / 7
3.3 V
RESET
N/A
Connected to system
reset of the board
J2 / 10
N/A
GND
N/A
Ground output to the
connector
J2 / 11
N/A
3.3V
N/A
3.3V power to the
connector
J2 / 12
N/A
VIN
N/A
User power into to the
MAX1000
J2 / 13
N/A
5V
N/A
5V power to the
connector
J2 / 14
N/A
*Can only choose one, hence same name pinning
