ARM Prospector P1100, User Manual, Page: 110 / 154

Programmer’s Reference
4-24 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A
• The host places a sequence of eight data bits onto CPU_SPI_TXD and supplies
a sequence of eight clock pulses on CPU_SPI_SCLK, one pulse for each bit.
The minimum clock period is 4µs, with a minimum clock LOW period of 2µs.
Each bit is read by the keyboard controller on the rising edge of
CPU_SPI_SCLK.
• The next byte is transferred by holding PLD_SPI_nCS0 LOW, placing another
sequence of eight bits of the next byte on CPU_SPI_TXD and supplying
another burst of clock pulses. At least 150µs must be allowed between the start
of one byte transfer and the start of the next.
• After the last byte is transferred, the host de-asserts PLD_SPI_nCS0 to indicate
that the transfer is complete. In response, the keyboard controller de-asserts
KEY_nATN. A new transfer can begin 120µs after the de-assertion of
KEY_nATN.
Note
The signals are described in SPI bus signal summary on page 3-30.
Keyboard controller host reads and report transfers
Figure 4-4 shows the timing for data transfers from the keyboard controller to the host.
Figure 4-4 SPI slave timing: keyboard controller to host
Keyboard controller transfers to the host are as follows:
• The keyboard controller alerts the host by asserting KEY_nATN and driving
CPU_SPI_RXD high.
Last Byte Ist Byte 2nd Byte
PLD_SPI_CS0
KEY_nATN
CPU_SPI_TXD
CPU_SPI_RXD
CPU_SPI_SCLK