ARM Prospector P1100, User Manual, Page: 62 / 154

Hardware Description
3-30 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A
The SPI transmit data, receive data and clock signals are buffered by a 74LCX16224.
This is a +3V device with +5V tolerant inputs. The buffer is permanently enabled, and
introduces a maximum propagation delay of 7ns into each signal. There is minimal
skew because all signals pass through the same buffer.
The only SPI master in the P1100 system is the SA-1100. The SPI bus clock rate can be
varied to suit the selected peripheral.
3.8.2 SPI bus signal summary
The SPI bus is implemented using the alternate output pins for serial port 4, and
additional chip selects are provided by using the GPIO pins shown in Table 3-14.
3.8.3 Using the SPI chip selects
Peripheral selection is performed by decoding three chip address signals
CPU_SPI_CS[2:0]
from the CPU with a 3-to-8 decoder. This generates eight separate
chip select signals, allowing only one chip select to be asserted at a time.
The decoder is enabled and disabled by a signal from the system controller PLD. This
signal is controlled by the
SPI_EN
bit in the SPI enable register (see SPI decoder enable
register on page 4-16.
Table 3-14 SPI signal summary
Signal Source Function
CPU_SPI_TXD SA-1100 GPIO10 SPI transmit data (from the CPU)
CPU_SPI_RXD SA-1100 GPIO11 SPI receive data (to the CPU)
CPU_SPI_CLK SA-1100 GPIO12 SPI clock, should be varied according to the peripheral addressed.
CPU_SPI_FRM SA-1100 GPIO13 SPI frame, used only as a logic analyzer monitor (devices used
need extended timing provided by chip select decode lines)
CPU_SPI_CS[2:0] SA-1100 GPIO[16:14] These signals are used to select one of eight SPI devices, as
shown in Table 3-15. These signals are ignored if PLD_SPI_nEN
is set HIGH (by writing a 0 to the PLD_EN register).
PLD_SPI_nEN PLD This signal enables and disables a 74LVC138 3-to-8 decoder.
This method ensures that only one SPI device can be selected at
any one time.