ARM Prospector P1100, User Manual, Page: 41 / 154

Hardware Description
ARM DUI 0122A Copyright © ARM Limited 2000. All rights reserved. 3-9
3.3.1 Reset signal summary
The reset signals are described in Table 3-2.
3.3.2 Power-on reset
A Dallas Semiconductor DS1233AZ 3.3V EconoReset ensures the orderly power-up
the P1100. This uses a precision reference with a comparator circuit which tests if the
power supply is within tolerance. The typical threshold for the DS1233AZ is 2.88V.
When the power supply is below this threshold the EconoReset asserts
MST_nRST
to
the PLD. When the voltage rises above 2.88V, the EconoReset holds
MST_nRST
asserted for an additional period of 350ms to provide a reliable debounce.
Sleep mode is controlled by the system controller module in the CPU. A pull-down
resistor on the
PLD_nRST_OUT
signal ensures that the signal is pulled LOW until the
PLD is initialized. The CPU asserts
CPU_nRESET_OUT
while
PLD_nRST_OUT
is
asserted, and keeps it asserted until the PLD releases
PLD_nRST_OUT
.
Table 3-2 Reset signal summary
Signal Function
MST_nRST MST_nRST is asserted at powerup (Vcc < 2.88V) or when the
signal SYSTEM_nRESET is asserted. In response, the PLD
asserts PLD_nRST_OUT.
MST_nRST
is ignored by the PLD when the SA-1100 is in
sleep mode, unless the PLD is in development mode when
(see Boot and mode control
on page 3-14
) the reset is
always passed to the CPU.
SYSTEM_nRESET This signal is a version MST_nRST. It is asserted by the button
in the keyboard housing, when the pins on J17 are momentarily
connected, or by a debug system connected to JP18.
This signal can be used by the debug system to detect when the
reset has been pressed.
CPU_nRESET_OUT The SA-1100 asserts CPU_nRESET_OUT during reset and
sleep mode. It is used to reset the UCB1200, the internal state
machines and signals of the PLD, and the flash memory. It is also
routed to a logic analyzer connector, the expansion connector and
to the FPGA.
PLD_nRESET_OUT The signal PLD_nRST_OUT is used to reset the keyboard
controller.