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Programmer’s Reference

4-16

4.3.4

SPI decoder enable register

The SPI decoder enable register, PLD_EN (0x1000000C), contains one active bit (bit
0) which is used to enable/disable the SPI bus chip-select decoder (see SPI bus on
page 3-28).

•

0 = SPI chip-select decoder disabled

•

1 = SPI chip-select decoder enabled.

4.3.5

Software input/output control register

The Software input/output control register, PLD_IO (0x10000010),

the LEDs connected to the PLD IO pins (see LED control on page 3-33) and monitors
the DEVMODE and BOOTSEL switches.

4.3.6

IrDA enable register

The IrDA enable register, PLD_IrDA (0x10000014), contains one active bit (bit 0)
which is used to enable/disable the IrDA port transceiver.

•

0 = IrDA port disabled

•

1 = IrDA port enabled.

Table 4-11 PLD input/output register

Bit

Name

Function

PLD_BOOTSEL
(read-only)

This bit indicates the setting of the BOOTSEL
switch (see Setting the switches on page 2-3).

PLD_DEVMODE
(read-only)

This bit indicates the setting of the DEMODE
switch (see Setting the switches on page 2-3).

PLD_LED3

These bits are used to enable/disable individual
LEDs that are connected to the PLD:
0 = LED OFF
1 = LED ON

PLD_LED2

PLD_LED1

PLD_LED0

PLD_LEDEN

This bit is used to enable/disable all of the LEDs
connected to the PLD, overriding the individual
control bits.
0 = LEDs disabled
1 = LEDs enabled

Summary of Contents for Prospector P1100

Page 1: ...ARM DUI 0122A Prospector P1100 User Guide ...

Page 2: ...roducts or services mentioned herein may be trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All ...

Page 3: ...quipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Caution Changes or modifications ...

Page 5: ...ii Further reading xv Feedback xvi Chapter 1 Introduction 1 1 About the Prospector P1100 1 2 1 2 System overview 1 4 1 3 Software development tools 1 7 Chapter 2 Getting started 2 1 Interface connectors 2 2 2 2 Setting the switches 2 3 2 3 Supplying power 2 4 2 4 Removing the CPU module cover 2 6 2 5 System startup 2 7 Chapter 3 Hardware Description 3 1 SA 1100 CPU 3 2 3 2 System clocks 3 6 ...

Page 6: ...ing the UCB1200 4 27 4 6 MMC programming 4 31 4 7 Programming the touch screen controller 4 34 Appendix A Connector reference A 1 Summary of P1100 Connectors A 2 A 2 UCB1200 Touchscreen Interface JP3 A 4 A 3 MMC Connector JP14 A 5 A 4 ADS7843 Touchscreen Interface JP15 A 6 A 5 JTAG Interface connector JP18 A 7 A 6 Auxiliary PS2 Interface JP19 A 8 A 7 Auxiliary SPI Interface Connector JP21 A 9 A 8 ...

Page 7: ...ent 3 25 Table 3 10 DRAM interface signal descriptions 3 25 Table 3 11 Serial port assignment 3 26 Table 3 12 COMs channel host signals 3 26 Table 3 13 MCP signal summary 3 28 Table 3 14 SPI signal summary 3 30 Table 3 15 SPI chip select assignment 3 31 Table 3 16 Keyboard controller GPIO LED assignment 3 34 Table 3 17 Keyboard controller GPIO port assignments 3 35 Table 3 18 Power management stat...

Page 8: ... 4 15 PLD LCD brightness register 4 18 Table 4 16 GPIO register 4 19 Table 4 17 Touchscreen register 4 19 Table 4 18 Message type summary 4 21 Table 4 19 UCB SIB frame format summary 4 27 Table 4 20 UCB1200 register summary 4 28 Table 4 21 MMC register in SPI mode 4 32 Table 4 22 MMC command summary 4 32 Table 4 23 Control byte 4 34 Table A 1 P1100 connector summary A 2 Table A 2 JP3 pinout A 4 Ta...

Page 9: ...ck diagram 3 3 Figure 3 2 SA 1100 clocks 3 6 Figure 3 3 Reset system architecture 3 8 Figure 3 4 System controller PLD functional block diagram 3 11 Figure 3 5 Interrupt controller 3 12 Figure 3 6 Power output control 3 15 Figure 3 7 Interface control 3 17 Figure 3 8 LEDs and switches 3 20 Figure 3 9 Flash memory block diagram 3 24 Figure 3 10 SPI bus architecture 3 29 Figure 3 11 Keyboard control...

Page 10: ... the keyboard controller 4 23 Figure 4 4 SPI slave timing keyboard controller to host 4 24 Figure 4 5 Keyboard data report 4 25 Figure 4 6 Pointing device report 4 26 Figure 4 7 Report block 4 26 Figure 4 8 SIB frame timing 4 28 Figure 4 9 MMC command token 4 31 Figure 4 10 ADS7843 SPI bus timing 4 35 Figure B 1 Modem and audio expansion connectors B 8 ...

Page 11: ...ed 2000 All rights reserved xi Preface This preface introduces the ARM Prospector P1100 and its reference documentation It contains the following sections About this document on page xii Further reading on page xv Feedback on page xvi ...

Page 12: ...t using the P1100 Information about connecting power and peripherals are contained in this chapter Chapter 3 Hardware Description Read this chapter for description of the major hardware devices This chapter contains details about the hardware architecture of the various parts of the system Chapter 4 Programmer s Reference Read this chapter for a description of the system memory map and programming...

Page 13: ...ights special terminology cross references and citations typewriter Denotes text that may be entered at the keyboard such as commands file names and program names and source code typewriter Denotes a permitted abbreviation for a command or option The underlined text may be entered instead of the full command or option name typewriter italic Denotes arguments to commands or functions where the argu...

Page 14: ...lled when they occur Therefore no additional meaning should be attached unless specifically stated Key to timing diagram conventions Shaded bus and signal areas are undefined so the bus or signal can assume any value within the shaded area at that time The actual level is unimportant and does not affect normal operation Clock Bus stable HIGH to LOW Transient Bus to high impedance Bus change HIGH L...

Page 15: ...eference Manual ARM DDI 0100 The following publications provide information about ARM SDT 2 5 ARM Software Development Toolkit User Guide ARM DUI 0040 ARM Software Development Toolkit Reference Guide ARM DUI 0041 The following publications provide information about the ARM Developer Suite Getting Started ARM DUI 0064 ADS Tools Guide ARM DUI 0067 ADS Debuggers Guide ARM DUI 0066 ADS Debug Target Gu...

Page 16: ...ions about this product please contact your supplier giving the product name a concise explanation of your comments Feedback on this document If you have any comments about this document please send email to errata arm com giving the document title the document number the page number s to which your comments refer a concise explanation of your comments General suggestions for additions and improve...

Page 17: ...ights reserved 1 1 Chapter 1 Introduction This chapter introduces the Prospector P1100 development system and contains the following sections About the Prospector P1100 on page 1 2 System overview on page 1 4 Software development tools on page 1 7 ...

Page 18: ...icle systems and games consoles At the heart of every P1100 system is a the P1100 CPU board The P1100 is supplied at two levels Compact system a CPU board in small enclosure with power supply Expanded system a CPU board keyboard and LCD display in a larger enclosure An expanded system is illustrated in Figure 1 1 on page 1 3 Expanded systems are available with a choice of two displays 8 4 inch VGA...

Page 20: ...ector P1100 system Figure 1 2 System architecture Expansion connectors 8 64MB flash 16MB EDO DRAM 16MB EDO DRAM second bank UCB1200 System controller PLD Switches LEDs PSU FPGA option COM1 COM2 IrDA ADS7843 touch screen controller Keyboard control MMC1 SA 1100 LCD screen Keyboard Mouse pointer Expanded system options SPI expansion Audio IN OUT ...

Page 21: ...B Flash 32MB fitted as standard 32MB EDO DRAM two banks of 16MB each system controller Programmable Logic Device PLD providing power supply mode control interrupt control flash chip select control boot mode control two RS232 COMs ports IrDA port keyboard controller touch screen controller SPI expansion option Multi Media Card MMC socket Figure 1 3 on page 1 6 shows the layout of the CPU board uppe...

Page 22: ...erved ARM DUI 0122A Figure 1 3 CPU board layout top 0 2 4 6 8 A C E 1 2 3 4 5 Audio IN Audio OUT Power supply jack 9V Battery input connector 3V IrDA COM1 COM2 console FLASH DRAM MMC StrongARM processor SA 1100 System controller PLD Keyboard controller UCB1200 ...

Page 23: ... programming interfaces operating system neutrality reusable code over a range or ARM and third party development platforms a set of tried and tested functions that enable rapid development of applications and device drivers AFS provides a collection of low level software which runs on a wide range of ARM based platforms The primary functions of the AFS are to identify and initialize the system pr...

Page 24: ...prises Code generation tools Embedded C and C compilers assembler and linker for ARM and Thumb instruction sets An integrated development environment for Windows CodeWarrior IDE from Metrowerks Powerful GUI debuggers Instruction set simulators ROM based debug tools AFS On line documentation ARM Applications Library Real time Trace support For further information refer to the ADS documentation ...

Page 25: ...2 Getting started This chapter describes how to start working with the P1100 It contains the following sections Interface connectors on page 2 2 Supplying power on page 2 4 Removing the CPU module cover on page 2 6 Setting the switches on page 2 3 System startup on page 2 7 ...

Page 26: ... rights reserved ARM DUI 0122A 2 1 Interface connectors Figure 2 1 shows the external interface connectors on the side of the motherboard enclosure Figure 2 1 External interface connectors Audio in Audio out DC power supply IrDA port COM1 COM2 console ...

Page 27: ...ot and mode control on page 3 14 The default setting is DEVMODE OFF SW5 BOOTSEL controls the boot image selection at system start up as described in System startup on page 2 7 The default setting for BOOTSEL selects the boot monitor Figure 2 2 shows the location and settings of the DEVMODE and BOOTSEL switches Figure 2 2 BOOTSEL and DEVMODE switches The hexadecimal switch and remaining three eleme...

Page 28: ...ard and display fitted the boot monitor uses the built in display Data entry can then be through either the console port or keyboard interface 2 3 1 Connecting the external power supply Connect power to the P1100 as follows 1 Connect the DC out lead from the PSU to the DC power supply socket see Figure 2 1 on page 2 2 2 Plug the PSU into a suitable AC socket outlet 2 3 2 Installing batteries Cauti...

Page 29: ... follows 1 Remove the battery cap by turning it one quarter turn counter clockwise 2 Insert two AA size batteries 3 Replace the cap and re secure by it turning it one quarter turn clockwise The system powers up immediately Note Battery provision is intended for experimentation with battery operation and power control rather than for continuous operation 1 2 ...

Page 30: ...upwards until it clear of the CPU unit housing 3 Slide the cover forwards On systems with a display it may be necessary to open the display housing lid slightly to remove and refit the CPU module cover Note The Prospector P1100 has been tested with the cover in place and found to comply with FCC class A limits see Electromagnetic conformity on page iii Operating the P1100 with covers removed may m...

Page 31: ...e the boot monitor to DRAM before it is invoked which is necessary if you want to reprogram the flash The boot switcher functions as follows If the BOOTSEL switch see Figure 2 2 on page 2 3 is LOW the boot monitor code is executed The boot monitor is a reserved image in flash with the image number 4280910 0x41524E If the BOOTSEL is HIGH the boot switcher Searches for a System Information Block SIB...

Page 32: ...ment sets up a basic µHAL interrupt handling environment displays a status report and a monitor prompt on the console Note For systems with a keyboard and display fitted the boot monitor configures the display for a blue screen text output and replicates the console port output onto it Data entry can then be through either the console port or keyboard An Angel debug monitor is provided in flash as...

Page 33: ...e 3 8 System controller PLD on page 3 11 LED control and switch sensing on page 3 20 Memory subsystem on page 3 23 Serial interfaces on page 3 26 SPI bus on page 3 29 Keyboard controller on page 3 32 MMC interface on page 3 37 Touch screen controller on page 3 38 Philips UCB1200 codec and touch screen controller on page 3 39 Display interface on page 3 43 Distribution board on page 3 44 Power supp...

Page 34: ...al timer power management controller reset controller two on chip oscillators peripheral control module 6 channel DMA controller LCD controller with programmable screen resolution five dedicated serial ports The core can be clocked at a range of clock frequencies between 59 and 191 7MHz with the upper limit determined by the speed grade of CPU fitted The SA 1100 operates at a fixed core voltage of...

Page 35: ...0 provides two RS232 serial ports UDC device port not used on P1100 IrDA port MCP port Serial Peripheral Interface SPI port For descriptions of these serial ports and their implementation in the P1100 design see Serial interfaces on page 3 26 ARM SA 1 core Icache Dcache Minicache IMMU DMMU Write buffer Read buffer Serial channel 0 Serial channel 1 Serial channel 2 Serial channel 3 Serial channel 4...

Page 36: ... wake up interrupts GPIO1 CPU_GPIO1 Input PLD merged interrupts all other external sources GPIO2 LCD_DD_8 Output Bit8 of 16 bit LCD data path GPIO3 LCD_DD_9 Output Bit9 of 16 bit LCD data path GPIO4 LCD_DD_10 Output Bit10 of 16 bit LCD data path GPIO5 LCD_DD_11 Output Bit11 of 16 bit LCD data path GPIO6 LCD_DD_12 Output Bit12 of 16 bit LCD data path GPIO7 LCD_DD_13 Output Bit13 of 16 bit LCD data ...

Page 37: ... UART2_CTS Input UART2 CTS GPIO21 CPU_MBGNT Output Expansion bus grant SA 1100 memory request mode GPIO22 CPU_MBREQ Input Expansion bus request SA 1100 memory request mode GPIO23 CPU_GPIO23 Expansion uncommitted GPIO24 CPU_GPIO24 Expansion uncommitted GPIO25 CPU_GPIO25 LED current sink can be configured as 1Hz from RTC GPIO26 CPU_RCLK_OUT Buffered core frequency 2 clock GPIO27 CPU_32KHz Buffered u...

Page 38: ...d version of the core clock is used to drive on chip controllers and also appears on GPIO26 as CPU_RCLK_OUT The secondary PLL supplies a 48MHz clock for the GPIO provided serial ports and pin controllers The reference clock from the 32 768 kHz crystal is used to drive an on chip Real Time Clock RTC and power management controller A buffered version of this clock also appears on GPIO27 An RTC deriv...

Page 39: ...ight ARM Limited 2000 All rights reserved 3 7 3 2 2 Keyboard clock In addition to the SA 1100 derived clocks a 4 MHz ceramic resonator is used to drive the on chip oscillator within the keyboard controller see Keyboard controller on page 3 32 ...

Page 40: ...n page 3 10 Software reset on page 3 10 Watchdog reset on page 3 10 Sleep reset on page 3 10 The architecture of the reset control subsystem is illustrated in Figure 3 3 Figure 3 3 Reset system architecture SA 1100 System controller PLD UCB1200 EconoReset FPGA option Keyboard controller Multi ICE connector JTAG MST_nRST SYSTEM_nRESET JP40 JP17 BUF_JTAG_nRESET CPU_nRESET_OUT PLD_nRST_OUT ...

Page 41: ...PLD_nRST_OUT is asserted and keeps it asserted until the PLD releases PLD_nRST_OUT Table 3 2 Reset signal summary Signal Function MST_nRST MST_nRST is asserted at powerup Vcc 2 88V or when the signal SYSTEM_nRESET is asserted In response the PLD asserts PLD_nRST_OUT MST_nRST is ignored by the PLD when the SA 1100 is in sleep mode unless the PLD is in development mode when see Boot and mode control...

Page 42: ... in the SA 1100 Reset controller Software Reset Register RSRR Reset is applied to most of the internal circuitry of the SA 1100 and CPU_nRESET_OUT asserted DRAM contents are retained during this reset because DRAM refresh and configuration settings are not cleared The SA 1100 remains in reset for 256 processor clock cycles before it reboots 3 3 5 Watchdog reset The watchdog reset is triggered when...

Page 43: ... 3 12 Boot and mode control on page 3 14 LCD power control and battery sensing on page 3 14 Interface enable on page 3 17 Flash chip select control on page 3 18 Buffer control on page 3 19 LED control and GPIO pins on page 3 19 Figure 3 4 shows the functional block diagram of the system controller PLD Figure 3 4 System controller PLD functional block diagram A JTAG interface is provided for in sys...

Page 44: ...tem Those from devices internal to the SA 1100 are controlled by the interrupt controller within the SA 1100 Interrupts from devices external to the SA 1100 are collated and controlled by the system controller PLD as shown in Figure 3 5 Figure 3 5 Interrupt controller Touchscreen controller COM2 MAX3225 COM1 MAX3225 CODEC FPGA option UCB1200 Keyboard controller PLD_INT PLD_COM2 PLD_COM1 PLD_CODEC ...

Page 45: ...ted in Table 3 3 Note The COM 2 1 _RDY and COM 2 1 _SENSE signals are not implemented as interrupts in the current release of the PLD code However the status of these signals can be read by polling the associated PLD registers see System controller PLD on page 3 11 Table 3 3 Interrupt summary Interrupt signal Source SA 1100 pin Function CDC_IRQ 3 0 FPGA if fitted GPIO1 CDC_IRQ 3 1 are interrupt in...

Page 46: ... be used when DRAM contents can be considered as undefined when returning from sleep mode 3 4 4 LCD power control and battery sensing This function of the system controller provides power supply mode control LCD power and bias control battery sensing Figure 3 6 on page 3 15 shows the architecture of the power output control function of the PLD COM 2 1 _SENSE COM 2 1 port GPIO1 These are low priori...

Page 47: ...lected The use of modes is discussed in Power supply on page 3 45 LCD power output and bias control A number of signals from the system controller PLD controlled by the PLD_PWR register are used to enable and disable the display power supply outputs The signals controlled by the PLD_LCDBC register are used to vary the monochrome bias output LCD_OUT4 Figure 3 6 Power output control PLD_PWR PLD_LCDB...

Page 48: ...an read this bit to determine whether the system is running from battery power or an external power supply The state of the sense line can be read from this bit in the power control register see Power control register on page 4 14 Table 3 4 LCD power configurations Signal Function PLD_LCDON Enables the monochrome LCD PLD_LCD_S1_OFF Enables 3V supply to the LCD PLD_LCD_S2A_ON Enables the 3 3V suppl...

Page 49: ...Figure 3 7 Interface control These are controlled by PLD registers see System controller PLD registers on page 4 13 The signals controlled by the PLD are summarized in Table 3 5 on page 3 18 Writing a 1 to the relevant bit enables the signal PLD_CODEC PLD_KBD PLD_SPIDEN PLD_IrDA PLD_COM2 PLD_COM1 PLD_KBWKP PLD_KEY_EN PLD_SPI_nEN PLD_IrDA_EN PLD_COM2_EN PLD_COM1_EN PLD_CDC_EN Keyboard controller SP...

Page 50: ... FPGA Table 3 5 Interface enable Signal Function CDC_EN FPGA codec enable PLD_COM2_EN Serial channel 2 transceiver enable PLD_COM1_EN Serial channel 1 transceiver enable PLD_IrDA_EN IrDA port enable PLD_SPI_nEN Enables the SPI bus decoder when LOW see SPI bus on page 3 28 PLD_KEY_EN Keyboard enable Table 3 6 Flash chip select decoding CPU_nCS 2 0 CPU_A 25 24 Chip select Function Base address 110 0...

Page 51: ...onal FPGA but the PLD must be reprogrammed to support this The significant signals are PLD_DBUF_DIR a passed through version of CPU_MEM_nWE PLD_MEMBUF_nOE a passed through version of CPU_MEM_nOE 3 4 8 LED control and GPIO pins The PLD provides control for four LEDs on the CPU board see Software controlled LEDs on page 3 21 It also provides three GPIO pins PLD_GPIO 2 0 These are connected to the au...

Page 52: ...0 CPU card include software controlled LEDs five software readable switches software readable hexadecimal switch Two additional LEDs provide status indication for the SA 1100 and FPGA if fitted Figure 3 8 shows the LED control and switch reader Figure 3 8 LEDs and switches Keyboard controller System controller PLD 1 2 3 4 5 0 2 4 6 8 A C E D2 D6 D3 D7 D4 D8 D5 D9 ...

Page 53: ...mal rotary switch providing a 4 bit value Three switches within the DIL pack and the rotary switch are connected to the GPIO pins on the keyboard controller These switches can be assigned any meaning by the software developer Table 3 7 LEDs connection and control LED Name Color Driving device Driving signal D1 CPU_LED Green SA 1100 CPU_GPIO25 D2 PLD_LED0 Red System controller PLD not named D3 PLD_...

Page 54: ... The switches are connected and assigned as shown in Table 3 8 Table 3 8 Switch connections and assignment Switch Device Pin name signal Function SW1 Keyboard controller GIO10 SW11 User definable SW2 GIO10 SW12 SW3 GIO10 SW13 SW4 System controller see Boot and mode control on page 3 14 PLD_DEVMODE Development mode control SW5 PLD_BOOTSEL AFS boot control Rotary hex Keyboard controller GIO 17 14 Su...

Page 55: ...a single contiguous 64MB region for the flash memory see Flash chip select control on page 3 18 The parts used are Intel G28F640J5 150 parts in a 56 ball microBGA package Note The 16 bit ROM size SA 1100 option is not supported by the P1100 Flash hardware interface The hardware interface to the SA 1100 is as follows buffered address and data buses a 5V level translated version of the system reset ...

Page 56: ... flash tools and utilities provided by the ARM Firmware Suite see the ARM Firmware Suite Reference Guide Flash and power conservation The flash devices enter standby mode automatically when their chip selects are not asserted This state conserves power without time penalty because the devices power up within a normal flash access cycle Power down mode is only used during reset because it provides ...

Page 57: ...ummarized in Table 3 9 The DRAM interface connects directly to the SA 1100 The signals used to access and control the DRAM are summarized in Table 3 10 Table 3 9 Maximum DRAM current 50ns 60ns EDO Mode current 105mA 85mA Standby current 200µA 200µA Self Refresh current 400µA 400µA Refresh current 140mA 115mA Table 3 10 DRAM interface signal descriptions Signal Function CPU_A 22 10 These provide a ...

Page 58: ... Table 3 11 Serial port assignment SA 1100serial channel Usage 0 Not used 1 COM1 2 IrDA 3 COM2 4 MCP SSP Table 3 12 COMs channel host signals Signal Source Function CPU_UART1_RTS SA 1100 GPIO_17 GPIO_17 is configured as an output for the CPU_UART1_RTS signal Assert this signal when software is ready to transmit UART1_CTS COM1 transceiver GPIO_18 is configured as an input for the UART1_CTS line Thi...

Page 59: ... the state of the COM1_SENSE bit in the Peripheral Control Register Read this bit to determine if a cable is plugged into the socket COM2_RDY COM1 transceiver This signal is monitored by the PLD and controls the state of the COM2_READY bit in the Peripheral Control Register Read this bit to determine if the serial port is ready to transmit COM2_SENSE COM1 transceiver This signal is monitored by th...

Page 60: ...ut this device are provided in Philips UCB1200 codec and touch screen controller on page 3 39 The signals used to provide the interface between the SA 1100 and UCB1200 are summarized in Table 3 13 3 7 4 SPI bus The SSP function of serial channel 4 is used to provide an SPI channel see SPI bus on page 3 29 This uses the alternate functions of the GPIO 13 10 pins of the SA 1100 and is allows both ty...

Page 61: ...he devices attached to the SPI bus refer to the following sections Keyboard controller on page 3 32 MMC interface on page 3 37 Touch screen controller on page 3 38 Philips UCB1200 codec and touch screen controller on page 3 39 3 8 1 SPI bus architecture The architecture of the SPI bus on P1100 CPU board is shown in Figure 3 10 Figure 3 10 SPI bus architecture CPU_SPI_SCLK CPU_SPI_RXD CPU_SPI_TXD C...

Page 62: ...is generates eight separate chip select signals allowing only one chip select to be asserted at a time The decoder is enabled and disabled by a signal from the system controller PLD This signal is controlled by the SPI_EN bit in the SPI enable register see SPI decoder enable register on page 4 16 Table 3 14 SPI signal summary Signal Source Function CPU_SPI_TXD SA 1100 GPIO10 SPI transmit data from...

Page 63: ...equirements are described in Keyboard controller host interface timing on page 4 23 The MMC interface timing requirements are described in MMC transaction timing on page 4 33 The touch screen controller timing requirements are described in Programming the touch screen controller on page 4 34 Table 3 15 SPI chip select assignment CPU_SPI_CS 2 0 Active chip select Device 000 PLD_SPI_nCS0 Keyboard co...

Page 64: ...th the keyboard controller on page 3 34 Power sensing and management on page 3 36 Pulse Width Modulated PWM The architecture of the keyboard controller implementation is shown in Figure 3 11 Figure 3 11 Keyboard controller CPU_SPI_SCLK CPU_SPI_RXD CPU_SPI_TXD CPU_SPI_CS 2 0 CPU_GPIO 0 PLD_SPI_nEN PLD_SPI_nCS3 KEY_nATTN SA 1100 System controller PLD 3 to 8 decoder Keyboard controller 4MHz crystal J...

Page 65: ...ntroller scans and debounces a keyboard matrix of up to 8 rows x16 columns The default matrix for the device is the Fujitsu FKB7654 miniature keyboard with which P1100 system units are equipped The Fujitsu keyboard provides an IBM PC AT style key layout within a minimal package size The matrix layout registers within the keyboard controller are automatically updated with data corresponding to this...

Page 66: ...s of 1 16 of a second Faster blink rates give the LED the appearance of being illuminated continuously The LEDs can be made to flash by adding meta blink intervals within blink cycle This give the appearance of the LED flashing For information about programming the LEDs see Programming the keyboard controller on page 4 20 Note You cannot put the keyboard controller into SUSPEND mode if a LED is on...

Page 67: ...istors to the hex encoded rotary switch JP10 GIO11 SW11 DIL switch SW1 GIO12 SW12 DIL switch SW2 GIO13 SW13 DIL switch SW3 GIO14 SW14 Rotary hex switch bit0 GIO15 SW15 Rotary hex switch bit1 GIO16 SW16 Rotary hex switch bit2 GIO17 SW17 Rotary hex switch bit3 GIO20 SW0 INT0 Expansion JP11 This port is a 2 bit port with individual pins configurable as inputs outputs or switch inputs When configured ...

Page 68: ...Ds It remains in this state until the PSU_BATT_OK signal transitions to a HIGH Normal state for this signal is HIGH LID CLOSED This state can be entered from either the state of the physical pin when enabled or under software control The controller can be activated as follows An external switch GIO20 or GIO21 transition If _LID is HIGH only the external switch XSW1 or 2 activates the keyboard cont...

Page 69: ...ected with PLD_SPI_CS2 Figure 3 12 shows the architecture of the MMC interface Figure 3 12 MMC interface Note Socket 2 is not fitted as standard It is possible to obtain a stacking socket to fit onto socket 1 All pins except the chip select pin need to be soldered in parallel PLD_SPI_CS2 appears at a test point close to MMC socket as shown in Figure 3 12 The connector provides hot swap capability ...

Page 70: ...he touch screen interface Figure 3 13 Touch screen interface ADS7843 The SA 1100 communicates with the ADS7843 using the SPI bus The signal PLD_SPI_CS3 is used to select the device The maximum operating frequency for SPI bus accesses to the ADS7843 is 115 kHz The SPI clock for this device idles HIGH and is sampled on the rising edge The ADS7843 issues interrupt requests by asserting TCH_nPENIRQ to...

Page 71: ...ock on page 3 41 Multiplexed analog to digital converter on page 3 42 Figure 3 14 shows a simplified functional diagram of the UCB1200 Figure 3 14 UCB1200 functional diagram The UCB1200 is programmed using the Serial Interface Bus SIB which is provided by the MCP port of the SA 1100 see Programming the UCB1200 on page 4 27 CPU_UCB_FRM CPU_UCB_RXD CPU_UCB_TXD CPU_UCB_CLK CPU_GPIO 1 UCB_IRQ SA 1100 ...

Page 72: ...provides more information about interface timing 3 12 2 Audio codec The audio codec is a 12 bit sigma delta codec with programmable sample rates It has outputs capable of directly driving a speaker and microphone with programmable voltage levels The audio sample rate is derived from the SIB clock input to the UCB1200 The sample rate is programmable in the audio control register A The sample rate i...

Page 73: ... cycle if an odd divisor is used A number of the GPIO pins from the UCB1200 are designated for modem support as shown in Table 3 19 3 12 4 General purpose input output pin block The GPIO port provides 10 input output pins The pins can be individually configured as inputs or outputs in the IO port direction and register can be read from or written to by accessing the IO port data register Each pin ...

Page 74: ...our switched resistive voltage divider inputs and the five touch screen inputs The switched resistive inputs are connected to the DF13 style connector JP3 and are available for user assigned functions These inputs have a typical full scale range of 7 5V a maximum of 7 9V The touch screen inputs are described in Touch screen controller on page 3 40 Conversions are synchronized by signal UCB_ADCSYNC...

Page 75: ...480 18bpp single panel transmissive screen LQ084V1DG21 with backlight and touchscreen The relative merits of these two options are summarized in Table 3 20 Active color TFTs employ an active matrix of transistors to control the pixels As a result they give fast switching times which prevents ghosting Hyper reflective screens illuminate the screen by using ambient light reflected back through the L...

Page 76: ...allel with surface mount LEDs on the CPU board Mechanical provision has been made for incorporating a touch pad as an alternate pointing device However this does require a redesign of the escutcheon plate used to mount the device The micro joystick used in the P1100 design is the MicroModule part number VP5510 This is a compact button style joystick providing 2 button mouse functionality Table 3 2...

Page 77: ...ss power is required For example when the system is in sleep mode select the PFM mode by writing a 0 to the PWR_MODE bit in the power control register in the PLD When the system is active select the PWM mode by writing a 1 to the PWR_MODE bit All the switched outputs and the MAX1703 mode are controlled by the PLD_PWR register in the system controller PLD see LCD power control and battery sensing o...

Page 78: ... and 5V to the system 3V regulator Linear Technology LT1085 positive adjustable linear regulator able to supply an output current of 3A Fitted with a 10 4 C W heatsink 5V regulator National Semiconductor LM2940CT 5 0 is a fixed 5V linear regulator capable of providing 1A The 5V supply is used for system expansion only and the 3V supply is used directly for FPGA expansion in high current drain appl...

Page 79: ... PSU_ 1V5 Yes MAX1703 from 3V_SUPPLY using the gain block in the MAX1703 and P channel MOSFET Q3 as a linear regulator 1 5V to the SA 1100 core Switched by the SA 1100 when the 3V rail is stable CPU_PWR_EN is used to switch the supply on using a FMMT617 transistor 3V No MAX1703 from 3V_SUPPLY 3V main system power including SA 1100 input output pad voltage LCD_OUT1 Yes MAX1703 from 3V_SUPPLY A swit...

Page 80: ...s CRITICAL SUSPEND mode It exits CRITICAL SUSPEND when PSU_BATT_OK is asserted PSU_VDD_FLT an inverted version of PSU_BATT_OK which is supplied to the SA 1100 When asserted the SA 1100 enters sleep mode PSU_LCD_BIAS Yes Maxim MAX686 Variable 14V to 20V Bias voltage for monochrome LCDs Digitally controlled output ranging between 14V to 20V controlled by setting either PLD_LCD_UP or PLD_LCD_DN in th...

Page 81: ... interrupt This is primarily the keyboard controller and touchscreen but can also include the serial ports and IrDA interfaces Any power saving is limited in this mode because the DRAM and SA 1100 core must remain active to allow screen refresh to continue Sleep mode Used when the case is closed or no activity detected for a predetermined period of time In this mode the screen and the SA 1100 core...

Page 82: ... ARM Limited 2000 All rights reserved ARM DUI 0122A System wakeup To wake from sleep mode 1 Restore the SA 1100 configuration registers and any system context 2 Take the DRAM out of self refresh mode 3 Re initialize and power up the LCD ...

Page 83: ...N The TDO signal CPU_TDO from the SA 1100 provides the TDI input to the XCR3128 The TDO signal from the PLD is then returned to the JTAG interface through the buffer The JTAG reset signal has a pull down on the board to minimize power consumption in normal use and a pullup on the cable to ensure correct functioning of Multi ICE A small profile single row 8 way vertical DF13 type connector JP18 pro...

Page 84: ... pin 3 nTRST is connected to pin 2 of the same connector with a 2kΩ resistor fitted inside the connector shell This pulls the nTRST signal HIGH Table 3 23 JTAG interface cable specification Xilinx PC connector pin JP18 pin P1100 Function 1 3 TDO 2 6 TCK 3 5 TDI 4 4 TMS 18 19 20 21 8 GND Table 3 24 Multi ICE cable specification Multi ICE connector pin JP18 pin P1100 Function 1 2 1 3V 13 3 TDO 9 6 T...

Page 85: ...rs are provided to connect a logic analyzer to the key system signals in the design The Mictor connectors have been laid out to easily connect to a Hewlett Packard HP16xxx series logic analyzer The primary function of each connector is JP34 SA 1100 address bus JP35 SA 1100 data bus JP36 SA 1100 and PLD generated system control signals ...

Page 87: ...faces of the main components of the P1100 It contains the following sections About this chapter on page 4 2 Memory map on page 4 3 System controller PLD registers on page 4 13 Programming the keyboard controller on page 4 20 Programming the UCB1200 on page 4 27 MMC programming on page 4 31 Programming the touch screen controller on page 4 34 ...

Page 88: ...the system controller PLD It also discusses how to access the major peripheral devices and describes the interface timing requirements The registers for devices such as those in the SA 1100 are listed for convenience but you should refer to the documentation supplied by the device manufacturers for detailed information See Other publications on page xv ...

Page 89: ...CPU_nCS 2 0 from the CPU and Table 4 1 SA 1100 memory map Base address Size Description 0x00000000 128MB Static bank select 0 0x08000000 128MB Static bank select 1 0x10000000 128MB Static bank select 2 0x18000000 128MB Static bank select 3 0x20000000 256MB Reserved for PCMCIA socket 0 0x30000000 256MB Reserved for PCMCIA socket 1 0x40000000 1GB Reserved 0x80000000 256MB Peripheral module registers...

Page 90: ... generated see Flash chip select control on page 3 18 4 2 2 PCMCIA socket 1 0 This region is mapped conventionally There are no PCMCIA devices on the P1100 CPU board Table 4 2 Static memory region memory map Base address Device Static bank select PLD chip select 0x00000000 Flash region 0 0 Flash_CS0 0x01000000 Flash region 1 0 Flash_CS1 0x02000000 Flash region 2 option 0 Flash_CS2 0x03000000 Flash...

Page 91: ...ble Bit 5 Receive Clock Edge Select Bit 6 Transmit Clock edge Select 0x8001 0004 UART1 Control Register 1 Bit 0 3 Baud Rate Divisor 0x8001 0008 UART1 Control Register 2 Bit 0 7 Baud Rate Divisor 0x8001 000C UART1 Control Register 3 Bit 0 Receiver Enable Bit 1 Transmitter Enable Bit 2 Break Bit 3 Receive FIFO Interrupt Enable Bit 4 Transmit FIFO Interrupt Enable Bit 5 Loopback Mode 0x8001 0010 UART...

Page 92: ...RT2 HSSP Control Register 1 0x8004 006C UART2 HSSP Data Register 0x8004 0074 UART2 HSSP Status Register 0 0x8004 0078 UART2 HSSP Status Register 1 0x9006 0028 UART2 HSSP Control Register 2 This register is in the PPC space COM 2 UART 3 serial port 3 0x8005 0000 UART3 Control Register 0 Bit 0 Parity Enable Bit 1 Parity Select Bit 2 Stop Bit Select Bit 3 Data Size Select Bit 4 Sample Clock Enable Bi...

Page 93: ...it 4 Receiver End of Break Bit 5 Error in FIFO Bit 0 Transmitter Busy Flag Bit 1 Receive FIFO Not Empty Bit 2 Transmit FIFO Not Full Bit 3 Parity Error Bit 4 Framing Error Bit 5 Receive FIFO Overrun UCB1200 MCP serial channel 4 These registers set up the port used to communicate with the UCB1200 0x8006 0000 MCP Control Register 0 0x8006 0008 MCP Data Register 0 0x8006 000C MCP Data Register 1 0x80...

Page 94: ...FIFO Interrupt Enable Bit 2 Loopback Mode Bit 3 Serial Clock Polarity Bit 4 Serial Clock Phase Bit 5 External Clock Select 0x8007 006C SSP Data Register 0x8007 0074 SSP Status Register Bit 1 Transmit FIFO Not Full Bit 2 Receive FIFO Not Empty Bit 3 SSP Busy Flag Bit 4 Transmit FIFO Service Request Bit 5 Receive FIFO Service Request Bit 6 Receive FIFO Overrun Table 4 3 Peripheral module registers c...

Page 95: ...02 0010 Power Manager Configuration Register 0x9002 0014 Power Manager PLL Configuration Register 0x9002 0018 Power Manager GPIO Sleep State Register 0x9002 001C Power Manager Oscillator Status Register Reset controller 0x9003 0000 Reset Controller Software Reset Register 0x9003 0004 Reset Controller Status Register GPIO 0x9004 0000 GPIO Pin Level Register Bit 0 PLD Interrupt0 Status Bit 1 PLD Int...

Page 96: ...t 19 UART2 RTS Bit 25 CPU LED Active Low 0x9004 000C GPIO Pin Output Clear Register Set to 1 to Clear Pin Bit 14 16 Encoded SPI Device Selection Active High Bit 17 UART1 RTS Bit 19 UART2 RTS Bit 25 CPU LED Active Low 0x9004 0010 GPIO Rising Edge Detect Register 0x9004 0014 GPIO Falling Edge Detect Register 0x9004 0018 GPIO Edge Detect Status Register 0x9004 001C GPIO Alternate Function Register Se...

Page 97: ...errupt Controller Mask Register 0x9005 0008 Interrupt Controller Level Register 0x9005 001C Interrupt Controller FIQ Pending Register 0x9005 0020 Interrupt Controller Pending Register 0x9005 0010 Interrupt Controller Control Register Table 4 4 System controller module registers Address Register Notes Table 4 5 Memory and expansion registers Address Register Notes 0xA000 0000 DRAM Configuration Reg...

Page 98: ...to support the size and memory device configuration for each bank as shown in Table 4 7 refer to the Intel StrongARM SA 1100 Developer s Manual Table 4 6 LCD control registers Address Register Notes 0xB010 0000 LCD controller control register 0 0xB010 0004 LCD controller status register 0xB010 0010 DMA channel 1 base address register 0xB010 0014 DMA channel 1 current address register 0xB010 0018 D...

Page 99: ... enable and IRQ register on page 4 18 LCD brightness register on page 4 18 LCD enable register on page 4 18 PLD version register on page 4 19 GPIO register on page 4 19 Touch screen register on page 4 19 4 3 1 Interrupt flag register The interrupt flag register PLD_INT 0x10000000 contains six bits that indicate the source of the interrupt request that caused an interrupt to be signalled on the GPI...

Page 100: ... COM2_IRQ Indicates a change of state of COM2 either when a cable is connected or disconnected Also indicates when COM2 has valid signal levels and is ready to communicate 3 COM1_IRQ Indicates a change of state of COM1 either when a cable is connected or disconnected Also indicates when COM1 has valid signal levels and is ready to communicate 2 CDC_IRQ Indicates when an interrupt is generated FPGA...

Page 101: ...supply not present 1 external supply present 4 PWR_MODE Selects the power supply operating mode 0 PFM 1 PWM 3 PLD_S4_ON Enable disables the switched bias voltage for the monochrome LCD interface 0 disabled 1 enabled 2 PLD_S3_ON Enable disables the 9V LCD backlight supply LCD_OUT3 0 disabled 1 enabled 1 PLD_S2A_ON Enable disables the 3 3V supply output LCD_OUT2 used by the LCD 0 disabled 1 enabled ...

Page 102: ...witches 4 3 6 IrDA enable register The IrDA enable register PLD_IrDA 0x10000014 contains one active bit bit 0 which is used to enable disable the IrDA port transceiver 0 IrDA port disabled 1 IrDA port enabled Table 4 11 PLD input output register Bit Name Function 6 PLD_BOOTSEL read only This bit indicates the setting of the BOOTSEL switch see Setting the switches on page 2 3 5 PLD_DEVMODE read onl...

Page 103: ... the COM2 interrupt indicated in the PLD_INT register 1 COM2_SENSE read only When set indicates a cable connection or disconnection from COM2 caused the COM2 interrupt indicated by the PLD_INT register 0 COM2_EN This bit is used to enable disable the COM2 port transceiver 0 disabled 1 enabled Table 4 13 PLD COM1 enable register Bit Name Function 2 COM1_RDY read only When set indicates that the COM...

Page 104: ... The LCD enable register PLD_LCDEN 0x10400008 contains one active bit bit 0 used to switch a monochrome display ON or OFF when fitted Write a 1 to enable the LCD display write a 0 to disable the LCD display Table 4 14 FPGA codec register Bit Name Function 4 CODEC_IRQ3 This bit is only used if the FPGA is fitted 3 CODEC_IRQ2 This bit is only used if the FPGA is fitted 2 CODEC_IRQ1 This bit is only ...

Page 105: ... Write 0 to TCH_EN to disable the interface and enable the PENIRQ interrupt 2 Wait for an interrupt is indicated by a 1 in TCH_nPENIRQ bit 3 When an interrupt is received write a 1 to TCH_EN to enable the interface and disable the PENIRQ interrupt and then commence transactions with the ADS7843 4 When the transaction is complete write a 0 to TCH_EN to disable the interface and re enable the PENIRQ...

Page 106: ...and write to individual bits within the internal registers Messages are also used by the keyboard controller to report events and to respond to reads and writes by the host Each message comprises a header a command or a report identifier a message body if necessary a Longitudinal Redundancy Check LRC The header identifies the message type and is followed by a byte containing a command code or regi...

Page 107: ...tes a the number data bytes contained in the message body The body length can vary between 2 and 32 bytes Table 4 18 Message type summary Message type Message header Message length Commands from the host Simple commands 0x80 3 bytes Write register bit 0x81 4 bytes Read register bit 0x82 4 bytes Write register 0x83 4 bytes Read register 0x84 4 bytes Write block 0x85 5 to 36 bytes Read block 0x86 5 ...

Page 108: ... register at offset 255 in both banks This is used to select the bank to be accessed To access bank 1 registers you must first write 1 to the page number register To revert back to page 0 you must write 0 to the page number register The default is bank 0 All other values written to this register are ignored Individual registers in the bank are selected by the register offset value contained in the...

Page 109: ...0 GPIO pins are used for data transfers and interface timing between the SA 1100 and keyboard controller Keyboard controller host writes Figure 4 3 shows the timing for host writes to the keyboard controller Figure 4 3 SPI master timing host writes to the keyboard controller Host writes to the keyboard controller are as follows Host transfers to the keyboard controller start with the assertion of ...

Page 110: ...tween the start of one byte transfer and the start of the next After the last byte is transferred the host de asserts PLD_SPI_nCS0 to indicate that the transfer is complete In response the keyboard controller de asserts KEY_nATN A new transfer can begin 120µs after the de assertion of KEY_nATN Note The signals are described in SPI bus signal summary on page 3 30 Keyboard controller host reads and ...

Page 111: ...I bus A new transfer can begin 120µs after the de assertion of KEY_nATN 4 4 6 Keyboard controller interrupts The keyboard controller asserts the signal KEY_nATN when any of the Human Input Device HID manager blocks are enabled and detect certain events The KEY_nATN signal is used by the system controller PLD to assert the keyboard interrupt which is connected to the GIO0 pin of the SA 1100 The int...

Page 112: ... 4 6 Pointing device report Report block These are generated by the direct report manager using a report block message This can be used to relay data generated by an external PS 2 device Figure 4 7 shows the format of a report block Figure 4 7 Report block JP19 can used to connect an external mouse and keyboard Header 0x87 X displacement Y displacement Z displacement LRC Xs Xs R A MB RB LB Header ...

Page 113: ...m data audio data and register contents are shown in Table 4 19 Table 4 19 UCB SIB frame format summary Bit SIBDin definition SIBDout definition 63 48 Control register write data 15 0 bit 0 MSB Control register read data 15 0 bit 0 MSB 47 32 Telecom input path data 15 0 bit 0 MSB 14 MSB bits are read Telecom output path data 15 0 bit 0 MSB bits 15 14 are 0 31 Telecom valid sample flag Telecom vali...

Page 114: ... which are selected using bits 20 17 in the SIB subframe The data for the addressed register is carried by bits 63 48 Table 4 20 provides a summary of the UCB1200 register For details of these register please refer to the UCB1200 Data Sheet CPU_UCB_CLK CPU_UCB_FRM CPU_UCB_TXD CPU_UCB_RXD bit 0 bit 1 bit 2 bit 3 bit 62 bit 63 bit 64 bit 65 bit 126 bit 127 bit 0 Table 4 20 UCB1200 register summary A...

Page 115: ...mple GPIO8 is used as a DAA off hook signal see General purpose input output pin block on page 3 41 4 5 5 UCB1200 interrupts The UCB1200 interrupt request signal UCB_IRQ is routed to the interrupt controller block of system controller PLD and then to the interrupt on the GPIO1 pin of the SA 1100 The interrupt handler must read the PLD interrupt register to determine the source of any interrupt on ...

Page 116: ...ghts reserved ARM DUI 0122A audio and telecom chip detect ADC ready signal tspx_low tsmx_low These sources are enabled acknowledged and cleared by accessing the interrupt rising and falling edge registers and the interrupt status clear register within the UCB1200 ...

Page 117: ... intelligent interface controller Data transfers are handled using a message based protocol The SPI implementation uses a subset of the MMC protocol Three types of messages are used command these are always 6 bytes in length as shown in Figure 4 9 and include a 7 bit CRC checksum The checksum is ignored in SPI mode Commands are transferred serially on the CPU_SPI_TXD signal response responses are ...

Page 118: ...le 4 21 MMC register in SPI mode Name Size bytes Description CID 16 Card identification data CSD 16 Card specific data OCR Operation condition register optional Table 4 22 MMC command summary SPI Index Name Function CMD0 GO_IDLE_STATE Reset card to idle state CMD1 SEND_OP_COND Request and confirm operating conditions CMD9 SEND_CSD Request card to send CSD data CMD10 SEND_CID Request card to send I...

Page 119: ... to the documentation supplied by your card vendor CMD30 SEND_WRITE_PROT Request card write protection status CMD32 TAG_SECTOR_START First sector in erase list CMD33 TAG_SECTOR_END Last sector in erase list CMD34 UNTAG_SECTOR Remove sector from erase list CMD35 TAG_ERASE_GROUP_START First group in erase list CMD36 TAG_ERASE_GROUP_END Last group in erase list CMD37 UNTAG_ERASE_GROUP Remove group fr...

Page 120: ... byte reducing the delay before it returns the acquired data Table 4 23 defines the bit assignment in a control byte from the SA 1100 Table 4 23 Control byte Bit Name Function 7 S Start bit always 1 6 4 A2 0 Channel select bits 001 X 101 Y 010 No function on The P1100 110 No function on The P1100 3 MODE Selects 12 bit or 8 bit conversion 0 12 bits 1 8 bits 2 SER DFR Selects single ended or differe...

Page 121: ...bit in the PLD_TCH register HIGH see Touch screen register on page 4 19 When the transaction is completed you must disable the interface to the ADS7843 and enable the PENIRQ interrupt by setting the TCH_EN bit LOW The transaction between the CPU and ADS7843 is as follows The CPU enables the interface by setting the TCH_EN bit in the PLD_TCH register HIGH During the first eight clock cycles the con...

Page 122: ...ol byte on the 15th clock cycle for 12 bit conversion or on the 11th clock for 8 bit conversions The CPU disbables the interface by setting the TCH_EN bit LOW Note The SPI bus timing for the ADS7843 differs from that used for the keyboard controller in that for the ADS7843 CPU_SPI_SCLK idles LOW and is sampled on the rising edge ...

Page 123: ...4 MMC Connector JP14 on page A 5 ADS7843 Touchscreen Interface JP15 on page A 6 JTAG Interface connector JP18 on page A 7 Auxiliary PS2 Interface JP19 on page A 8 Auxiliary SPI Interface Connector JP21 on page A 9 TFT color connector JP23 on page A 10 Serial port connectors on page A 11 UCB1200 DAA modem interface JP37 on page A 13 Distribution panel connectors on page A 14 Note The abbreviation N...

Page 124: ...ace 8 JP9 0 1 HDRx3 Keyboard controller lid switch sense 13 JP10 Hex rotary SW Keyboard controller GPIO 13 JP11 DF13 5P 125V Keyboard controller GPIO interrupt 13 JP14 MMC_conn MMC 16 JP15 DF13 4P 125V ADS7843 touch screen 16 JP16 Plated through hole SPI_CS2 for 2nd MMC 16 JP17 0 1 HDRx2 RESET 16 JP18 DF13 8P 125V JTAG 16 JP19 DF13 10DP 125V Keyboard controller PS2 interfaces 16 JP20 PCR 128FDNG1 ...

Page 125: ... DAA 8 JP38 DF13 15P 125H Distribution board keyboard and loudspeaker 15 JP39 DF13 15P 125H Distribution board keyboard 15 JP40 DF13 15P 125H Distribution board LEDs PS2 port and reset 15 JP42 DF13 4P 125H Distribution board microphone 15 JP46 StereoJack External microphone 8 JP47 StereoJack External headphones 8 JP48 0 1 HDRx2 Microphone power 8 JP49 StereoJack AC97 audio 15 JP50 0 1 HDR1x11 AC97...

Page 126: ...Limited 2000 All rights reserved ARM DUI 0122A A 2 UCB1200 Touchscreen Interface JP3 Table A 2 shows the pinout of JP3 Table A 2 JP3 pinout Pin Function 1 UCB_TSPY Positive Y 2 UCB_TSPX Positive X 3 UCB_TSMY Negative Y 4 UCB_TSMX Negative X ...

Page 127: ...UI 0122A Copyright ARM Limited 2000 All rights reserved A 5 A 3 MMC Connector JP14 Table A 3 shows the pinout of JP14 Table A 3 JP14 pinout Pin Function 1 PLD_SPI_nCS1 2 BUF_SPI_TXD 3 GND 4 3V 5 BUF_SPI_CLK 6 GND 7 BUF_SPI_RXD ...

Page 128: ...6 Copyright ARM Limited 2000 All rights reserved ARM DUI 0122A A 4 ADS7843 Touchscreen Interface JP15 Table A 4 shows the pinout of JP15 Table A 4 JP15 pinout Pin Function 1 Positive Y 2 Positive X 3 Negative Y 4 Negative X ...

Page 129: ...right ARM Limited 2000 All rights reserved A 7 A 5 JTAG Interface connector JP18 Table A 5 shows the pinout of JP18 Table A 5 JP18 pinout Pin Function 1 3V 2 JTAG_nRESET 3 BUF_PLD_TDO 4 JTAG_TMS 5 JTAG_TDI 6 JTACK_TCK 7 SYSTEM_nRESET 8 GND ...

Page 130: ...ts reserved ARM DUI 0122A A 6 Auxiliary PS2 Interface JP19 Table A 6 shows the pinout of JP19 Table A 6 JP19 pinout Pin Function 1 PS2_0DAT 2 PS2_EN 3 PS2_0CLK 4 PS2_IDAT Internal PS2 device 5 PS2_1DAT 6 PS2_ICLK Internal PS2 device 7 PS2_1CLK 8 3V 9 GND 10 GND ...

Page 131: ... rights reserved A 9 A 7 Auxiliary SPI Interface Connector JP21 Table A 7 shows the pinout of JP21 Table A 7 JP21 pinout Pin Function Pin Function 1 BUF_SPI_RXD 6 3V 2 PLD_SPI_nCS7 7 PLD_SPI_nCS5 3 PLD_SPI_TXD 8 GND 4 GND 9 PLD_SPI_nCS6 5 BUF_SPI_CLK 10 PLD_SPI_nCS4 ...

Page 132: ...ine Clock Hsync 19 GND 4 LCD_FCLK Frame Clock Vsync 20 Tied LOW Blue LSB 5 GND 21 LCD_DD_0 Blue 1 6 Tied LOW Red LSB 22 LCD_DD_1 Blue 2 7 LCD_DD_11 Red 1 23 LCD_DD_2 Blue 3 8 LCD_DD_12 Red 2 24 LCD_DD_3 Blue 4 9 LCD_DD_13 Red 3 25 LCD_DD_4 Blue 5 10 LCD_DD_14 Red 4 26 GND 11 LCD_DD_15 Red 5 27 LCD_BIAS ENAB 12 GND 28 3V3 13 LCD_DD_5 Green 0 29 3V3 14 LCD_DD_6 Green 1 30 Tied HIGH Horizontal Displa...

Page 133: ...outs for the serial port connectors A 9 1 COM1 JP30 Table A 9 shows the pinout of JP30 A 9 2 COM2 JP31 Table A 10 shows the pinout of JP31 Table A 9 JP30 pinout Pin Function 1 NC 2 UART1_RXD 3 CPU_UART1_TXD 4 NC 5 GND 6 NC 7 CPU_UART1_RTS 8 UART1_CTS 9 NC Table A 10 JP31 pinout Pin Function 1 NC 2 UART2_RXD 3 CPU_UART2_TXD 4 NC 5 GND 6 NC ...

Page 135: ... A 13 A 10 UCB1200 DAA modem interface JP37 Table A 11 shows the pinout of JP37 Table A 11 JP37 pinout Pin Function 1 AGND 2 UCB_TOUTP Telephone Out Positive 3 5V 4 UCB_TINP Telephone In Positive 5 UCB_DAA_OH Off Hook 6 UCB_DAA_MUTE Mute 7 NC 8 UCB_DAA_RI Ring Indicate 9 GND 10 3V ...

Page 136: ...ith the keybaord controller A 11 1 Keyboard controller connector 1 JP38 Table A 12 shows the pinout of JP38 The connector provides the keyboard row signals and speaker connections Table A 12 JP38 pinout Pin Function 8 KBD_ROW6 1 UCB_SPKR_P 2 UCB_SPKR_N 3 GND 4 KBD_COL15 5 KBD_COL14 6 KBD_COL13 7 KBD_ROW7 9 KBD_ROW5 10 KBD_ROW4 11 KBD_ROW3 12 KBD_ROW2 13 KBD_ROW1 14 KBD_ROW0 15 GND ...

Page 137: ...oller connector 2 JP39 Table A 13 shows the pinout of JP39 The connector provides the keyboard column signals Table A 13 JP39 pinout Pin Function 1 GND 2 KBD_COL12 3 KBD_COL11 4 KBD_COL10 5 KBD_COL9 6 KBD_COL8 7 KBD_COL7 8 KBD_COL6 9 KBD_COL5 10 KBD_COL4 11 KBD_COL3 12 KBD_COL2 13 KBD_COL1 14 KBD_COL0 15 3V ...

Page 138: ...P40 Table A 14 shows the pinout of JP40 The connector provides signals for the LEDs mouse pointer and reset button in the keyboard housing Table A 14 JP40 pinout Pin Function 1 3V 2 SYSTEM_nRESET 3 PLD_nRST_OUT 4 PS2_EN 5 3V 6 PS2_ICLK 7 PS2_IDAT 8 GND 9 CPU_GPIO25 10 GND 11 KBD_LED3 12 KBD_LED2 13 KBD_LED1 14 KBD_LED0 15 GND ...

Page 139: ...ference ARM DUI 0122A Copyright ARM Limited 2000 All rights reserved A 17 A 11 4 Microphone connector JP42 Table A 15 shows the pinout of JP42 Table A 15 JP42 pinout Pin Function 1 UCB_MIC_GND 2 UCB_MIC 3 GND 4 5V0 ...

Page 141: ...ons It contains the following sections Power considerations on page B 2 System expansion on page B 3 SPI expansion on page B 4 Flash memory expansion on page B 5 UCB1200 expansion on page B 6 FPGA and AC97 CODEC Interface on page B 7 Connector support for expansion on page B 8 PLD enhanced clocking on page B 9 GPIO support for expansion on page B 10 ...

Page 142: ...e able to supply a limited additional loading as shown in Table B 1 These figures can vary with the number of items within the P1100 system that are active and should be used for guidance only Table B 1 Power supply support for expansion Rail Total Used Available 3V 1A 500mA Max 500mA 3V3 350mA 100mA 250mA 5V 300mA 100mA 200mA 9V 3600mW 1V5 200mA 100mA 100mA ...

Page 143: ... fitted to allow a second board to be attached to the underside of the P1100 CPU board It provides an interface that is compatible with the Intel SA 1101 Evaluation Board with access to address and data buses PCMCIA control signals GPIO buffered address and data buses system control signals and DRAM strobes Note This connector is not fitted as standard ...

Page 144: ...ote The chip select signal PLD_SPI_nCS7 is reserved as a null select and should not be used for expansion see Using the SPI chip selects on page 3 30 Table B 2 SPI chip select assignment CPU_SPI_CS 2 0 Chip select Device 000 PLD_SPI_nCS0 Keyboard controller 001 PLD_SPI_nCS1 MMC Socket 1 010 PLD_SPI_nCS2 MMC Socket 2 011 PLD_SPI_nCS3 Touch screen controller 100 PLD_SPI_nCS4 System expansion 101 PLD...

Page 145: ...ited 2000 All rights reserved B 5 B 4 Flash memory expansion The buffered address and data busses along with PLD control outputs are routed to the expansion connector JP20 This allows connection of additional ROM Flash or provision for an alternate boot path ...

Page 146: ...provide a Data Access Arrangement DAA interface four ADC inputs a 10 bit GPIO port The DAA interface enables you to add a DAA to the P1100 to allow connection to telephone networks The interface uses GPIO pins to provide Mute Ring Indicate RI and Off Hook OH signals Connection is made at a single dual row 10 pin DF13 type connector JP37 Note The connector JP37 is not fitted as standard ...

Page 147: ...t has finished configuration The configuration PROM is placed in a socket allowing its removal for programming Most of the unused IO pins of the FPGA are connected to a 40 way expansion connector JP26 for use by alternate functions The AC 97 codec interface logic essentially consists of an interface to the SA 1100 memory bus 4 transmit FIFOs 4 receive FIFOs serializing plus control and muxing logi...

Page 148: ... expansion connectors on the rear of the compact module enclosure with the blanking plate removed The signal traces to these connectors appear on JP50 and enable you to connect for example an audio codec and modem that you have added to the system Figure B 1 Modem and audio expansion connectors Note These connectors are not fitted on the standard product variant ...

Page 149: ...er PLD code currently used in the P1100 design assumes that the PLD is not an enhanced clocking device This means that the code must steal pins to use as clocks for the internal registers If an anhanced clocking device is used then these pins can be used The pins affected by this are pin 92 CDC_IRQ0 pin 83 CPU_RCLK_OUT pin 37 CPU_32KHz ...

Page 150: ...pansion connector The SA 1100 can provide a buffered divide by two version of the core clock on this pin as an alternate function The clock is currently unused on the SA 1100 and to save power need not be configured by the software It could be used by the PLD for high speed state machines or for latching transient data but is not used in the first release of the PLD GPIO27 CPU_32KHz This signal is...

Page 151: ...control 3 17 interrupt control 3 12 LED control 3 20 MMC interface 3 37 power supply 3 45 reset system 3 8 SA 1100 3 3 SPI bus 3 29 switch sensing 3 20 system 1 4 ARM Boot Switcher 2 7 ARM Developer Suite 1 8 ARM Firmware Suite 1 7 3 14 ARM publications xv ARM v4 architecture 3 2 Asynchronous serial ports 3 26 Audio codec 3 40 Audio connector expansion B 8 B Battery backup 3 47 power 3 46 sensing ...

Page 152: ... Flash memory expansion B 5 Further reading xv G General Purpose Input Output 3 2 General purpose switches 2 3 GPIO expansion B 10 PLD 3 19 UCB1200 3 41 GPIO register PLD 4 19 H Hardware reset 3 8 3 10 Hexadecimal switch 2 3 3 20 Hot swap capability MMC 3 37 I Idle mode 3 49 Initialization completion 2 8 Interface connectors 2 2 Interface control architecture 3 17 Interface enable 3 17 Interface e...

Page 153: ...set 3 8 3 9 Product feedback xvi Programming flash 3 24 the keybaord controller 4 20 touch screen controller 4 34 UCB1200 4 27 PSU_BATT_OK 3 48 PSU_VDD_FLT 3 48 R Register bank selection keyboard controller 4 22 Regulator mode control 3 45 Related publications xv Report block 4 26 Reset control 3 8 Reset management PLD 3 12 Reset signal summary 3 9 Response message MMC 4 31 S SA 1100 CPU overview ...

Page 154: ...rotocol 4 35 Touch screen controller ADS7843 3 38 Touch screen controller UCB1200 3 40 Touch screen register PLD 4 19 Typographical conventions xiii U UCB_ADCSYNC 3 42 UCB_ADSYNC 3 41 UCB_DAA_MUTE 3 41 UCB_DAA_OH 3 41 UCB_DAA_RI 3 41 UCB_LED 3 41 UCB1200 3 28 UCB1200 functional diagram 3 39 UCB1200 GPIO pin assignments 3 41 UCB1200 interrupts 4 29 UCB1200 registers 4 28 Using the GPIO pins UCB1200...

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Summary of Contents for Prospector P1100

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ARM Prospector P1100, User Manual, Page: 102 / 154

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Summary of Contents for Prospector P1100

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