Arbor Technology EmCORE-v7002, User Manual

Page: 55 / 57

Appendix
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4.1 I/O Map
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Address
0000h-0000Fh
0080h-009Fh
00C0h-00DFh
0020h, 0021h
00A0h, 00A1h
0040h-0043h
0044h-0047h
0060h-0064h
0070h-0073h
00F0h-00FFh
01F0h-01F7h
0274h-0277h
0279h , 0A79h
0295h , 0296h
02F8h-02FFh
0378h-037Ah
03B0h-03BFh
03C0h-03CFh
03D4h-03D9h
03F0h-03F7h
03F6h-03F6h
03F8h-03FFh
0400h-041F
04D0h-04D1h
0500h-053Fh
0800h-087Fh
0A00h-0A07h
0CF8h
0CFCh Description
Direct memory access controller
Programmable interrupt Controller
System timer
Keyboard controller
System CMOS/real time clock
Math Co-Processor
Primary IDE
ISAPNP Read Data Port
ISAPnP Configuration
SuperIO Configuration Port
COM_2 (If use)
Parallel Port (If use)
MDA/MGA
EGA/VGA
CGA CRT
Floppy Diskette
Primary IDE
COM_1 (If use)
South Bridge SMB
IRQ Edge/level control ports
South Bridge GPIO
ACPI
PME
PCI Configuration address
PCI Configuration Data
Appendix
- 51 -
Appendix
4
Chapter 4