AMI BIOS Utility
3-13
DRAM Timing Setting
The selections for this parameter are
60 ns, 70 ns,
and
Manual
.
If you select either
60 ns
or
70 ns
, the DRAM Timing subparameters
become non-configurable since BIOS automatically sets the values. Select
Manual
if you want to specify your own parameter settings.
FAST MA TO RAS# DELAY
This option specifies the wait state between the master address (MA) and row
address strobe (RAS) signals. The selections are
1 clock
and
2
clocks
.
EDO:SPM READ BURST TIMING
This parameter adjusts the read wait state for Extended Data Out (EDO)
DRAM and Standard Page Mode (SPM) DRAM. Every time the CPU reads
the second-level cache miss, it reads four continuous memory cycles on four
continues addresses from the EDO and SPM cache.
The selections for this parameter are
x444/X444, X333/X444,
X222/X333,
and
X3222/X333
. The value of
X
depends on the
DRAM Lead-off Timing parameter setting.
DRAM WRITE BURST TIMING
This parameter adjusts the write wait state between the second-level and the
DRAM cache. The second-level cache is processed through write-back
method and each cache write process consists of four continuous cache write
cycles.
The parameter settings are
X444, X333,
and
X222
. Faster DRAMs
require shorter wait states. The value of
X
depends on the DRAM Lead-off
Timing parameter setting.
FAST RAS TO CAS DELAY
This option specifies the wait state between the row address strobe (RAS) and
column address strobe (CAS) signals. The available settings are
3
clocks
and
2 clocks
.
DRAM LEAD-OFF TIMING
This option specifies the DRAM waiting time or the delay before data can be
accessed. Some DRAMs may require a longer delay to access data. The
selections are
11-7-3, 10-6-3, 11-7-4,
and
10-6-4
.
Summary of Contents for AP5VM
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