Hardware Installation
2-31
Warning
: Do not use SIMM and SDRAM DIMM
together unless you have 5V tolerance SDRAM (such as
Samsung or TI). The FPM/EDO operate at 5V while
SDRAM operates at 3.3V. If you combine them
together the system will temporary work fine; however
after a few months, the SDRAM 3.3V data input will be
damaged by 5V FPM/EDO data output line.
There is an important parameter affects SDRAM performance, CAS Latency
Time. It is similar as CAS Access Time of EDO DRAM and is calculated as
number of clock state. The SDRAM that AOpen had tested are listed below. If
your SDRAM has unstable problem, go into BIOS "Chipset Features Setup",
change CAS Latency Time to 3 clocks.
Manufacturer
Model
Suggested CAS
Latency Time
5V Tolerance
Samsung
KM416S1120AT-G12
2
Yes
NEC
D4516161G5-A12-7JF
2
No
Micron
MT4LC1M16E5TG-6
2
No
TI
TMS626162DGE -15
2
Yes
TI
TMS626162DGE M-67
3
Yes
The driving capability of new generation chipset is limited because the lack of
memory buffer (to improve performance). This makes DRAM chip count an
important factor to be taking into consideration when you install SIMM/DIMM.
Unfortunately, there is no way that BIOS can identified the correct chip count,
you need to calculate the chip count by yourself. The simple rule is: By visual
inspection, use only SIMM with chip count less than 24 chips, and use only
DIMM which is less than 16 chips.
Warning
: Do not install any SIMM that contains more
than 24 chips. SIMMs contain more than 24 chips
exceed the chipset driving specification. Doing so may
result in unstable system behavior.
Warning
: Due to loading issue, it is not recommended to
use x4 (bit) SDRAM chip.
Summary of Contents for AP5VM
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