Page 20 of 34
A8520E24A91 – User’s Manual
Release Date 02/27/12
Table 5 pin-out table, with references to chip pins
Pi
n
N
u
m
b
er
Pin Name
Pin Type
Description
C
C
25
9x
Pi
n
C
C
85
xx
Pi
n
1
GND
Common Ground
2
DNC
Do Not
Connect. Connecting this pin to anything will significantly affect the performance
of the module and may
void
the end users right, under FCC, to operate the module
3
GND
Common Ground
4
DNC
Power/Decoupling
Do Not
Connect. This pin should not be used unless deemed necessary in particular
noisy power supply environments, See "power supply consideration" section for more
information
5
VBAT
Analog Input
Battery voltage supervisor (threshold level programmable by external resistor to positive
battery terminal)
29
6
SCL, GIO10
Digital I/O
I2C master clock line. Must be connected to external pull-up, General-purpose digital I/O
pin 10
32
7
SDA, GIO11
Digital I/O
Digital I/O1 I2C master data line. Must be connected to external pull-up, General-purpose
33
8
GIO12
Digital I/O
General-purpose digital I/O pin 12
34
9
GIO13
Digital I/O
General-purpose digital I/O pin 13
35
10
XPAEN/PAEN
Digital Out
The CC85xx asserts this pin high to turn on the CC259x power amplifier for transmit. The
pin can be used to detect the radio state to synchronize other system events e.g. to
smooth out power consumption or minimize noise injection. A high indicates that the PA
is on. At no time will both XPAEN and XLNAEN be high at the same time.
5 36
11
XLNAEN/EN
Digital Out
The CC85xx asserts this pin high to turn on the CC259x low noise amplifier. The pin can
be used to detect the radio state to synchronize other system events e.g. to turn of
noise/switching sources for better sensitivity. At no time will both XPAEN and XLNAEN
be high at the same time.
6 38
12
GND
Common Ground
13
DNC
Digital I/O
Do Not Connect (future antenna diversity control or USB interface)
1
14
DNC
Digital I/O
Do Not Connect (future antenna diversity control or USB interface)
2
15
CS_N
Digital Input (Pull-up) Serial SPI configuration interface, active low chip select
3
16
SCLK
Digital I/O
Serial SPI configuration interface, clock input/output
4
17
MOSI
Digital I/O
Serial SPI configuration interface, master data input, slave data output
5
18
MISO, GIO0
Digital I/O
Serial SPI configuration interface, master data output, slave data input GIO0 output when
CS_N is deasserted. General-purpose digital I/O pin 0
6
19
GIO1
Digital I/O
General-purpose digital I/O pin 1, Configurable with PurePath™ Wireless Configurator
7
20
GIO2
Digital I/O
General-purpose digital I/O pin 2
8
21
GIO3
Digital I/O
General-purpose digital I/O pin 3, Configurable with PurePath™ Wireless Configurator
9
22
GND
Common Ground
23
RSTN
Digital Input (Pull-up) Active-low device reset
11
24
MCLK
Digital I/O
Digital I/O1 Master clock output for external audio devices (GIO4).
13
25
BCLK
Digital I/O
Digital I/O1 I2S/DSP audio interface bit clock (in/out) (GIO5).
14
26
WCLK
Digital I/O
Digital I/O1 I2S/DSP audio interface word clock (in/out) (GIO6).
15
27
AD0
Digital I/O
Digital I/O1 I2S/DSP audio interface data line 0 (in/out) (GIO7).
16
28
AD1
Digital I/O
Digital I/O1 I2S/DSP audio interface data line 1 (in/out) (GIO8).
17
29
AD2, GIO9
Digital I/O
Digital I/O2 I2S/DSP audio interface data line 2 (in/out), Configurable with PurePath™
Wireless Configurator
19
30
GND
Common Ground
31
HGM
Digital Input
Digital control pin. HGM=1 → CC259x LNA is in High Gain Mode (~10dB gain),
HGM=0 → CC259x LNA is in Low Gain Mode (~0dB gain). Can be used to avoid
overdriving the receiver in case the transmitter is in very close proximity to the receiver,
otherwise do not connect.
7
32
IOVDD
Power (I/O pins)
Digital power supply for the digital core, GIO's SPI, I2C and I2S (1.8V to 3.6V)
10
33
AVDD
Power (Analog)
Analog power supply connection for the Radio and PA/LNA (2.0V to 3.6V)
20
34
GND
Common Ground
