SD Interface
1-12
ADSP-BF707 EZ-KIT Lite Evaluation System Manual
SD Interface
The ADSP-BF707 processor has a secure digital (SD) interface that con-
sists of a clock pin, command pin, card detect pin, and an 8-bit data bus.
SoftConfig controls the connection of the card detect pin (
PA_08
) and a
GPIO pin used for write protect (
PB_07
). Refer to
for more details.
An example program is included in the ADSP-BF707 Board Support
Package.
Debug Interface
The EZ-KIT Lite provides a JTAG/SWD/SWO connection via connector
(
P3
), which is a 0.05” pitch header. An 8-bit trace connection also is avail-
able via connector (
P2
), although this is not supported at this time. See
Power-On-Self Test
The Power-On-Self-Test Program (POST) tests all EZ-KIT Lite peripher-
als and validates functionality as well as connectivity to the processor.
Once assembled, each EZ-KIT Lite is fully tested for an extended period
of time with POST. All EZ-KIT Lite boards are shipped with POST pre-
loaded into flash memory. The POST is executed by resetting the board
and pressing the proper push button(s). The POST also can be used as a
reference for a custom software design or hardware troubleshooting.
Note that the source code for the POST program is included in the
ADSP-BF707 Board Support Package along with the
readme.txt
file that
describes how the board is configured to run POST.
Summary of Contents for EZ-KIT Lite ADSP-BF707
Page 4: ......
Page 34: ...Reference Design Information 1 16 ADSP BF707 EZ KIT Lite Evaluation System Manual ...
Page 60: ...Connectors 2 26 ADSP BF707 EZ KIT Lite Evaluation System Manual ...
Page 68: ...A 8 ADSP BF707 EZ KIT Lite Evaluation System Manual ...
Page 85: ...Index I 4 ADSP BF707 EZ KIT Lite Evaluation System Manual ...
