Preliminary Technical Data
EVAL-ADF4602EB1Z
Rev. PrC | Page 11 of 37
AD9863 BASEBAND INPUT/OUTPUT
The AD9863 digital baseband inputs and outputs accommodate
a variety of modes for data transfer. Two 12-bit buses, an upper
bus (U12), and a lower bus (L12) are use to transfer the dual
channel 12-bit ADC data and dual channel 12-bit DAC data by
means of interleaved data, parallel data, or a mix of both. A
detailed description of the modes is outside the scope of this
document, but the modes that apply to the evaluation board are
discussed. For more information see the AD9863 datasheet.
The AD9862 configuration options for the evaluation board are
as follows:
a.
Full Duplex (FD) mode. One 12-bit interleaved Rx
data bus L12, and one 12-bit interleaved Tx data bus,
U12
b.
Half Duplex 24 (HD24) mode. Two 12 bit parallel Rx
data buses or two 12-bit parallel Tx data buses.
For FDD (Frequency Division Duplex) WCDMA, the AD9863
is required to operate transmit and receive channels
simultaneously. This requires the use of FD mode on the
AD9863. For ease of test reasons, HD24 mode is also allowed
on the evaluation board. This allows the user to use two 12-bit
parallel buses to evaluate the transmit or receive channel
individually. This can be useful if for example the user does not
have interleaved Tx data available for initial tests.
Jumper Settings
Input/output buffers U25 and U27 are bi-directional to allow
the various configurations. The “Board Setup” tab in the
evaluation software allows the user to select which mode of
operation is required. The default setting is FD Mode 1. A
thorough description of each mode is given in Table 4.
Comments
FD Mode 1
Interleaved Rx data appears on upper forty pins of connector J8(1:40) from buffer U27.
Interleaved Tx data should be provided on forty pin connector J9 with Txsync on pin J9-12.
FD Mode 2
Interleaved Rx data appears on upper forty pins of connector J8(1:40) from buffer U27.
Interleaved Tx data should be provided on lower pins of connector J8(41:80). Resistor R53
should be populated with 0Ω, and Txsync provided on pin J8-72.
HD24 Mode Tx
Two 12 bit parallel I/Q data should be provided on 80 pin connector J8.
HD24 Mode Rx
Two 12 bit parallel I/Q data appears on 80 pin connector J8
Table 4. Jumper Settings for various AD9863 I/O configurations
AD9863 TRANSMIT SECTION
Digital Baseband Data
The baseband data can have a number of formats as described
in the AD9863 Baseband input/output Section. For
evaluation/test purposes of the board, the R&S AMIQ-04
arbitrary waveform generator was used to provide the baseband
data. The accompanying WINIQSIM software calculates and
loads the necessary WCDMA test models.
DAC Outputs
The AD9863 TxDAC core provides dual, differential,
complimentary current outputs generated from the 14-bit data.
External resistor R107 sets the full scale output current I
OUTFSMAX
from the TxDAC.. The relationship between I
OUTFSMAX
and R
SET
is:
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
×
=
SET
OUTFSMAX
R
V
I
23
.
1
67
On the evaluation board R
SET
this is set to 3.9kΩ giving the
optimal dynamic setting for the TxDACs.
The ADF4602 transmit baseband inputs accept a 1.2V common
mode input signal with 1Vpk-pk differential swing. The
configuration in Figure 14 can be used to provide this.
DAC1
R
L
DAC2
I INPUT
Q INPUT
ADF4602
AD9863
R
L
R
DC
R
DC
R
DC
R
DC
Figure 14. AD9863 TxDAC to ADF4602 baseband input interface
Resistors R
DC
setup the DC common mode voltage, while load
resistor R
L
sets the differential swing. The differential swing V
diff
is a function of the load resistor R
L
and the DAC full scale
current I
OUTFSMAX
according to:
