Preliminary Technical Data
EVAL-ADF4602EB1Z
Rev. PrC | Page 7 of 37
Board LDO Regulator Control
The on-board regulators are controlled from the main software
panel. Each regulator can be individually turned on or off as
shown in Figure 10. This is useful for observing the current
drawn by each device. For example when measuring the current
drawn in receive, the on-board buffer and PA supplies can be
powered down in order to view the current drawn by the
ADF4602 and AD9863 alone.
Figure 10. On-board LDO regulator Control
Loading and Saving Settings
Register settings for both the ADF4602 and AD9863 can be
saved individually for future use. This feature is useful as there
are many registers in both devices and programming each
individually is time consuming.
To save settings, click on
File->Save ADF4602 setup
or
Save
AD9863 setup
. Loading saved files is achieved by clicking on
the corresponding
Load
option.
When a file is loaded, the filename is shown in the
Current
Setup
frame in the top left hand corner of the screen. Having
loaded settings files for each device, a
Load All
should be
performed on both devices to initialize them correctly.
Help
Hovering the mouse pointer over the register text will give a
description of the register function.
ADF4602 R0.1 Silicon Soft Reset
A soft reset must be performed on the ADF4602 R0.1 silicon
after power up for correct operation. To do this, load all
registers, then toggle the soft reset button in register 2, and then
load all registers again.
Default Configurations
A number of default software configurations are provided for
easy setup of the evaluation board. It is recommended that these
be used when first using the evaluation board. Table 1 shows the
files that come with the evaluation software.
Compatibility with Visual Analog software
The Visual Analog software and the EVAL-ADF4602EB1Z
software should not be operated simultaneously on a single
PC/laptop. This is due to the incompatibility of the USB drivers.
The Visual Analog software must be run on a separate PC.
File Name
Mode
Description
ADF4602_tx.txt
ADF4602
Transmit
ADF4602 Transmit @
2140MHz. Output power =
+13dBm. Receive section
powered down. RF
switches set appropriately
ad9863_tx_FD
mode.txt
AD9863
Transmit FD
Mode
AD9863 TxDACs
powered up. TxPGA
gain = max. ADCs
powered down. PLL
multiplier = 2x.
Interpolation control =
2x. Tx input data
interleaved
ADF4602_rx.txt
ADF4602
Receive
ADF4602 Receive @
1950MHz. Rx gain = 45.
Transmit section
powered down. RF
switches set
appropriately
ad9863_rx_FD
mode_alt_timin
g.txt
AD9863
Receive FD mode
AD9863 ADCs powered
up. Sample rate =
19.2MHz. Rx output
data interleaved
ad9863_rx_24H
Dmode_alt_timi
ng.txt
AD9863
Receive HD24
mode
AD9863 ADCs powered
up. Sample rate =
19.2MHz. Rx output
data 2 x 12-bit parallel
ADF4602_
Powerdown.txt
ADF4602
Powerdown
ADF4602 LDO’s
powered up. Receive
and Transmit powered
down. Reference
output buffers powered
down
AD9863_
powerdown.txt
AD9863
Powerdown
AD9863 TxDAC, ADCs,
PLL powered down
Table 1. Coniguration files descriptions
