Preliminary Technical Data
EVAL-ADF4602EB1Z
Rev. PrC | Page 13 of 37
discussed. See the AD9863 datasheet for a more complete
description of the modes of operation.
The AD9863 is configured in alternate timing mode. In this
mode, all on-chip clocks are derived from the signal provided at
the CLKIN2 pin.
On the evaluation board, this can be provided by either of the
ADF4602 reference output signals (26MHz or 19.2MHz), or by
an external reference clock applied through SMA J14. The
default configuration is to use the 19.2MHz buffered output
from the ADF4602. This is connected to pin 47 (CLKIN2) on
the AD9863.
In the recommended full duplex configuration, the PLL
multiplier is set to 2x. This gives a PLL output frequency of
38.4MHz. The ADC is clocked at half this frequency by
enabling the ADC divide by 2 bit. IFACE3 provides the
necessary clock for the interleaved data (38.4MHz), and
IFACE2 provides the Rxsync signal to indicate which of I or Q
data is on the bus at any time.
On the transmit side, the PLL output of 38.4MHz is used to
clock the DAC. Interpolation is set to 2x in order to suppress
DAC images.
The transmit data input rate is controlled by IFACE3. This clock
is available at pin 2 of connector J9, and also at SMA J10. This
should be used as the clock for the external arbitrary waveform
generator.
The ADC clock rate, DAC clock rate, PLL and interpolator
settings are software controllable. This allows the user to easily
change the clocking configuration of the AD9863 and observe
the changes in performance and power to find the optimum
setting.
Figure 15. EVAL-ADF4602EB1Z connected to HSC-ADC-EVALB-DC data acquisition board
