Analog Devices EVAL-ADAU1777Z, User Manual

Page: 18 / 26

EVAL-ADAU1777Z User Guide UG-1055
Rev. 0 | Page 17 of 25
EVALUATION BOARD SCHEMATICS AND ARTWORK
ANAL
O
G
I
NP
UT
0
ANAL
O
G
I
NP
UT
1
S
T
E
RE
O
ANAL
O
G
I
NP
UT
S
2
AND 3
M
O
NO
DI
F
F
E
RE
NT
IAL
O
UT
P
UT
RI
G
HT
M
O
N
O
D
IFFE
R
E
N
TI
A
L O
U
TP
U
T LE
FT
S
T
E
R
E
O
S
IN
G
L
E
-E
N
D
E
D
O
UT
P
UT
S
E
L
F
B
OOT
ON
OF
F
A
P
P
L
Y
S
H
U
N
T
F
O
R
/
P
D
S
T
E
R
E
O
O
U
T
P
U
T
C6
0.
10µ
F
C3
22p
F
C
36
10µ
F
C
35
10µ
F
R
41
49.
9kΩ
C
33
O
P
E
N
J18
R
47
49.
9kΩ
C
38
O
P
E
N
J20
R
52
49.
9kΩ
C
43
O
P
E
N
R
55
49.
9kΩ
C
46
O
P
E
N
J22
R
53 0Ω
R
54
0Ω
R
42 0Ω
R
48
0Ω
R
44
2kΩ
R
45
2kΩ
C
34
2.
2µ
F
C
37
2.
2µ
F
J19
J21
R
57
49.
9kΩ
R
56
49.
9kΩ
J23
R
49
O
P
E
N
R
51
O
P
E
N
R
43
O
P
E
N
R
46
O
P
E
N
1
A0
2
A1
3
A2
4
GN
D
8
V
C
C
7
W
P
6
S
C
L
5
S
D
A
U2
M
24C
32-
F
J8
J12
S
2
S
P
D
T R
24
10Ω
R2 O
P
E
N
C
42
10µ
F
R3
100Ω
C
39
1.
0µ
F
R
10
1kΩ
J13
J16
J17
1 2
J11
R
50
2kΩ
J15
Y
1
12.
288M
H
z
R4
33R
2
C
40
2.
2µ
F
TP
5
1
2
3 6
5
4
12
11
10
7
8
9
S
7
4
P
DT
_
S
L
IDE
_
BBM
R
13
0Ω
R
12
0Ω
R
11
0Ω
R9
0Ω
C
15
O
P
E
N
C4
O
P
E
N
+
C45
470µF
+ C44
470µF
C
17
10µ
F
C
19
10µ
F
R5
33R
2
R6
33R
2
R7
33R
2
R8
33R
2
C
41
10µ
F
A
B
1
2
3
J14
A7
IOVD D
B7
S
C
L/
S
C
LK
C7
M
ICBI
AS
0
D7
M
ICBI
AS
1
E7
AVDD
F7AG
ND
A6
X
TA
LI
/M
C
LK
I
B6
S
D
A
/M
IS
O
C6
ADDR0
/S
S
D6
ADDR1
/M
O
S
I
E
6
S
E
L
F
B
OOT
F6
CM
A5
X
TA
LO
B5
D
M
IC
0_1/
M
P
4
E
5
AI
N0
F5
AI
N1
A4
ADC_
S
DAT
A1
/CL
K_
O
UT
/M
P
6
B4
D
M
IC
2_3/
M
P
5
E
4
AI
N3
F4
AI
N2
A3
ADC_
S
DAT
A0
/P
DM
O
UT
/M
P
1
B3
DAC_
S
DAT
A/
M
P
0
E
3
P
D
F3AG
ND
A2
BCL
K/
M
P
2
B2
L
RCL
K/
M
P
3
C2
RE G_OU T
D2
HP
O
UT
RN/
L
O
UT
RN
E
2
H
P
O
U
TLP
/LO
U
TLP
F2
AVDD
A1DG
ND
B1
DVDD
C1
HP
O
UT
RP
/L
O
UT
RP
D1
AVDD
E1
AGND
F1
H
P
O
U
TLN
/LO
U
TLN
U1
A
D
A
U
1777_W
L
C
S
P
C1
47.
0µ
F
C2
47.
0µ
F
R
58
O
P
E
N
R
59
O
P
E
N
C5
22p
F
C
14
0.
10µ
F
C
12
0.
10µ
F
C
11
0.
10µ
F
C
13
0.
10µ
F
C9
0.
10µ
F
C7
0.
10µ
F
C
25
0.
10µ
F
M
ICBI
AS
0
M
ICBI
AS
0
IOV
D
D
S
C
L/
S
C
LK
S
D
A
/M
IS
O
M
ICBI
AS
0
M
ICBI
AS
1
S
D
A
/M
IS
O
S
C
L/
S
C
LK
ADDR1
/M
O
S
I
ADDR0
/S
S
ADC_
S
DAT
A1
/CL
KO
UT
/M
P
6
E
X
T_
M
C
LK
M
ICBI
AS
1
LE
FT_
IN
R
IGH
T
_
IN
LE
FT_
IN
R
IGH
T
_
IN
DV
DD
IOV
D
D
IOV
D
D
D
M
IC
_0_1
D
M
IC
_2_3
IOV
D
D
L
RCL
K/
M
P
3
BCL
K/
M
P
2
DAC_
S
DAT
A/
M
P
0
ADC_
S
DAT
A0
/P
DM
O
UT
/M
P
1
BRD_
RE
S
E
T
V
D
D
DV
DD
15054-050
Figure 50. EVAL-ADAU1777Z Evaluation Board Schematic—Digital and Analog Input/Output, Master Clock Generation