EVAL-AD4111SDZ
User Guide
UG-1124
Rev. A | Page 19 of 26
VI
N
: U
se
thi
s
pin
to
pow
er
th
e
SD
P
re
qui
res
4-
7V
2
00m
A
VI
O
: U
SE
to
set
IO
v
ol
ta
ge
m
ax
dr
aw
2
0m
A
BM
OD
E1
: P
ul
l u
p
w
ith
a
1
0K
re
si
sto
r to
s
et
SD
P t
o
bo
ot
fro
m
a
S
PI
F
LA
SH
on
the
da
ugh
te
r boa
rd
EEPRO
M
-S
W
/USB
ID
SD
P
CO
NN
ECTO
R
VI
N
: U
se
thi
s
pi
n
to
pow
er
th
e
SD
P
requi
res
5V
2
00m
A
Boa
rd
ID
E
EP
R
O
M
(24
LC
32)
m
us
t be
o
n
I2C
bus
0,
I2
C
b
us
1
is
c
om
m
on
acr
os
s
bo
th
c
onn
ec
to
rs
o
n
SD
P
- P
ul
l up
re
si
st
or
s
requ
ired
BM
OD
E1
: P
ul
l u
p w
ith
a
1
0K
re
si
sto
r to
s
et
SD
P t
o
bo
ot
fro
m
a
S
PI
F
LA
SH
on
the
da
ugh
ter
boa
rd
(c
on
ne
cte
d
to
b
la
ck
fin
G
PIO
- u
se
I2
C
_0
fi
rs
t)
M
ai
n
I2C
bus
SD
P
C
on
nect
or
S
ch
em
e,
R
.R
. 1
5/
04/
11
Pow
er
the
bo
ar
d
from
S
D
P-
B
Pow
er
th
e
boar
d
fro
m
A
D
uC
M
3029
ev
al
(P
ul
led
up
on
B
la
ck
fin
S
D
P)
*N
C
o
n
BL
AC
KFI
N
S
D
P
*
*
*
*
*
*
*
*
*
*
*
*
*
TI
M
ER
S
IN
PU
T/
O
U
TP
U
T
GE
N
ER
AL
I2
C
SP
I
SP
O
R
T
PO
R
T
PA
R
ALLE
L
SD
P
ST
AND
ARD
CO
N
NE
C
TO
R
12
0
NC
11
9
NC
11
8
GN
D
11
7
GN
D
11
6
VI
O
(+3
.3
V)
11
5
GN
D
11
4
PA
R_
D2
2
11
3
PA
R_
D2
0
11
2
PA
R_
D1
8
11
1
PA
R_
D1
6
11
0
PA
R_
D1
5
10
9
GN
D
10
8
PA
R_
D1
2
10
7
PA
R_
D1
0
10
6
PA
R_
D8
10
5
PA
R_
D6
10
4
GN
D
10
3
PA
R_
D4
10
2
PA
R_
D2
10
1
PA
R_
D0
10
0
PA
R
_W
R
99
PA
R
_I
N
T
98
GN
D
97
PA
R
_A2
96
PA
R
_A0
95
PA
R
_F
S2
94
PA
R_
CL
K
93
GN
D
92
SP
O
RT
_RS
CL
K
91
SP
O
RT
_DR0
90
SP
O
R
T_
R
FS
89
SP
O
R
T_
TF
S
88
SP
O
R
T_
D
T0
87
SP
O
R
T_
TS
C
LK
86
GN
D
85
SP
I_
SE
L_
A
84
SP
I_
M
O
SI
83
SP
I_
M
IS
O
82
SP
I_
C
LK
81
GN
D
80
SD
A_
0
79
SCL
_0
78
GP
IO
1
77
GP
IO
3
76
GP
IO
5
75
GN
D
74
GP
IO
7
73
TMR
_B
72
TM
R
_D
71
NC
70
NC
69
GN
D
68
NC
67
NC
66
NC
65
NC
64
NC
63
GN
D
62
UA
RT
_T
X
61
BM
O
D
E1
60
RES
ET
_I
N
59
UART
_R
X
58
GN
D
57
NC
56
EE
PR
O
M
_A0
55
NC
54
NC
53
NC
52
GN
D
51
NC
50
NC
49
TM
R
_C
48
TM
R
_A
47
GP
IO
6
46
GN
D
45
GP
IO
4
44
GP
IO
2
43
GP
IO
0
42
SC
L_1
41
SD
A_
1
40
GN
D
39
SPI
_SE
L1
/S
PI
_SS
38
SP
I_
SEL
_C
37
SP
I_
SEL
_B
36
GN
D
35
SP
O
R
T_
IN
T
34
SP
O
R
T_
D
T3
33
SP
O
R
T_
D
T2
32
SP
O
R
T_
D
T1
31
SP
O
R
T_
D
R
1
30
SP
O
R
T_
D
R
2
29
SP
O
R
T_
D
R
3
28
GN
D
27
PA
R
_F
S1
26
PA
R
_F
S3
25
PA
R
_A1
24
PA
R
_A3
23
GN
D
22
PA
R_
CS
21
PA
R_
RD
20
PA
R_
D1
19
PA
R_
D3
18
PA
R_
D5
17
GN
D
16
PA
R_
D7
15
PA
R_
D9
14
PA
R_
D1
1
13
PA
R_
D1
3
12
PA
R_
D1
4
11
GN
D
10
PA
R_
D1
7
9
PA
R_
D1
9
8
PA
R_
D2
1
7
PA
R_
D2
3
6
GN
D
5
U
SB_
VB
U
S
4
GN
D
3
GN
D
2
NC
1
VI
N
J8
1
A0
2
A1
3
A2
4
VS
S
8
VC
C
7
WP
6
SCL
5
SD
A
U4
24L
C
32
J10-
1
J10-
2
J10-
3
J10-
4
J10-
5
J10-
6
R4
5
DN
P
R4
6
100
k
R4
4
100k
C5
0
1u
F
C5
1
1uF
A
K
D1
5
J10-
7
A
K
D1
6
CS
MO
SI
MI
SO
SC
LK
V_
IO
GN
D
+5
V
R4
8
10
0k
R4
7
100
k
V_
EE
PRO
M
V_
EE
PRO
M
SC
LK
MI
SO
MO
SI
CS
V_
IO
V_
U
SB
V_
EE
PR
O
M
SC
L
SD
A
SC
L
SD
A
V_
IO
15728-
020
Figure 24. System Demonstration Platform Connector Schematic
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