ADV7619 Reference Manual
ADV7619 Required Settings Manual
Rev. 1.8 | Page 10 of 14
6
MANUAL HOT PLUG ASSERT
To manually assert a hot plug, to replicate a downstream hot plug in a repeater application for example, the writes below should be used.
•
Port A:
To manually assert hot plug on port A, the following writes should be used.
HDMI Map and IO Map
68 6C A3
Hot plug assert controlled manually
98 20 B0
Manually assert hot plug on port A
•
Port B:
To manually assert hot plug on port A, the following writes should be used.
HDMI Map and IO Map
68 6C A3
Hot plug assert controlled manually
98 20 70
Manually assert hot plug on port B
When a hot plug was asserted manually, it must also be de-asserted manually.
7
CLOCK TERMINATION
The clock termination on both Port A and Port B can be enabled manually by the following writes:
HDMI Map
68 01 00
TERM_AUTO set to 0. Automatic clock termination control disabled (default)
68 83 FC
Enable clock termination manually on both part A and port B
The clock termination can also be enabled automatically. This can be done by setting TERM_AUTO (HDMI Map, Register 0x01[0]) to 1.
8
FREE-RUN OPERATION
For better control in free-run mode, the free-run resolution can be set manually. This can be achieved by following the steps below:
•
Set PRIM_MODE[3:0] to the desired free-run standard (IO Map, Register 0x01[3:0])
•
Set VID_STD[5:0] to the desired free-run standard (IO Map, Register 0x00[5:0])
•
Set V_FREQ[2:0] to the desired free-run frame rate (IO Map, Register 0x01[6:4])
•
Set DIS_AUTO_PARAM_BUFF to 1 (CP Map, Register 0xC9[0]) for the free-run resolution to be defined by PRIM_MODE[3:0],
VID_STD[5:0] and V_FREQ[2:0]
The free-run output defined by PRIM_MODE[3:0], VID_STD[5:0] and V_FREQ[2:0] is generated by the CP core. It is possible to force the
CP core to free-run. This can be done by setting CP_FORCE_FREERUN to 1 (CP Map, Register 0xBF[0]).
Note:
It is not possible to set the free-run resolution manually for input video resolutions with a pixel clock of greater than170 MHz. For these
modes, the CP core is bypassed.
