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ADV7619 Required Settings Manual

 

ADV7619 Reference Manual

 

 

Rev. 1.8 | Page 11 of 14 

9

 

POWER DOWN MODES 

The ADV7619 has two power down modes, power down mode 0 and power down mode 1. In power down mode 0 and power down mode 1, 
chassis supply is available. In power down Mode 1, CEC is powered up. In power down Mode 0, CEC is powered down. 
 
To correctly power down the ADV7619, the steps below should be followed: 

 

Set POWER_DOWN bit to 1 to power down the chip (98 0C 62) 

 

In case of power down mode 0: power down CEC (80 2A 3E) 

 

In case of power down mode 1: power up CEC (80 2A 3F) 

 
When returning from low power mode, to correctly power up the ADV7619, the steps below should be followed: 

 

Set POWER_DOWN to 0 to power up the chip (98 0C 42) 

 

If CEC should be powered up, set CEC_POWER_UP to 1 (80 2A 3F) 

 

If CEC should be powered down, set CEC_POWER_UP to 0  (80 2A 3E) 

 

Note: 

In power down modes,

 

additional power-savings can be achieved by using the following writes: 

 

Disable ring oscillator (68 48 01) 

 

Power down DDC pads (68 73 03)   

 
 

10

 

PACKET DETECTION 

The ADV7619 does not generate an interrupt when a source stops sending the following infoframes: 

 

Audio infoframe 

 

Source Prod infoframe 

 

MPEG Source infoframe 

 

Vendor Specific infoframe 

 

ACP infoframe 

 

ISRC1 infoframe 

 

ISRC2 infoframe 

 

Gamut infoframe 

 
To detect when a source has stopped sending an infoframe, the steps below should be followed: 

 

Clear infoframe interrupt RAW bit 

 

If RAW bit does not get set during max allowed packet repeat time, the source has stopped sending the infoframe 

 
For example, 3D content is indicated using the Vendor Specific (VS) infoframe. It has been observed that some 3D sources stop sending the VS 
infoframe should their output be switched from 3D to 2D. For this reason, the application must detect when the VS infoframe stops being 
received. 
 
Figure 4  and Figure 5 below provide an Interrupt Service Routine (ISR) example that could be used to detect if the VS infoframe is no longer 
received. 
 

Summary of Contents for ADV7619

Page 1: ...is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Information contained within...

Page 2: ...gs 5 2 1 Input Video Pixel Clock Frequency 170MHz 5 2 2 Input Video Pixel Clock Frequency 170MHz 6 3 TMDS Equalizer Settings 7 3 1 Input Video Pixel Clock Frequency 170MHz 7 3 2 Input Video Pixel Cloc...

Page 3: ...ed to TOTAL_LINE_LENGTH 2 12 14 Revision 1 5 to 1 6 Updated overall format of the document Section 1 1 Recommended I2C Addresses renamed Section 1 ADV7619 I2C addresses and content updated Section 1 2...

Page 4: ...A 6C EDID Map Address set to 0x6C 98 FB 68 HDMI Map Address set to 0x68 98 FD 44 CP Map Address set to 0x44 The I2 C addresses are programmed in the IO Map at the registers shown above The ADV7619 IO...

Page 5: ...OCK FREQUENCY 170MHZ The following two categories of settings are required for input video resolutions with a pixel clock of less than or equal to 170 MHz 2 1 1 480i 576i 480p and 576p Resolutions up...

Page 6: ...red Write 68 84 03 ADI Required Write 2 2 INPUT VIDEO PIXEL CLOCK FREQUENCY 170MHZ The following settings are required for input video resolutions with a pixel clock of greater than170 MHz For these r...

Page 7: ...i 576i 480p and 576p resolutions with color depths between 24 bit and 36 bit HDMI Map 68 85 11 ADI Required Write 68 86 9B ADI Required Write 68 89 03 ADI Required Write 68 9B 03 ADI Required Write 68...

Page 8: ...ADI Required Write 4 LOW VERTICAL FREQUENCY FORMATS To process low frame rate video formats such as 720p24 720p25 and 720p30 the NEW_VS_PARAM bit should be set Figure 2 illustrates how to proceed to d...

Page 9: ...TING TMDSPLL_LCK_X_MB1 or TMDSPLL_LCK_X_MB2 1 ENABLE NEW_TMDS_FRQ_ST INTERRUPT BY SETTING NEW_TMDS_FRQ_MB1 or NEW_TMDS_FRQ_MB2 TMDS FREQUENCY READ BACK NOT VALID OR STABLE READ THE TMDS FREQUENCY TMDS...

Page 10: ...68 83 FC Enable clock termination manually on both part A and port B The clock termination can also be enabled automatically This can be done by setting TERM_AUTO HDMI Map Register 0x01 0 to 1 8 FREE...

Page 11: ...ditional power savings can be achieved by using the following writes Disable ring oscillator 68 48 01 Power down DDC pads 68 73 03 10 PACKET DETECTION The ADV7619 does not generate an interrupt when a...

Page 12: ...END VS_INFO_ST has been set indicating that VS_INFO_RAW has changed Is VS_INFO_RAW high IO Map 0x60 4 YES NO Clear status bit IO Map 0x62 4 Enable Software timer for max allowed packet repeat time tim...

Page 13: ...O NO Is Timer Enabled Is Timer Enabled Is time max allowed packet repeate time YES YES YES Is VS_INFO_RAW bit high IO Map 0x60 4 Clear VS_INFO_RAW Infoframe Map 0xEC 0x81 Enable Interrupt Mask IO Map...

Page 14: ...loped by Philips Semiconductors now NXP Semiconductors HDMI the HDMI Logo and High Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States an...

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