ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-3
INDEX
power
connector (J7),
specifications,
PPI0,
,
,
,
Clock, primary processor pin,
primary processor pins 7-0,
SYNC1, primary processor pin,
SYNC2, primary processor pin,
,
Clock, primary processor pin,
primary processor pins 7-0,
SYNC1 signal,
,
SYNC2 signal,
,
primary processor pins (PPIs)
PPIs bits 7-0,
processor SDRAM map, see ADSP-BF561
programmable flags (PFs),
,
PF12-PF9,
PF13,
PF14,
PF15,
PF16-19,
PF2,
,
,
PF20-31,
PF3,
PF39-32,
PF4,
,
,
PF47-40,
,
push buttons,
,
connecting to PF pins,
R
registering, this product,
reset
options,
processor,
push button (SW1),
RFS0, signal,
RSCLK0
register,
S
SDRAM,
,
default settings,
optimum settings,
SDRAM memory,
core MMRs,
data bank A SRAM,
data bank B SRAM,
instruction SRAM,
reserved,
serial
clock (SCL),
Serial Peripheral Interconnect (SPI),
setting target options,
~SMS0, memory select pin,
SPI interface,
SPORT0,
,
,
,
starting EZ-KIT Lite,
SW1, reset push button,