Vi+ Interface
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Table 1-7. Miscellaneous Target Options
Option
Description
Verify all writes to target
memory
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files, since Vi+ does not perform the extra reads that are
required to verify each write.
Reset cycle counters on
run
Resets the cycle count registers to zero before a
Run
command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
Use opcode scan method
Enables the debugger to use a highly optimized JTAG scan method.
This provides extremely fast communication between the EZ-KIT
Lite and the processor. In certain circumstances, this causes JTAG
scan failures. Typically, JTAG scan failures occur when using this
method combined with debugging situations that hold off or stall
the core (such as debugging, loading, or viewing external memory).
Clearing this option uses a less optimized JTAG scan method.
Use XML reset values
Uses a section in the processor-specific
.XML
file located in the
installation’s
system
folder. The file defines registers that are reset
to certain values; the values are read at startup and subsequently
used to set the registers when a reset is performed through Visu-
alDSP++. Applies to both processors.
Mask interrupts during
step
Disables interrupts while single stepping through code. Applies to
both processors.
Disable breakpoints in
shared memory messages
Suppress a warning message caused by setting a breakpoint in
shared memory. Applies to both processors.
