ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-11
EZ-KIT Lite Hardware Reference
Positions 1 thorough 5 of
SW2
determine how and if the
SYNC1
,
SYNC2
, and
FIELD
control signals of the
PPI0
and
PPI1
interfaces are routed to the pro-
cessor’s PPIs. In standard configuration of the encoder and decoder, this is
not necessary because the processor is capable of reading the embedded
control information, which is in the data stream.
Position 6 of
SW2
determines whether
PF2
connects to the
~OE
signal of the
ADV7183A. When the switch is “
OFF
”,
PF2
can be used for other opera-
tions, and the decoder output enable is held “
HIGH
” with a pull-up resistor.
Boot Mode Switch (SW3)
The
SW3
switch positions 1 and 2 set the ADSP-BF561 processor’s boot
mode as described in
. Position 3 sets the processor’s PLL on
boot. When
SW3
position 3 is “
ON
”, the PLL is in bypass.
Table 2-4. Video Configuration Switch (SW2)
Switch Position (Default)
Processor Signal
Video Signal
1 (
OFF
)
PPI1
SYNC1
ADV7179
2 (
OFF
)
PPI0
SYNC1
ADV7183A
3 (
OFF
)
PPI1
SYNC2
ADV7183A
4 (
OFF
)
PPI1
SYNC2
ADV7179
5 (
OFF
)
PF3
(
FIELD
)
ADV7183A
6 (
ON
)
PF2
ADV7183A
Table 2-5. Boot Mode Select Switch (SW3)
Position 1 BMODE0
Position 2 BMODE1
Boot Mode
ON
ON
Reserved
ON
OFF
Flash memory