ADSP-BF518F EZ-Board Evaluation System Manual
2-3
ADSP-BF518F EZ-Board Hardware Reference
is configurable over the 2-wire interface (TWI) signals. Refer to the
power-on-self test (POST) example in the ADSP-BF518F installation
directory of Vi+ for information on how to set up the TWI
interface.
The core voltage and clock rate can be set on the fly by the processor. The
input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock
(RTC) inputs of the processor. The default boot mode for the processor is
external parallel flash boot. See
“Boot Mode Select Switch (SW1)” on
for information on how to change the default boot mode.
Programmable Flags
The processor has 40 general-purpose input/output (GPIO) signals spread
across three ports (
PF
,
PG
, and
PH
). The pins are multi-functional and
depend on the ADSP-BF518F processor setup. The following tables show
how the programmable flag pins are used on the EZ-Board.
•
PF
programmable flag pins –
•
PG
programmable flag pins –
•
PH
programmable flag pins –
Table 2-1. PF Port Programmable Flag Connections
Processor Pin
Other Processor Function
EZ-Board Function
PF0
ETxD2/PPID0/SPI1_SSEL2/TA
CLK6
Default:
ETXD2
Land grid array, expansion interface II
PF1
ERxD2/PPID1/PWM_AH/TACLK7
Default:
ERXD2
Land grid array, expansion interface II
PF2
ETxD3/PPID2/PWM_AL
Default:
ETXD3
Land grid array, expansion interface II
PF3
ERxD3/PPID3/PWM_BH/TACLK0
Default:
ERXD3
Land grid array, expansion interface II
