ADSP-BF518F EZ-Board Evaluation System Manual
2-5
ADSP-BF518F EZ-Board Hardware Reference
Table 2-2. PG Port Programmable Flag Connections
Processor Pin
Other Processor Function
EZ-Board Function
PG0
MIICRS/RMII-
CRS/HWAIT/SPI1_SSEL3
Default:
MIICRS
HWAIT
, land grid array, expansion interface II
PG1
ERxER/DMAR1/PWM_CH
Default:
ERXER
Land grid array, expansion interface II
PG2
MIITxCLK/RMIIREF_CLK/
DMAR0/PWM_CL
Default:
MIITXCLK
Land grid array, expansion interface II
PG3
DR0PRI/RSI_DATA0/
SPI0_SSEL5/TACLK3
Default:
DR0PRI
SD_D0
, land grid array, expansion interface II
PG4
RSCLK0/RSI_DATA1/TMR5/
TACI5
Default:
RSCLK0
SD_D1
, land grid array, expansion interface II
PG5
RFS0/RSI_DATA2/PPICLK_1/
TMRCLK
Default:
RFS0
SD_D2
, land grid array, expansion interface II
PG6
TFS0/RSI_DATA3/TMR0/
PPIFS1_1
Default:
TFS0
SD_D3
, land grid array, expansion interface II
PG7
DT0PRI/RSI_CMD/TMR1/
PPIFS2_1
Default:
DT0PRI
SD_CMD
, land grid array, expansion interface II
PG8
TSCLK0/RSI_CLK/TMR6/TACI6
Default:
TSCLK0
SD_CLK
, land grid array, expansion interface II
PG9
DT0SEC/UART0_TX/TMR4
Default:
UART0_TX
Land grid array, expansion interface II
PG10
DR0SEC/UART0_RX/TACI4
Default:
UART0_RX
Land grid array, expansion interface II
PG11
SPI0_SS/AMS[2]/SPI1_SSEL5/
TACLK2
Default:
AMS2
Land grid array, expansion interface II
PG12
SPI0_SCK/PPICLK_2/TMRCLK
Default:
SPI0_SCK
Land grid array, expansion interface II
PG13
SPI0_MISO/TMR0/PPIFS1_2
Default:
SPI0_MISOI
Land grid array, expansion interface II