AD9854
Rev. E | Page 7 of 52
AD9854ASVZ
AD9854ASTZ
Parameter Temp
Test
Level
Min Typ Max Min Typ Max Unit
PARALLEL I/O TIMING CHARACTERISTICS
t
ASU
(Address Setup Time to WR Signal Active)
Full IV 8.0 7.5
8.0 7.5
ns
t
ADHW
(Address Hold Time to WR Signal Inactive)
Full IV 0
0
ns
t
DSU
(Data Setup Time to WR Signal Inactive)
Full IV 3.0 1.6
3.0 1.6
ns
t
DHD
(Data Hold Time to WR Signal Inactive)
Full IV
0
0
ns
t
WRLOW
(WR Signal Minimum Low Time)
Full IV 2.5 1.8
2.5 1.8
ns
t
WRHIGH
(WR Signal Minimum High Time)
Full IV 7
7
ns
t
WR
(Minimum WR Time)
Full IV 10.5
10.5
ns
t
ADV
(Address to Data Valid Time)
Full
V
15
15 15
15 ns
t
ADHR
(Address Hold Time to RD Signal Inactive)
Full IV 5
5
ns
t
RDLOV
(RD Low to Output Valid)
Full IV
15
15 ns
t
RDHOZ
(RD High to Data Three-State)
Full IV
10
10 ns
SERIAL I/O TIMING CHARACTERISTICS
t
PRE
(CS Setup Time)
Full IV 30
30
ns
t
SCLK
(Period of Serial Data Clock)
Full
IV
100
100
ns
t
DSU
(Serial Data Setup Time)
Full
IV
30
30
ns
t
SCLKPWH
(Serial Data Clock Pulse Width High)
Full
IV
40
40
ns
t
SCLKPWL
(Serial Data Clock Pulse Width Low)
Full
IV
40
40
ns
t
DHLD
(Serial Data Hold Time)
Full
IV
0
0
ns
t
DV
(Data Valid Time)
Full
V
30
30
ns
CMOS LOGIC INPUTS
10
Logic 1 Voltage
25°C
I
2.2
2.2
V
Logic 0 Voltage
25°C
I
0.8
0.8 V
Logic 1 Current
25°C
IV
±5
±12 μA
Logic 0 Current
25°C
IV
±5
±12 μA
Input Capacitance
25°C
V
3
3
pF
POWER SUPPLY
11 , 15
V
S
Current
11, 12 , 15
25°C I
1050 1210
755 865 mA
V
S
Current
11, 13 , 15
25°C I
710 816
515 585 mA
V
S
Current
14
25°C I
600 685
435 495 mA
P
DISS
11, 12, 15
25°C I
3.475 4.190
2.490 3.000 W
P
DISS
11, 13, 15
25°C I
2.345 2.825
1.700 2.025 W
P
DISS
14
25°C I
1.975 2.375
1.435 1.715 W
P
DISS
Power-Down Mode
25°C I
1 50
1 50
mW
1
The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine wave centered at one-half the applied V
DD
or a 3 V TTL-level pulse input.
2
An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.
3
The I and Q gain imbalance is digitally adjustable to less than 0.01 dB.
4
Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are 0s, the delay appears longer. This is due to insufficient phase
accumulation per system clock period to produce enough LSB amplitude to the DAC.
5
If a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.
6
The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.
7
Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
8
Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.
9
Comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output
terminated in 50 Ω.
10
Avoid overdriving digital inputs. (Refer to the equivalent circuits in Figure 3.)
11
If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum
internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.
12
All functions engaged.
13
All functions except inverse sinc engaged.
14
All functions except inverse sinc and digital multipliers engaged.
15
In most cases, disabling the inverse sinc filter reduces power consumption by approximately 30%.
