Quick Start Guide
AD9789-EBZ
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D00000-0-1/07(A)
USING THE AD9516 AS THE CLOCK SOURCE
The AD9789-EBZ has an AD9516 Clock Generator on board to allow evaluation without a high frequency, low
jitter clock source. To enable this, several steps must be performed on the stock board. First, JP8, a three-way solder
jumper, must be soldered to the right position, as shown in Figure 19. This will connect the AD9789’s clock input to
one of the outputs of the AD9516. Note that this will prevent the HF_DACCLK SMA jack from functioning.
Next, move JP11 to position 2-3. This enables the AD9516. The current measured from the +5Vdc power supply
will increase by approximately 300mA. Run the AD9516 Load application (Start > Programs > Analog Devices >
AD9789-EBZ > AD9516 Load). When prompted, select
AD9516_SPI_settings_out0_out2_ref_95MHz.txt
as the file
to read. Once the application has finished writing to the AD9516, it can be closed.
Connect the clock source to S6 (REF_CLK_IN), and set it to generate a 95.573MHz clock with 0dBm amplitude.
This will generate a 2.29376GHz clock for the AD9789. This signal is also available at S10/S11 for debugging the AD9516.
ELECTRICAL INTERFACE SELECTION
The AD9789-EBZ is designed to allow evaluation of both the CMOS and LVDS modes of the AD9789. For LVDS mode, the selection
jumpers JP9 and JP10 should be placed closer to the DPG2 connector (labeled LVDS_BUS and LVDS_CTRL on the board). For CMOS,
the jumpers should be reversed. In DPGDownloader, select the corresponding Configuration. Note that mixing modes (for example,
CMOS_BUS and LVDS_CTRL) is not supported on this evaluation board.
In CMOS mode, the CMOS_DCO (S3) and CMOS_FS (S2) SMA jacks are enabled. They are for observation only; they do not need to be
cabled to the DPG2. Both signals are also routed through the main DPG2 connector.
Between CMOS and LVDS modes, the register settings can remain the same, with the exception of the Latency register in the Data
Control section. This should be 4 in LVDS mode, and 5 in CMOS mode (when used with the DPG2).
Figure 19
