AMD Xilinx ZCU670, User Manual

Page: 25 / 94

Table 6: I/O Voltage Rails (cont'd)
ZU67DR
Power Net
Name
Voltage Connected To
PS Bank 504 VCC1V2 1.2V PS_DDR4_SODIMM (64-BIT) I/F
PS DDR4 SODIMM Socket
[ Figure 2 , callout 2]
The PS-side memory is wired to the Zynq Ult RFSoC DDRC Bank 504 hard memory
controller. A 64-bit single rank DDR4 SODIMM is inserted into socket J48. The ZCU670 is
shipped with a DDR4 SODIMM installed:
• Manufacturer: Micron
• Part Number: MTA4ATF51264HZ-2G6E1
• Description:
○
4 GByte DDR4 260-Pin SODIMM
○
Single Rank (x 16-bit components)
○
512 Mb x 64-bit
○
2666 MT/s
The ZCU670 ZU67DR RFSoC (ZU67DR supports 2400MT/s) PS DDR interface performance is
documented in the Zynq Ult RFSoC Data Sheet: DC and AC Switching Characteristics
(
DS926 ).
The ZCU670 DDR4 SODIMM interface adheres to the constraints guidelines documented in the
PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide (
UG583 ).
The DDR4 SODIMM interface is a 40Ω impedance implementation. Other memory interface
details are also available in the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (
PG150 ).
For additional details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet on the Micron
Technology website.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
Appendix B: Xilinx Design Constraints .
PL C0 I/F DDR4 Component Memory
[ Figure 2 , callout 3]
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 25
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