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Figure 6: Encryption Key Battery Backup Circuit

X25697-090221

The Seiko TS621E rechargeable 1.5V lithium button-type battery B1 is soldered to the board
with the positive output connected to the ZU67DR RFSoC U1 VCC_PSBATT pin AE29. The
battery supply current IBATT specification is 150 nA maximum when board power is off. B1 is
charged from the VCC1V8 1.8V rail through a series diode with a typical forward voltage drop of
0.38V and 4.7 ΩK current limit resistor. The nominal charging voltage is 1.42V.

I/O Voltage Rails

The ZU67DR RFSoC PL I/O bank voltages on the ZCU670 board are listed in the following table.

Table 6: I/O Voltage Rails

ZU67DR

Power Net

Name

Voltage

Connected To

PL Bank 65

VCC1V2

1.2V

PL_DDR4_C0_DQx, MSP430_UCA1, UART2

PL Bank 66

VCC1V2

1.2V

PL_DDR4_C0_Ax, USER_SI570_C0, SI5381_PL_CLK,

ADCIO[08:15], DACIO[08:15]

PL Bank 67

VCC1V8

1.8V

ADCIO[00:07], DACIO[0:07], SI5381_CLK2_IN,

8A34001_Q3_OUT, SI5381_CLK_125,

CLK104_CLK_SPI_MUX_SEL[0:1]

PL Bank 88

VCC1V8

1.8V

SYSMON_SDA/SCL, CPU_RESET, GPIO_SW_PL,

SI5381_CLK104_MUX_SEL, SI53340_MUX_GT_SEL,

SI53340_MUX_GTR_SEL, CLK104_PL_CLK,

8A34001_Q2_OUT, MUX_PL_SYSREF,

8A34001_CLK6_IN, GPIO_LED[0:3],

MSP430_GPIO[0:3]

PS Bank 500

VCC1V8

1.8V

MIO_LED/PB, UART0, MIO_I2C0/1, PS_GPIO2, QSPI

LWR/UPR

PS Bank 501

VCC1V8

1.8V

SDIO I/F, PMU_GPO[0:5], SFP[0:3]_TX_DISABLE,

PMU_INPUT

PS Bank 502

VCC1V8

1.8V

ENET I/F, USB (3.0) I/F

PS Bank 503

VCC1V8

1.8V

PS CONFIG I/F, JTAG I/F

Chapter 3: Board Component Descriptions

UG1532 (v1.0) March 30, 2022

ZCU670 Board User Guide

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Summary of Contents for Xilinx ZCU670

Page 1: ...language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including terms embedded in our software and IPs You may still find examples of non inclusive language in our older products as we work to make these changes and align with evolving industry standards Follow this link for more informati...

Page 2: ...U67DR 18 Chapter 3 Board Component Descriptions 20 Overview 20 Component Descriptions 20 Appendix A VITA57 4 FMCP Connector Pinout 63 Appendix B Xilinx Design Constraints 64 Overview 64 Appendix C Regulatory and Compliance Information 65 CE Information 65 Compliance Markings 66 Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM 67 Overview 67 Block Diagram 68 Connector 69 XM650 755 Connect...

Page 3: ...l Description 82 Appendix E Additional Resources and Legal Notices 92 Xilinx Resources 92 Documentation Navigator and Design Hubs 92 References 92 Revision History 94 Please Read Important Legal Notices 94 UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 3 Send Feedback ...

Page 4: ... applications The ZCU670 board is equipped with all the common board level features needed for design development such as DDR4 memory networking interfaces an FMC expansion port as well as access to the RFMC 2 0 interface Additional Resources See Appendix E Additional Resources and Legal Notices for references to documents files and resources relevant to the ZCU670 evaluation board Chapter 1 Intro...

Page 5: ...X_SEL TDD SMA x1 CPU_RESET MPS430_GPIO 8A34001 CLKO x1 8A34001 CLKinx1 Si5381 CLKO x1 CLK104_PL_CLK TDD SMA x1 PB LEDs CLK MUX SEL SYSMON_I2C PS PB LED UART0 PS_I2C0 PS_I2C1 QSPI_UPR QSPI_LWR PS_GPIO2 RFMC2 0 CON1 ADC_T1_CH0 CH3 ADC_T2_CH01 CH23 ADC_T0_CH0 CH3 RFMC2 0 CON2 DAC_T1_CH0 CH3 DAC_T0_CH0 CH3 X25678 111521 Board Features The ZCU670 evaluation board features are listed here Detailed infor...

Page 6: ...nd SI5381A 10 Independent Output Any Frequency Clock Generator U43 PS_REF_CLK 33 333333 33 1 3 MHz ADC_CLK_226 direct connect SSMP For additional details on this clock see Table 17 Table 18 and Programmable User SI570 Clocks DAC_CLK_228 direct connect SSMP USER_MGT_SI570 default 156 25 MHz For additional details on this clock see Table 17 Table 18 and Programmable User SI570 Clocks USER_SI570_C0 d...

Page 7: ... PS MIO 27 30 SFP 0 3 TX_DISABLE PS MIO 32 37 PMU_GPO 0 5 PS MIO 38 PS_GPIO1 PS MIO 39 43 45 51 SD I F PS MIO 52 63 USB3 0 PS MIO 64 77 Ethernet RGMII PL I O connections PL user GPIO pushbutton PL CPU reset pushbutton PL user GPIO LEDs 4 Security PSBATT button battery backup SYSMON header Operational switches power on off PS_PROG_B boot mode DIP switch Operational status LEDs INIT DONE PS STATUS P...

Page 8: ... 95 GSPS RF ADC with DDC 8 14 bit 5 9 GSPS ADC RF DAC with DDC 2 14 bit 10 GSPS RF DAC with DUC 8 APU Quad core Arm Cortex A53 MPCore with CoreSight 1 RTPU Dual core Arm Cortex R5F MPCore with CoreSight 1 HD I O 96 HP I O 312 MIO banks 3 banks total of 78 pins PS GTR 6 Gb s transceivers 4 PS GTRs PL GTY 28 Gb s transceivers 8 GTYs System logic cells 489 300 CLB flip flops 447 360 CLB LUTs 223 680 ...

Page 9: ... for general guidelines only Customers should use the ZCU670 evaluation board for evaluation purposes only in a normal lab environment and should not operate beyond room temperature Temperature Operating 0 C to 45 C Storage 25 C to 60 C Humidity 5 to 95 non condensing Operating Voltage 12 VDC Chapter 1 Introduction UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 9 Send Feedback ...

Page 10: ...d installing or replacing hardware touch an unpainted metal surface of the system for a minimum of five seconds Do not remove the device from the antistatic bag until you are ready to install the device in the system With the device still in its antistatic bag touch it to the metal frame of the system Grasp cards and boards by the edges Avoid touching the components and gold connectors on the adap...

Page 11: ...be used as such Always refer to the schematic layout and XDC files of the specific ZCU670 version of interest for such details Figure 2 ZCU670 Component Locations 1 00 Round callout references a component on the front side of the board Square callout references a component on the back side of the board 00 35 27 42 45 13 15 43 28 12 16 33 7 25 36 30 5 8 47 26 3 37 38 39 40 9 10 41 29 44 2 14 17 34 ...

Page 12: ...G 2 mm 2x7 flat cable connector Molex 87832 1420 25 10 U43 Fixed frequency clock gen B Skyworks SiLabs SI5381A E13960 GMR 37 11 U47 C0 User Clock 300 MHz 3 3V LVDS B Skyworks SiLabs 570BAB001614DG 38 12 U48 User MGT Clock 156 250 MHz 3 3V LVDS Skyworks SiLabs 570BAB000544DG 38 U409 Various eCPRI clocks Renesas 8A34001E 000AJG8 34 13 External SFP jitter attenuated clock CLK104 module function J101 ...

Page 13: ...03 0 L 08 2 K TR 61 30 J87 RFMC 2 0 connector 2 Samtec LPAF 50 03 0 L 08 2 K TR 62 31 J148 2 pin HDR RFSoC selection SULLINS PBC02SAAN 53 33 U50 Fan controller Maxim MAX6643LBBAEE 43 J57 Fan header keyed 3 pin Molex 22 11 2032 43 34 J6 J7 SMA 8A34001_Q5_OUT_SMA AMPHENOL 132134 15 35 35 J8 J98 ADC clock connectors CARLISLE TM14 0084 00 7 36 J99 J100 DAC clock connectors CARLISLE TM14 0084 00 8 37 U...

Page 14: ...witch Settings The following figure shows the ZCU670 board jumper header and switch locations Each numbered component shown in the figure is keyed to the applicable table in this section Both tables reference the respective schematic page numbers Chapter 2 Board Setup and Configuration UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 14 Send Feedback ...

Page 15: ...ces a component on the front side of the board Square callout references a component on the back side of the board 00 1 2 5 12 3 11 7 14 4 8 X25710 091021 Chapter 2 Board Setup and Configuration UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 15 Send Feedback ...

Page 16: ...Sequencer PS_SRST_B ON 10 OFF Sequencer does not control PS_SRST_B ON Sequencer can control PS_SRST_B J17 Reset Sequencer inhibit OFF 10 OFF Sequencer normal operation ON Sequencer inhibit resets will stay asserted 4 ULPI USB3320 U6 ULPIO_VBUS_SEL option jumper OFF 20 J19 ON Selects U17 MIC2544A switch 5V for VBUS OFF Normal operation VBUS from J18 USB3 0 conn J20 USB 3 0 Connector J18 Shield conn...

Page 17: ...Gen3 Switches The following table lists the default switch settings Table 4 Default Switch Settings Callout Reference Design Function Default Schematic Page 11 SW2 RFSoC U1 mode 4 pole DIP switch 0000 10 Switch OFF 1 High ON 0 Low Mode SW1 4 1 Mode 3 0 JTAG ON ON ON ON 0000 QSPI32 ON ON OFF ON 0010 SD OFF OFF OFF ON 1110 12 SW6 MSP430 U38 5 pole GPIO DIP switch 11111 27 Switch OFF 1 High ON 0 Low ...

Page 18: ...e U29 connected to micro USB connector J24 QSPI Use the following steps to boot from the dual QSPI non volatile configuration memory 1 Store a valid Zynq UltraScale RFSoC boot image into the QSPI flash devices U11 U12 MIO 0 12 QSPI interface 2 Set the boot mode pins SW2 4 1 as indicated in the table above for QSPI32 3 Either power cycle or press the power on reset POR pushbutton SW2 is callout 11 ...

Page 19: ...ce Technical Reference Manual UG1085 for more information about Zynq UltraScale RFSoC configuration options Chapter 2 Board Setup and Configuration UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 19 Send Feedback ...

Page 20: ...gic PL in the same device The processing system in the Zynq UltraScale RFSoC features the Arm flagship Cortex A53 64 bit quad core processor and Cortex R5F dual core real time processor The VCCINT supplies are user adjustable through the PMBus with the voltage ranges to support whichever Zynq UltraScale RFSoC speed grade is on the evaluation board See the Zynq UltraScale RFSoC Data Sheet DC and AC...

Page 21: ...IO Central Switch FPD DMA DisplayPort v1 2 x1 x2 2 x SATA v3 1 PCIe Gen2 x1 x2 or x4 SHA3 AES GCM RSA Processor System BPU DDRC DDR4 3 3L LPDDR3 4 Programmable Logic 128 KB RAM PL_LPD HP GIC RGMII ULPI PS GTR SMMU CCI GFC USB 3 0 SGMII Low Power Switch To ACP Low Power Full Power Battery Power 32 bit 64 bit 64 bit M S 128 bit M S LPD_PL HPC HPM GTY Quad GTH Quad DFE 100G Ethernet ACE Low latency P...

Page 22: ...ltraScale RFSoCs can also use the I O in the PL domain for many of the PS I O peripherals This is done through an extended multiplexed I O interface EMIO and boots at power up or reset The ZCU670 is an evaluation board featuring the ZU67DR Zynq UltraScale RFSoC DFE device This board enables the evaluation of applications requiring multi band sub 7 GHz mmWave multi std 5G LTE etc and multi mode TDD...

Page 23: ...ters data capture insertion Signal statistics debug Calibration diagnostics Processor Subsystem System configuration DPD update DFE DAC DFE ADC DFE ADC DFE IP Prog Logic Processor X25919 102921 For more information on the Zynq UltraScale RFSoC DFE see the Breakthrough Adaptive Radio Platform website and the Zynq UltraScale RFSoC DFE Data Sheet Overview DS883 Encryption Key Battery Backup Circuit T...

Page 24: ...me Voltage Connected To PL Bank 65 VCC1V2 1 2V PL_DDR4_C0_DQx MSP430_UCA1 UART2 PL Bank 66 VCC1V2 1 2V PL_DDR4_C0_Ax USER_SI570_C0 SI5381_PL_CLK ADCIO 08 15 DACIO 08 15 PL Bank 67 VCC1V8 1 8V ADCIO 00 07 DACIO 0 07 SI5381_CLK2_IN 8A34001_Q3_OUT SI5381_CLK_125 CLK104_CLK_SPI_MUX_SEL 0 1 PL Bank 88 VCC1V8 1 8V SYSMON_SDA SCL CPU_RESET GPIO_SW_PL SI5381_CLK104_MUX_SEL SI53340_MUX_GT_SEL SI53340_MUX_G...

Page 25: ...C and AC Switching Characteristics DS926 The ZCU670 DDR4 SODIMM interface adheres to the constraints guidelines documented in the PCB guidelines for DDR4 section of the UltraScale Architecture PCB Design User Guide UG583 The DDR4 SODIMM interface is a 40Ω impedance implementation Other memory interface details are also available in the UltraScale Architecture Based FPGAs Memory IP LogiCORE IP Prod...

Page 26: ...aScale Architecture Based FPGAs Memory IP LogiCORE IP Product Guide PG150 For additional details see the Micron MT40A1G8SA 075 data sheet on the Micron Technology website The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file referenced in Appendix B Xilinx Design Constraints PSMIO The following table provides PS MIO peripheral mapping ...

Page 27: ...Not assigned no connect 50 SD1 76 GEM3 25 Not assigned no connect 51 SD1 77 GEM3 Quad SPI Flash Memory MIO 0 12 Figure 2 callout 5 The Micron dual MT25QU02GCBB8E12 0SIT serial NOR flash Quad SPI memories are capable of holding the boot image for the Zynq UltraScale RFSoC This interface is used to support QSPI32 boot mode as defined in the Zynq UltraScale Device Technical Reference Manual UG1085 Th...

Page 28: ...O bits are connected to the U38 MSP430 system controller for general purpose signaling or communications between the Zynq UltraScale RFSoC and the MSP430 system controller These signals are level shifted by TXS0108E U37 The connections between the U38 system controller and the ZU67DR RFSoC are listed in following table Table 8 System Controller U38 GPIO Connections to ZU67DR U1 Net Name MSP430 U38...

Page 29: ...IO26_PMU_IN DAC_VOUT_SEL SI5381_INT_ALM IIC_MUX_RST_B GEM3_RST_B MAX6643_FSPD FMCP_PRSNT VINT_VRHOT_B 8A34001_RST_B IRPS_ALERT_B INA_ALERT_B U1 XCZU67DR X25698 111521 I2C0 MIO 14 15 Figure 2 callout 17 I2C bus I2C0 connects Zynq UltraScale RFSoC U1 PS Bank 500 and the system controller U38 to a GPIO 16 bit port expander TCA6416A U15 and I2C switch PCA9544A U17 The port expander enables controlling...

Page 30: ..._SDA SCL SYSMON_SCA SCL U17 SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 U15 I2C0_SDA SCL X25699 090321 The following table identifies the devices on each port of the I2C0 U15 TCA6416A port expander Table 9 I2C0 Port Expander TCA6416A U15 Connections TCA6416A U15 Schematic Net Name Connected To Pin Name Pin Name Ref Designator Device SDA I2C0_SDA Refer to connections shown in the figure above TCA6416A U15 Addr...

Page 31: ... switch are identified in the following table Table 10 I2C0 Multiplexer PCA9544A U17 Target Device Addresses PCA9544A U17 Addr 0x75 Port I2C0 Bus Device Target Device Address 0 INA226_PMBus Power Monitors 0X40 0x43 0x45 0x4E 1 Not Connected N A 2 IRPS5401_PMBus Voltage Regulators 0X40 0x43 0x44 0x45 0x4B 0x4C 3 SYSMON U1 bank 65 0X32 I2C1 MIO 16 17 Figure 2 callout 18 I2C bus I2C1 connects RFSoC U...

Page 32: ...A SCL SFP3_IIC_SDA SCL SFP2_IIC_SDA SCL SFP1_IIC_SDA SCL SFP0_IIC_SDA SCL SDA SCL 0x75 U22 X25700 111621 The addresses of each target device on the I2C1 U20 and U22 PCA9548A switches are identified in the following tables Table 11 I2C1 TCA9548A U20 Target Device Addresses TCA9548A U20 Addr 0x74 Port I2C1 Bus Device Target Device Address 0 EEPROM U16 0X54 1 Si5341 Clock U43 0x76 2 USER SI5381A C0 C...

Page 33: ...d in Appendix B Xilinx Design Constraints UART0 MIO 18 19 Figure 2 callout 8 This is the primary Zynq UltraScale RFSoC PS side UART interface and is connected to the FTDI U29 FT4232HL USB to Quad UART Bridge port B through TXS0108E level shifter U32 The FT4232HL U29 port assignments are listed in the following table Table 13 FT4232HL Port Assignments FT4232HL U29 Zynq UltraScale RFSoC U1 Port A JT...

Page 34: ...de pushbutton SW1 is connected to MIO22 PS side LED DS1 physically placed adjacent to the pushbutton is connected to MIO23 PMU GPI MIO 26 PS side MIO 26 is reserved as an input to the PMU for indicating a warm boot PS bank 501 MIO26 is connected to the I2C0 U15 TCA6416A bus expander port P02 through level shifter U27 See the Zynq UltraScale Device Technical Reference Manual UG1085 for details abou...

Page 35: ...ale Device Technical Reference Manual UG1085 for details about the PMU interface The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file referenced in Appendix B Xilinx Design Constraints SDIO MIO 39 51 A PS side interface to an SD card connector is provided for booting and file system storage This interface is used for the SD boot mode ...

Page 36: ...ides SD3 0 capability with SDR104 performance The following figure shows the connections of the SD card interface on the ZCU670 board Figure 11 SD Card Interface X25730 091021 The NXP SD3 0 level shifter is mounted on an X SDM 01 interposer board that has the pin mapping shown in the following table Table 15 NVT4857UK U23 Adapter Pinout Adapter Pin Number NVT4857UKAZ Pin Number NVT4857UKAZ Pin Nam...

Page 37: ...escribed in this section are documented in the ZCU670 board XDC file referenced in Appendix B Xilinx Design Constraints USB0 MIO 52 63 USB 3 0 Transceiver and USB 2 0 The USB interface on the PS side serves multiple roles as a host or device controller The USB 3 0 interface host mode only is supported by the RFSoC GTR interface while the USB 2 0 host and device modes capabilities of the SMSC USB33...

Page 38: ...systems Corporation USB3320 data sheet for clocking mode details The interface to the USB3320 PHY is implemented through the IP in the ZU67DR RFSoC Processor System PS USB OTG support is available for USB 2 0 See Table 3 for USB 2 0 jumper settings Note The shield for the USB 3 0 micro B connector J18 can be tied to GND by a jumper on header J20 pins 2 3 default The USB shield can optionally be co...

Page 39: ...wn in the following figure which connects to a TI DP83867IRPAP Ethernet RGMII PHY before being routed to an RJ45 Ethernet connector The RGMII Ethernet PHY is boot strapped to PHY address 5 b01100 0x0C and Auto Negotiation set to Enable Communication with the device is covered in the TI DP83867 RGMII PHY data sheet on the Texas Instruments website Figure 14 Ethernet Block Diagram TI DP83867IR GEM M...

Page 40: ... pin 6 input also triggers a PS_POR_B signal Figure 15 Ethernet PHY Reset Circuit X25883 101921 Ethernet PHY LED Interface Figure 2 callout 16 The DP83867IRPAP PHY U33 LED interface LED_0 LED_2 uses the two LEDs embedded in the P1 RJ45 connector bezel The LED functional description is as shown in the following table Table 16 Ethernet PHY LED Functional Description Pin Name Type Description LED_2 S...

Page 41: ... of the board near the RJ45 P1 connector Figure 2 callout 16 For more Ethernet PHY details see the TI DS83867 data sheet on the Texas Instruments website The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file referenced in Appendix B Xilinx Design Constraints Programmable Logic JTAG Programming Options Figure 2 callouts 8 and 9 ZCU670 J...

Page 42: ... fixed and variable clock sources for the ZU67DR Zynq UltraScale RFSoC The following table lists the source devices for each clock Table 17 ZCU670 Board Clock Sources Clock Net Name Frequency Clock Source Fixed Frequency Clocks PS_REF_CLK 33 33 MHz U130 SI570 I2C PROG OSC 0x5D SI5381_CLK_125 125 MHz U43 SI5381A PROG CLK GEN 0x76 SI5381_GTR_REFCLK_USB3 26 MHz Chapter 3 Board Component Descriptions ...

Page 43: ...PRI clocks Various U409 8A34001 0x58 The following table lists the connections for each clock Table 18 Clock Connections to ZU67DR U1 Clock Source Ref Des and Pin Net Name I O Standard U130 SI570 I2C PROG OSC U130 4 PS_REF_CLK series R300 1 U47 SI570 I2C Prog Oscillator DDR4 C0 I F 300 MHz Default U47 4 USER_SI570_C0_P LVDS U47 5 USER_SI570_C0_N LVDS U48 SI570 I2C PROG OSC 156 25 MHz Default U48 4...

Page 44: ..._CLK_228_P See Zynq UltraScale RFSoC Data Sheet DC and AC Switching Characteristics DS926 J100 N SMA CONN DAC_CLK_228_N See Zynq UltraScale RFSoC Data Sheet DC and AC Switching Characteristics DS926 U409 8A34001 eCPRI Clock U409 A9 Q1 8A34001_Q1_OUT_P 2 U409 B9 Q1 8A34001_Q1_OUT_N 2 U409 A11 Q2 8A34001_Q2_OUT_P LVDS U409 B11 Q2 8A34001_Q2_OUT_N LVDS U409 A12 Q3 8A34001_Q3_OUT_P LVDS U409 B12 Q3 8A...

Page 45: ...abs SI5381A E13960 GMR documents the pre programmed output frequencies Inputs XAXB 54 000000 MHz Crystal mode IN0 SMA Input J146 IN1 8A34001_Q7_OUT IN2 SI5381_CLK2_IN FB_IN SI5381_FEEDBACK U43 OUT9 Outputs OUT0A 122 88 MHz Enabled Diff_920mV OUT0 Unused OUT1 Unused OUT2 N C OUT3 122 88 MHz Enabled Diff_920 mV OUT4 Unused OUT5 245 76 MHz Enabled LVDS Pulled to 1 2V OUT6 26 MHz Enabled LVDS Chapter ...

Page 46: ... interface Power cycling the ZCU670 board reverts user clocks to their default settings These oscillators can also be reprogrammed from MSP430 system controller U38 see TI MSP430 System Controller on the Texas Instruments website for more system controller information and the ZCU670 Evaluation Board website for the ZCU670 System Controller GUI Tutorial XTP698 DDR4 memory interface C0 U47 SI570 Pro...

Page 47: ...ignal ADC_CLK_226_N connects to U1 AB4 The DAC differential pair feeds into Zynq UltraScale RFSoC U1 ADC Bank 228 The P side SMA J99 signal ADC_CLK_226_P connects to U1 J5 The N side SMA J100 signal ADC_CLK_226_N connects to U1 J4 The differential 1588 eCPRI clock signal pair is series capacitor coupled to the Skyworks Solutions Inc SiLabs SI5381A The P side SMA J129 signal 8A31004_CLK3_P connects...

Page 48: ...P_TX_DISABLE Jumper J39 Switch Q6 U1 K16 Off SFP Disabled On SFP Enabled SFP_MOD_DETECT Test Point J12 High Module not present Low Module Present SFP_RS0 PU R262 PD R269 PU R262 Full RX bandwidth PD R269 Reduced RX bandwidth SFP_RS1 PU R263 PD R264 PU R263 Full TX bandwidth PD R264 Reduced TX bandwidth SFP_LOS Test Point TP13 High Loss of receiver signal Low Normal operation SFP1 J29 LL1 2 SFP_TX_...

Page 49: ...ion SFP3 J29 RL1 2 SFP_TX_FAULT Test Point TP8 High Fault Low Normal Operation SFP_TX_DISABLE Jumper J35 Switch Q5 U1 K15 Off SFP Disabled On SFP Enabled SFP_MOD_DETECT Test Point TP9 High Module not present Low Module Present SFP_RS0 PU R284 PD R290 PU R284 Full RX bandwidth PD R290 Reduced RX bandwidth SFP_RS1 PU R285 PD R291 PU R285 Full TX bandwidth PD R291 Reduced TX bandwidth SFP_LOS Test Po...

Page 50: ... download is complete DS4 PS_RESET_B Red POR U5 asserts RESET_B low when any of the monitored voltages IN_ falls below its respective threshold any EN_ goes low or MR is asserted DS5 PS_ERR_OUT Red PS error out is asserted for accidental loss of power an error in the PMU that holds the CSU in reset or an exception in the PMU DS6 PS_ERR_STATUS Red PS error status indicates a secure lockdown state A...

Page 51: ...DS31 VCCINT_AMS_PG Green VCCINT_AMS 0 85VDC power on DS32 ADC_AVCC_PG Green ADC_AVCC 0 925VDC power on DS34 ADC_AVCCAUX_PG Green ADC_AVCCAUX 1 8VDC power on DS36 DAC_AVTT_PG Green DAC_AVTT 2 5VDC power on DS37 UTIL_1V13_PG Green UTIL_1V13 1 13VDC power on DS38 UTIL_2V5_PG Green UTIL_2V5 2 5VDC power on DS39 UTIL_3V3_PG Green UTIL_3V3 3 3VDC power on DS40 UTIL_5V0_PG Green UTIL_5V0 5VDC power on DS...

Page 52: ...Scale RFSoC has 4 GTR gigabit transceivers 6 Gb s capable on the PS side and 8 GTY gigabit transceivers 28 Gb s capable on the PL side All 4 GTR and all 8 GTY transceivers are allocated Chapter 3 Board Component Descriptions UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 52 Send Feedback ...

Page 53: ...ets of clocks to from IDT 8A34001 U409 Each zSFP connector provides an I2C based control interface This I2C interface is accessible for each individual zSFP module through the I2C multiplexer topology on the ZCU670 For additional information on GTY transceivers see the UltraScale Architecture GTY Transceivers User Guide UG578 The detailed RFSoC connections for the feature described in this section...

Page 54: ... 1 27 mm 0 050 in pitch Mates with SEAM series connector More information about SEAF series connectors is available on the Samtec Inc website More information about the VITA 57 4 FMC specification is available on the VITA FMC Marketing Alliance website The 560 pin FMC connector defined by the FMC specification see Appendix A VITA57 4 FMCP Connector Pinout provides connectivity for up to 160 single...

Page 55: ...chanisms are defined by the strapping resistors on the MAX6643 device The over temperature and fan failures alarms can be monitored by any available processor in the RFSoC by polling the I2C expander U15 on the I2C0 bus See the MAX6643 data sheet on the Maxim Integrated Circuits website for more information on the device circuit implementation on this board The ZCU670 cooling fan circuit is shown ...

Page 56: ...power advantage demonstration and system controller firmware A host PC resident system controller board user interface is provided on the ZCU670 Evaluation Board website The board user interface allows the query and control of select programmable features such as clocks FMC functionality and power system parameters The ZCU670 website also includes the ZCU670 System Controller GUI Tutorial XTP698 a...

Page 57: ...e ZCU670 board includes the following power configuration and reset switches SW15 power on off slide switch callout 24 SW3 PS_PROG_B active Low pushbutton callout 23 SW4 POR_B active Low pushbutton callout 23 SW5 SRST_B active Low pushbutton callout 23 SW2 U1 RFSoC PS bank 503 4 pole mode DIP switch callout 23 Power On Off Slide Switch Figure 2 callout 24 The ZCU670 board power switch is SW15 Slid...

Page 58: ...921 Program_B Pushbutton Figure 2 callout 23 PS_PROG_B pushbutton switch SW3 grounds the ZU67DR RFSoC PS_PROG_B pin when pressed This action clears programmable logic configuration which the PS software can then act on See the Zynq UltraScale Device Technical Reference Manual UG1085 for information about the Zynq UltraScale RFSoC configuration System Reset Pushbuttons Figure 2 callout 23 The follo...

Page 59: ...tage at IN2 is below its threshold or EN2 P B switch SW5 is pressed goes Low OUT2 PS_SRST_B goes Low Active Low Reset Output RESET_B asserts when any of the monitored voltages IN_ falls below its respective threshold any EN_ goes Low or MR is asserted RST_B remains asserted for the reset time out period after all of the monitored voltages exceed their respective threshold all EN_ are High all OUT_...

Page 60: ...05 53 U114 MPM3833C ADC_AVCCAUX 1 8 2 U71 0x4D R475 0 005 54 U125 MPM3833C DAC_AVCCAUX 1 8 1 5 U124 0x4B R889 0 005 55 U118 MPM3833C DAC_AVTT_BUS 2 5 3 0 1 5 U59 0x4A R869 0 005 55 U111 IR3889 UTIL_3V3 3 3 15 NA NA NA 57 U126 IR3889 UTIL_5V0 5 10 NA NA NA 58 U79 TPS51200 PL_DDR4_C0_VTT 0 6 3 0 NA NA NA 59 The FMCP HSPC J28 VADJ pins and RFSoC U1 banks 66 and 67 VCCO pins are wired to the programma...

Page 61: ...IRCenter graphical user interface The PMBus interface controllers and regulators are accessed through 1x3 PMBus connector J21 that is provided for use with the Infineon PowIRCenter USB cable Infineon part number USB005 and can be ordered from the Infineon Integrated Circuits website The associated Infineon PowerTool GUI can be downloaded from the Infineon website This is the simplest and most conv...

Page 62: ...ower monitors are separated on to INA226_PMBUS Figure 8 and Table 10 document the I2C0 bus access path to the Infineon PMBus controllers and INA226 power monitor op amps Also refer to schematic 038 05070 01 Power rail measurements are accessible to the system controller and RFSoC PL logic through their respective I2C0 bus connections Chapter 3 Board Component Descriptions UG1532 v1 0 March 30 2022...

Page 63: ...ctor defined by the VITA 57 4 FMC specification For a description of how the ZCU670 evaluation board implements the FMCP specification see FPGA Mezzanine Card Interface Figure 22 FMCP HSPC Connector Pinout X25925 102921 Appendix A VITA57 4 FMCP Connector Pinout UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 63 Send Feedback ...

Page 64: ...Vivado Design Suite User Guide Using Constraints UG903 for more information The HSPC FMCP connector J28 is connected to Zynq UltraScale RFSoC U1 banks powered by the variable voltage VADJ_FMC The FMC bank I O standards must be uniquely defined by each customer because different FMC cards implement different circuitry IMPORTANT To access the XDC file click the Documentation tab on the ZCU670 Evalua...

Page 65: ...ion IEC CE Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2010 Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement This is a Class A product In a domestic environment this product can cause radio interference in which case the user might be required to ...

Page 66: ...EEE Compliance Schemes in some countries to help manage customer returns at end of life If you have purchased Xilinx branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life please do not dispose of them with your other household or municipal waste Xilinx has labeled its branded electronic products with the WEEE Symbol to alert...

Page 67: ...ty The XM755 add on card is a full break out of 16 DAC channels x 16 ADC channels to SMA connectivity using Carlisle CoreHC2 assembly connections Note The following descriptions for pinout and RF tile figures are specific to the ZCU670 evaluation board For pinouts and tile descriptions for other boards see the applicable board user guide Table 24 Add on Board Features Feature Description Base boar...

Page 68: ... Figure 23 XM755 Block Diagram XM650 16T16R N79 Band Loopback Demo Add on Card Figure 24 XM650 Block Diagram Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 68 Send Feedback ...

Page 69: ...I O pins 8x50 Stack height 157 4 00 mm Mated with LPAF 50 03 0 L 08 2 K TR Make SAMTEC Description Low profile open pin field array male connector Data sheet See the Samtec website Figure 25 LPAM 50 01 0 L 08 2 K TR 3D View Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 69 Send Feedback ...

Page 70: ...Figure 26 LPAM Connector Drawing Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 70 Send Feedback ...

Page 71: ...V GND 12V 8 5v0 GND 5v0 GND 5v0 GND 5v0 GND 9 GND 5v0 GND 5v0 GND 5v0 GND 5v0 10 GND GND GND GND GND GND GND GND 11 GND GND GND GND GND GND GND GND 12 GND GND GND GND GND GND GND GND 13 GND GND GND GND GND GND GND GND 14 GND GND GND GND GND DAC_T1_CH3_N DAC_T1_CH3_P GND 15 GND GND GND GND GND GND GND GND 16 GND GND GND GND GND GND GND GND 17 GND GND GND GND GND GND GND GND 18 GND GND GND GND GND G...

Page 72: ...5 GND GND GND GND GND GND GND GND 36 GND GND GND GND GND GND GND GND 37 GND GND GND GND GND GND GND GND 38 GND GND GND GND GND GND GND GND 39 GND GND GND GND GND DAC_T0_CH2_N DAC_T0_CH2_P GND 40 GND GND GND GND GND GND GND GND 41 GND GND GND GND GND GND GND GND 42 GND GND GND GND GND GND GND GND 43 GND GND GND GND GND GND GND GND 44 GND GND GND GND GND DAC_T0_CH1_N DAC_T0_CH1_P GND 45 GND GND GND ...

Page 73: ...DC_T2_CH 01_P GND GND GND GND GND 8 GND GND GND GND GND GND GND GND 9 GND GND GND GND GND GND GND GND 10 GND GND GND GND GND ADC_T1_CH 2_N ADC_T1_CH 2_P GND 11 GND GND GND GND GND GND GND GND 12 GND GND GND GND GND GND GND GND 13 GND GND GND GND GND GND GND GND 14 GND GND GND GND GND GND GND GND 15 GND GND GND GND GND ADC_T1_CH 1_N ADC_T1_CH 1_P GND 16 GND GND GND GND GND GND GND GND 17 GND GND GN...

Page 74: ...GND GND GND GND GND GND 30 GND GND GND GND GND ADC_T0_CH 2_N ADC_T0_CH 2_P GND 31 GND GND GND GND GND GND GND GND 32 GND GND GND GND GND GND GND GND 33 GND GND GND GND GND GND GND GND 34 GND GND GND GND GND GND GND GND 35 GND GND GND GND GND ADC_T0_CH 1_N ADC_T0_CH 1_P GND 36 GND GND GND GND GND GND GND GND 37 GND GND GND GND GND GND GND GND 38 GND GND GND GND GND GND GND GND 39 GND GND GND GND GN...

Page 75: ...5 3V3 GND 3V3 GND 3V3 GND 3V3 GND 46 GND ADCIO_02 GND ADCIO_06 GND ADCIO_10 GND ADCIO_14 47 ADCIO_00 GND ADCIO_04 GND ADCIO_08 GND ADCIO_12 GND 48 GND ADCIO_03 GND ADCIO_07 GND ADCIO_11 GND ADCIO_15 49 ADCIO_01 GND ADCIO_05 GND ADCIO_09 GND ADCIO_13 GND 50 GND I2C_SCL GND I2C_SDA GND ADCIO_VAD J GND ADCIO_VAD J Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 ww...

Page 76: ...1 3 0 2 1 3 01 23 Tile Channel JHC6 ADC_T0_CH0 ADC_T0_CH1 ADC_T0_CH2 ADC_T0_CH3 JHC5 ADC_T2_CH01 ADC_T2_CH23 JHC8 ADC_T1_CH0 ADC_T1_CH1 ADC_T1_CH2 ADC_T1_CH3 JHC7 ADC X25992 112321 Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 76 Send Feedback ...

Page 77: ...rs and pinout as defined in XM650 755 Connector Pinouts For signal break out Carlisle CoreHC2 connectors and cable assemblies are used Digital I O and I2C are supported on headers The XM755 module features are 16 ADC differential signals to 4 male Carlisle CoreHC2 connector pads 16 DACs differential signals to 4 male Carlisle CoreHC2 connector pads 2 ADC inputs compression mount SMAs through low f...

Page 78: ...on a header strip 12V 5V0 3V3 VCCADJ DAC VCCADJ_ADC DAV_AVTT and GND I2C signals access on a header strip The XM650 balun add on card demonstrations DAC to ADC loopback with a 16T16R configuration of N79 baluns and filters There is no external connectivity to the ADC or DAC signals Digital I O and I2C are supported on headers The XM650 module features are 16 DAC outputs looped back to 16 ADC input...

Page 79: ... TR the mated height between the boards will be 4 0 mm No component is placed on the bottom side of the module XM755 Dimensions Length 9 85 250 19 mm Width 4 90 124 46 mm Thickness 0 065 1 651 mm Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 79 Send Feedback ...

Page 80: ...e 29 XM755 Board Dimensions XM650 Dimensions Length 9 85 250 19 mm Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 80 Send Feedback ...

Page 81: ...oles Keepouts There are four jack screws on the module and two edge standoff as shown in the figure above The boards are screwed to the ZCU670 board Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 81 Send Feedback ...

Page 82: ...94 Description Jack screw press in standoff 4 40 0 625 aluminum standoff Data sheet See the Samtec website Functional Description Cables SMAs XM755 Cables Carlisle Core HC2 8 Channel Male 3 5 mm TM40 0157 00 Figure 31 Carlisle Core HC2 8 Channel Male Cable Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 82 Send Feedback ...

Page 83: ... 45o TYP 031 0 790 016 0 411 024 0 600 024 0 600 078 1 986 530 0 013 X23659 041420 SMAs Carlisle Compression Mount SMA TMB V5F2 1L1 Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 83 Send Feedback ...

Page 84: ...B V5F2 1L1 SMA Drawing Figure 34 SMA to SMA Cable Carlisle TM40 0159 00 6 Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 84 Send Feedback ...

Page 85: ...lun Specifications Electrical Specifications at 25 Parameter Frequency MHz Minimum Type Maximum Unit Impedance Ratio secondary primary 2 Frequency range 10 3000 MHz Insertion loss1 10 3000 1 5 3 0 dB Amplitude unbalance 10 3000 0 7 dB Phase unbalance 10 3000 4 Degree Notes 1 Insertion loss is reference to mid band loss 0 8 dB typ Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1...

Page 86: ...ns for the figure above Table 31 Outline Dimensions mm A B C D E F G H J K Wt 0 160 0 150 0 160 0 050 0 040 0 025 0 028 0 065 0 190 0 030 grams 4 06 3 81 4 06 1 27 1 02 0 64 0 71 1 65 4 83 0 76 0 15 Table 32 Medium Frequency Balun Part Number Parameter Value Part number BD1631J50100AHF Manufacturer Anaren Order P N 1173 1059 2 ND Vendor Digikey Description Balun 1 6 GHz 3 1 GHz 50 100 0805 Data sh...

Page 87: ...d RF GND Balanced Port Balanced Port GND NC Orientation Marker Denotes Pin Location Mechanical Outline Dimensions are in Millimeters X23662 012320 Table 33 High Frequency Balun 4 5 GHz Part Number Parameter Value Part number BD3150N50100AHF Manufacturer Anaren Order P N 1173 1069 2 ND Vendor Digikey Description Balun 3 1 GHz 5 GHz 50 100 0404 Data sheet See the Anaren website Appendix D HW XM650 7...

Page 88: ... Parameter Value Part number BD60120N50100AHF Manufacturer Anaren Order P N BD60120N50100AHF ND Vendor Digikey Description RF balun 5 9 GHz 11 7 GHz 50 100Ω 0404 Data sheet See the Anaren website Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 88 Send Feedback ...

Page 89: ...RF Cages Table 35 RF Cages Parameter Value Part number LT 7925 Manufacturer Leader Tech Order P N LT 7925 Vendor Leader Tech Description EMI cage Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 89 Send Feedback ...

Page 90: ...ata sheet See the Murata website Table 37 N79 Balun Parameter Value Part number LDB184G7BAAFA065TEMP Manufacturer Murata Order P N LDB184G7BAAFA065TEMP Vendor Murata Description Chip multilayer Balun 4 4 GHz 5 GHz Data sheet See the Murata website Header There are a total of 20 DACIO and 20 ADCIO digital I O pins on the header strips Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG153...

Page 91: ...Figure 42 High ADCIO and DACIO Digital I O Header Pins Appendix D HW XM650 755 Balun Daughter Cards for RFSoC EVM UG1532 v1 0 March 30 2022 www xilinx com ZCU670 Board User Guide 91 Send Feedback ...

Page 92: ... All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concepts and address frequently asked questions To access the Design Hubs In DocNav click the Design Hubs View tab On the Xilinx website see the Design Hubs page Note For more information on Doc...

Page 93: ...Board Setup Tutorial XTP699 13 Micron Technology MTA4ATF51264HZ 2G6E1 MT40A512M16JY 075E MT25QU02GCBB8E12 0SIT data sheets 14 Standard Microsystems Corporation SMSC USB3320 data sheet 15 SanDisk Corporation 16 SD Association 17 Skyworks Solutions Inc 18 Silicon Labs SI570 SI5341B SI5382A 19 Texas Instruments TCA9548A PCA9544A TCA6416A DP83867 MSP430FS342 TPS51200DRCT 20 PCI SIG 21 Samtec Inc SEAF ...

Page 94: ...rrors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at https www xilinx com legal htm tos IP cor...

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