Appendix B
Xilinx Design Constraints
Overview
The Xilinx design constraints (XDC) file template for the ZCU670 board provides for designs
targeting the ZCU670 evaluation board. Net names in the constraints listed correlate with net
names on the latest ZCU670 evaluation board schematic. Identify the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (
) for more information.
The HSPC FMCP connector J28 is connected to Zynq
®
Ult™ RFSoC U1 banks powered
by the variable voltage VADJ_FMC. The FMC bank I/O standards must be uniquely defined by
each customer because different FMC cards implement different circuitry.
IMPORTANT! To access the XDC file, click the Documentation tab on the
and select Board Files under Document Type.
Appendix B: Xilinx Design Constraints
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
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