Miscellaneous Pins
© 2010 Advanced Micro Devices, Inc.
47062 SR5650 Databook 2.00
Proprietary
3-7
3.7
Miscellaneous Pins
3.8
Power Pins
Table 3-7 Miscellaneous Pins
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination Functional Description
I2C_CLK
I/O
VDD18
VSS
–
I
2
C interface clock signal. Can also be used as GPIO.
I2C_DATA
I/O
VDD18
VSS
–
I
2
C interface data signal. Can also be used as GPIO.
STRP_DATA
I/O
VDD18
VSS
–
I
2
C interface data signal for external EEPROM based strap loading.
See the SR5650 Strap Document for details on the operation.
TESTMODE
I
VDD18
VSS
–
When High, puts the SR5650 in test mode and disables the
SR5650 from operating normally.
DFT_GPIO5/
SYNCFLOODIN#
I/O
VDD18
VSS
Pull Up
Output for DFT TESTMODE, or Syncflood input for triggering a
HyperTransport™ syncflood event.
Because the pin is used as a pin strap during the power-on of the
SR5650, an external device must not drive the pin until after
SYSRESET# is deasserted. Also, the pin is not 3.3V tolerant and
needs a level shifter when interfacing to a 3.3V line.
The pin cannot be used for general GPIO functions.
DFT_GPIO[4:1],
I/O
VDD18
VSS
Pull Up
Outputs for DFT TESTMODE. These pins cannot be used for
general GPIO functions.
DFT_GPIO0/NMI#
I/O
VDD18
VSS
Pull Up
Output for DFT TESTMODE, or NMI input for triggering an
upstream NMI packet to the processor complex.
Because the pin is used as a pin strap during the power-on of the
SR5650, an external device must not drive the pin until after
SYSRESET# is deasserted. Also, the pin is not 3.3V tolerant and
needs a level shifter when interfacing to a 3.3V line.
The pin cannot be used for general GPIO functions.
DBG_GPIO3/
NON_FATAL_CORR#
I/O
VDD18
VSS
Pull Up
Output for Debug Bus, or Non-Fatal or Correctable Error signal to
BMC. The pin is not 3.3V tolerant and needs a level shifter when
interfacing to a 3.3V line. When used as a debug bus output, the
pin’s NON_FATAL_CORR# function is overridden.
The pin cannot be used for general GPIO functions.
DBG_GPIO0/
SERR_FATAL#
I/O
VDD18
VSS
Pull Up
Output for Debug Bus, or System Error or Fatal Error signal to
BMC. The pin is not 3.3V tolerant and needs a level shifter when
interfacing to a 3.3V line. When used as a debug bus output, the
pin’s SERR_FATAL# function is overridden.
The pin cannot be used for general GPIO functions.
THERMALDIODE_P,
THERMALDIODE_N
A-O
–
–
–
Diode connections to external SM Bus microcontroller for
monitoring IC thermal characteristics.
Table 3-8 Power Pins
Pin Name
Voltage
Pin
Count Ball Reference
Comments
VDDC
1.1V
18
L14, L16, M13, M15, N12,
N14, N16, P13, P15, P17,
R12, R14, R16, T13, T15,
T17, U14, U16
Core power
VDD18
1.8V
5
A18, B18, C18, D18, E18
I/O Power for GPIO pads
VDDPCIE
1.1 V
39
A3, B2, C1, C3, D4, E5, F6,
G8, G10, H7, H9, H11, K7,
L8, M7, N8, P7, R8, T7, V7,
W8, Y7, AA8, AA10, AA12,
AA16, AA18, AB7, AB9,
AB11, AB13, AB15, AB17,
AB19, AC6, AD5, AE4, AF3,
AG2
PCI Express interface main I/O and PLL power