47062 SR5650 Databook 2.00
© 2010 Advanced Micro Devices, Inc.
1-2
Proprietary
Software Features
1.2.4 Multiple Processor Support
•
Supports multiple-socket configurations for up to 8 processors on the same system.
1.2.5 Multiple Northbridge Support
•
Supports multiple-SR5690/5670/5650 configurations on the same system. See
Section 2.3, “Multiple Northbridge
1.2.6 Power Management Features
•
Fully supports ACPI states S1, S3, S4, and S5.
•
The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—
On, Standby, Suspend, and Off. Each power state can be achieved by software control bits.
•
Support for AMD PowerNow!™ technology.
•
Clocks are controlled dynamically using a mechanism that is transparent to the software. The ASIC hardware detects
idle blocks and turns off the clocks to those blocks in order to reduce power consumption.
•
Supports dynamic lane reduction for the PCIe interfaces, adjusting to the task the number of lanes employed.
1.2.7 PC Design Guide Compliance
The SR5650 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft
®
for WHQL
certification.
1.2.8 Test Capability Features
The SR5650 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per
Million) ratio:
•
Full scan implementation on the digital core logic which provides about 97% fault coverage through ATPG
(Automatic Test Pattern Generation Vectors).
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•
A JTAG test mode in order to allow board level testing of neighboring devices.
•
An XOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level.
•
Access to the analog modules and PLLs in the SR5650 in order to allow full evaluation and characterization of these
modules.
•
IDDQ mode support to allow chip evaluation through current leakage measurements.
•
Highly advanced signal observability through the debug port.
These test modes can be accessed through the settings of the instruction register of the JTAG circuitry.
1.2.9 Packaging
•
Single chip solution in 65nm, 1.1V CMOS technology.
•
Flip chip design in a 29mm x 29mm 692-FCBGA package.
1.3
Software Features
•
Supports Windows Server
®
2003, Windows Server
®
2008, Red Hat Enterprise Linux, SUSE Linux, and Solaris.
•
Supports corporate manageability requirements such as DMI.
•
ACPI support.
•
Full write combining support for maximum performance.
•
Comprehensive OS and API support.
•
Extensive Power Management support.
