AMD Geode SC3200 Data Book Download

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AMD Geode™ SC3200 Processor Data Book

AMD Geode™ SC3200 Processor
Data Book

February 2007

Publication ID: 32581C

Summary of Contents for Geode SC3200

Page 1: ...AMD Geode SC3200 Processor Data Book AMD Geode SC3200 Processor Data Book February 2007 Publication ID 32581C...

Page 2: ...particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant in...

Page 3: ...7 3 2 Strap Options 44 3 3 Multiplexing Configuration 45 3 4 Signal Descriptions 49 4 0 General Configuration Block 69 4 1 Configuration Block Addresses 69 4 2 Multiplexing Interrupt Selection and Bas...

Page 4: ...cture 310 7 2 Functional Description 311 7 3 Register Descriptions 327 8 0 Debugging and Monitoring 349 8 1 Testability JTAG 349 9 0 Electrical Specifications 351 9 1 General Specifications 351 9 2 DC...

Page 5: ...tions 119 Figure 5 15 ACCESS bus Data Transaction 120 Figure 5 16 ACCESS bus Acknowledge Cycle 120 Figure 5 17 A Complete ACCESS bus Data Transaction 121 Figure 5 18 UART Mode Register Bank Architectu...

Page 6: ...Read Operation Timing Diagram 379 Figure 9 20 Sub ISA Write Operation Timing Diagram 380 Figure 9 21 LPC Output Timing Diagram 381 Figure 9 22 LPC Input Timing Diagram 381 Figure 9 23 IDE Reset Timin...

Page 7: ...C97 Low Power Mode Timing Diagram 414 Figure 9 53 PWRBTN Trigger and ONCTL Timing Diagram 415 Figure 9 54 GPWIO and ONCTL Timing Diagram 415 Figure 9 55 Power Up Sequencing With PWRBTN Timing Diagram...

Page 8: ...8 AMD Geode SC3200 Processor Data Book List of Figures 32581C...

Page 9: ...isters 93 Table 5 4 SIO Control and Configuration Register Map 95 Table 5 5 SIO Control and Configuration Registers 95 Table 5 6 Relevant RTC Configuration Registers 96 Table 5 7 RTC Configuration Reg...

Page 10: ...Table 5 56 Bank 1 Bit Map 137 Table 5 57 Bank 2 Bit Map 137 Table 5 58 Bank 3 Bit Map 137 Table 5 59 Bank 4 Bit Map 137 Table 5 60 Bank 5 Bit Map 138 Table 5 61 Bank 6 Bit Map 138 Table 5 62 Bank 7 Bi...

Page 11: ...e Registers 300 Table 6 45 Programmable Interval Timer Registers 301 Table 6 46 Programmable Interrupt Controller Registers 303 Table 6 47 Keyboard Controller Registers 306 Table 6 48 Real Time Clock...

Page 12: ...Port Timing Parameters 405 Table 9 31 Standard Parallel Port Timing Parameters 406 Table 9 33 ECP Forward Mode Timing Parameters 408 Table 9 34 ECP Reverse Mode Timing Parameters 409 Table 9 35 AC Res...

Page 13: ...Inter face ACPI version 1 0 compliant power management and an audio codec interface The SuperI O module has three serial ports UART1 UART2 and UART3 with fast infrared a parallel port two ACCESS bus...

Page 14: ...er Hardware graphics frame buffer compress decompress Hardware cursor 32x32 pixels Video Processor Module Video Accelerator Flexible video scaling support of up to 800 horizontally and vertically Bili...

Page 15: ...USB USB OpenHCI v1 0 compliant Three ports SuperI O Module Real Time Clock RTC DS1287 MC146818 and PC87911 compatible Multi century calendar ACCESS bus ACB Interface Two ACB interface ports Parallel P...

Page 16: ...16 AMD Geode SC3200 Processor Data Book Overview 32581C...

Page 17: ...Revision 8 1 1 Specification Update documents The SC3200 processor s device ID is contained in the GX1 module Software can detect the revision by reading the DIR0 and DIR1 Configuration registers see...

Page 18: ...te as 0 21 RSVD Reserved Must be written as 0 Wait state on the X Bus x_data during read cycles for debug only 20 18 SDCLKRATE SDRAM Clock Ratio Selects SDRAM clock ratio 000 Reserved 100 3 5 001 2 10...

Page 19: ...d Write as 0 13 12 SDCLKCTL SDCLK High Drive Slew Control Controls the high drive and slew rate of SDCLK 3 0 and SDCLK_OUT 11 is strongest 00 is weakest 11 RSVD Reserved Write as 0 10 SDCLKOMSK Enable...

Page 20: ...ece of output data This parameter significantly affects system performance Optimal setting should be used If an SODIMM is used BIOS can interrogate EEPROM across the ACCESS bus interface to determine...

Page 21: ...7 TE Test Enable TEST 3 0 0 TEST 3 0 are driven low normal operation 1 TEST 3 0 pins are used to output test information 16 TECTL Test Enable Shared Control Pins 0 RASB CASB CKEB WEB normal operation...

Page 22: ...ide a summary of how the Video Processor interfaces with the other modules of the SC3200 For detailed information about the Video Processor see Section 7 0 Video Proces sor Module on page 309 2 2 1 GX...

Page 23: ...k throttling CPU_RST resets the CPU and is asserted for approxi mately 100 s after the negation of POR PCI bus interface signals 2 4 Super I O Module The SuperI O SIO module is a PC98 and ACPI complia...

Page 24: ...24 AMD Geode SC3200 Processor Data Book Architecture Overview 32581C...

Page 25: ...6 PE TFTD14 SLCT TFTD15 SLIN ASTRB TFTD16 STB WRITE TFTD17 Parallel Port IDE_ADDR2 TFTD4 IDE_DATA15 TFTD7 IDE_IOR0 TFTD10 IDE_IOW0 TFTD9 IDE_CS0 TFTD5 IDE_IORDY0 TFTD11 IDE_DREQ0 TFTD8 IDE_DACK0 TFTD...

Page 26: ...CLK AC97_RST GPIO16 PC_BEEP Power CLK32 GPWIO 2 0 LED ONCTL PWRBTN PWRCNT 1 2 THRM TCK TDI TDO TMS TRST JTAG TEST1 PLL6B TEST0 PLL2B GXCLK FP_VDD_ON TEST3 TEST2 PLL5B GTEST Test and TDP TDN GPIO11 RI2...

Page 27: ...LPC Registers Function 0 on page 188 2 Configuration settings listed in this table are with regard to the Pin Multiplexing Register PMR See Section 4 2 Multiplexing Interrupt Selection and Base Addre...

Page 28: ...AD8 GP32 GP13 VIO VSS AD3 AD6 AD5 VSS AD4 ICS1 AD1 VCORE VSS GP12 AB1D AB1C VCORE SDO SYNC ACCK VSS VSS VSS VSS VCORE VCORE VCORE VCORE AD0 IAD2 AD2 VCORE IDAT15 IDAT14 IDAT13 VSS VIO VSS IDAT12 IDAT1...

Page 29: ...3 3 0 and PMR 27 0 and FPCI_MON 0 TFTD13 O O1 4 PMR 23 3 1 and PMR 27 0 and FPCI_MON 0 F_AD7 O O14 14 PMR 23 3 0 and PMR 27 1 or FPCI_MON 1 A19 VSS GND A205 2 PD6 I O INT O14 14 VIO PMR 23 3 0 and PMR...

Page 30: ...VSS GND B23 NC B24 VSS GND Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration B25 VSS GND B26 NC B275 DPOS_PORT2 I O INUSB OUSB AVC CUSB B285 DNEG_PORT2 I O INUSB OUSB AVC CUSB B29 G...

Page 31: ...uffer1 Type Power Rail Configuration C28 GPIO9 I O PU22 5 INTS O1 4 VIO PMR 18 0 and PMR 8 0 DCD2 I PU22 5 INTS PMR 18 1 and PMR 8 0 IDE_IOW1 O PU22 5 O1 4 PMR 18 0 and PMR 8 1 SDTEST2 O PU22 5 O2 5 P...

Page 32: ...or FPCI_MON 1 D23 VIO PWR D24 NC D25 VSS GND Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration D26 INTA I PU22 5 INPCI VIO D27 AVCCUSB PWR D28 GPIO6 I O PU22 5 INTS O1 4 VIO PMR 18...

Page 33: ...on J31 GPIO39 I O PU22 5 INPCI OPCI VIO PMR 14 4 0 and PMR 22 4 0 SERIRQ I O INPCI OPCI PMR 14 4 1 and PMR 22 4 1 K1 AD11 I O INPCI OPCI VIO Cycle Multiplexed A11 O OPCI K2 VIO PWR K3 VSS GND K4 AD14...

Page 34: ...GND N16 VSS GND N17 VSS GND N18 VCORE PWR N19 VCORE PWR N28 VSS GND Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration N29 GPIO12 I O PU22 5 INAB O8 8 VIO PMR 19 0 AB2C I O PU22 5 IN...

Page 35: ...ATA_IN I INT VIO FPCI_MON 0 F_GNT0 O O2 5 FPCI_MON 1 V1 IDE_DATA15 I O INTS1 TS1 4 VIO PMR 24 0 TFTD7 O O1 4 PMR 24 1 V2 IDE_DATA14 I O INTS1 TS1 4 VIO PMR 24 0 TFTD17 O O1 4 PMR 24 1 V3 IDE_DATA13 I...

Page 36: ...VIO PMR 24 0 TFTD12 O O1 4 PMR 24 1 Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AB285 MD24 I O INT TS2 5 VIO AB29 VIO PWR AB30 VSS GND AB31 DQM7 O O2 5 VIO AC1 IDE_DATA1 I O IN...

Page 37: ...AH9 POR I INTS VIO AH105 MD3 I O INT TS2 5 VIO AH115 MD5 I O INT TS2 5 VIO Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AH12 WEA O O2 5 VIO AH13 VSS GND AH14 VIO PWR AH15 MA1 O...

Page 38: ...O O2 5 VIO AK13 VIO PWR AK14 BA1 O O2 5 VIO Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AK15 MA2 O O2 5 VIO AK16 VIO PWR AK175 MD35 I O INT TS2 5 VIO AK185 MD46 I O INT TS2 5...

Page 39: ...definitions refer to Table 9 10 Buffer Types on page 357 2 Is 5V tolerant ACK AFD DSTRB BUSY WAIT ERR INIT PD 7 0 PE SLCT SLIN ASTRB STB WRITE ONCTL PWRCNT 2 1 3 The TFT_PRSNT strap determines the pow...

Page 40: ...D27 AVSSPLL2 C16 AVSSPLL3 AK3 AVSSUSB C27 BA0 AJ13 BA1 AK14 BHE E4 BIT_CLK U30 BOOT16 C8 BUSY WAIT B17 C BE0 L1 C BE1 J2 C BE2 F3 C BE3 H4 CASA AJ12 CKEA AL22 CLK27M AA4 CLK32 AH8 CLKSEL0 B8 CLKSEL1 A...

Page 41: ...IDE_DATA12 W3 IDE_DATA13 V3 IDE_DATA14 V2 IDE_DATA15 V1 IDE_DREQ0 AC4 IDE_DREQ1 C31 IDE_IOR0 Y4 IDE_IOR1 D28 IDE_IORDY0 AD1 IDE_IORDY1 B29 IDE_IOW0 AD2 IDE_IOW1 C28 IDE_RST AA1 INIT B21 INTA D26 INTB...

Page 42: ...IN2 AL8 SDATA_OUT P29 SDCLK_IN AJ27 SDCLK_OUT AK28 SDCLK0 AJ21 SDCLK1 W29 SDCLK2 AA28 SDCLK3 V29 SDTEST0 C30 SDTEST1 B29 SDTEST2 C28 SDTEST3 E28 SDTEST4 C31 SDTEST5 D28 SERIRQ J31 SERR H1 SIN1 AG2 SIN...

Page 43: ...al Name Ball No VSS Total of 96 A1 A13 A16 A19 A31 B1 B7 B10 B14 B22 B24 B25 B30 C12 C14 C15 D7 D13 D19 D25 G2 G4 G28 G30 K3 K30 M1 M31 N4 N15 N16 N17 N28 P15 P16 P17 R1 R2 R3 R4 R13 R14 R15 R16 R17 R...

Page 44: ...grammed at reset by CLKSEL 3 0 Note Values for GCB I O Offset 10h 3 0 and 1Eh 3 0 are not the same CLKSEL1 SOUT1 AF3 PD100 CLKSEL2 SOUT2 D29 PD100 CLKSEL3 SYNC P30 PD100 BOOT16 ROMCS C8 PD100 Enable b...

Page 45: ...ed with GPIO except GPIO12 GPIO13 and GPIO16 Table 3 5 Two Signal Group Multiplexing Ball No Default Alternate Signal Configuration Signal Configuration IDE TFT PCI GPIO System AD3 IDE_ADDR0 PMR 24 0...

Page 46: ...Test E28 SIN2 PMR 28 0 SDTEST3 PMR 28 1 AC97 FPCI Monitoring U29 AC97_RST FPCI_MON 0 F_STOP FPCI_MON 1 U31 SDATA_IN F_GNT0 U30 BIT_CLK F_TRDY Internal Test Internal Test AG4 PLL6B PMR 29 0 TEST1 PMR...

Page 47: ...and PMR 5 0 IOCS0 PMR 23 0 and PMR 5 1 TFTDCK PMR 23 1 A9 GPIO20 PMR 23 0 and PMR 7 0 DOCCS PMR 23 0 and PMR 7 1 TFTD0 PMR 23 1 D10 GPIO1 PMR 23 0 and PMR 13 0 IOCS1 PMR 23 0 and PMR 13 1 TFTD12 PMR 2...

Page 48: ...Configuration Signal Configuration GPIO UART2 IDE2 Internal Test C30 GPIO7 PMR 17 0 and PMR 8 0 RTS2 PMR 17 1 and PMR 8 0 IDE_DACK1 PMR 17 0 and PMR 8 1 SDTEST0 PMR 17 1 and PMR 8 1 C31 GPIO8 CTS2 ID...

Page 49: ...pull down resistor of 1 5 K must be used ROMCS LPC_ROM D6 I LPC_ROM This strap signal forces selecting of the LPC bus and sets bit F0BAR1 I O Offset 10h 15 LPC ROM Addressing Enable It enables the SC3...

Page 50: ...3 4 1 System Interface Continued Signal Name Ball No Type Description Mux 3 4 2 Memory Interface Signals Signal Name Ball No Type Description Mux MD 63 0 See Table 3 3 on page 40 I O Memory Data Bus...

Page 51: ...These signals should have an external pull down resistor of 33 K SDCLK3 V29 O SDRAM Clocks SDRAM uses these clocks to sample all control address and data lines To ensure that the Suspend mode functio...

Page 52: ...h the IDE interface or the Par allel Port See Table 3 5 on page 45 and Table 3 6 on page 46 for details 3 4 5 ACCESS bus Interface Signals Signal Name Ball No Type Description Mux AB1C N31 I O ACCESS...

Page 53: ...tiplexed Command and Byte Enables During the address phase of a transaction when FRAME is active C BE 3 0 define the bus command During the data phase C BE 3 0 are used as byte enables The byte enable...

Page 54: ...onjunction with IRDY A data phase is complete on any PCI clock in which both TRDY and IRDY are sampled as asserted During a read TRDY indicates that valid data is present on AD 31 0 During a write it...

Page 55: ...ive decode basis As a master if no DEVSEL is detected within and up to the subtractive decode clock a master abort cycle is initiated except for special cycles which do not expect a DEVSEL returned Th...

Page 56: ...5 GNT1 C6 O Grant Lines GNT 1 0 indicate to the requesting mas ter that it has been granted access to the bus Each mas ter has its own GNT line GNT can be retracted at any time a higher REQ is receive...

Page 57: ...l timing is as fol lows In a read cycle TRDE has the same timing as RD In a write cycle TRDE is asserted to active low at the time WR is asserted It continues being asserted for one PCI clock cycle af...

Page 58: ...pe Description Mux IDE_RST AA1 O IDE Reset This signal resets all the devices that are attached to the IDE interface TFTDCK IDE_ADDR2 U2 O IDE Address Bits These address bits are used to access a regi...

Page 59: ...K1 C30 O GPIO7 RTS2 SDTEST0 IRQ14 AF1 I Interrupt Request Channels 0 and 1 These input sig nals are edge sensitive interrupts that indicate when the IDE device is requesting a CPU interrupt service No...

Page 60: ...elected as CTS2 function but not used tie CTS2 low GPIO8 IDE_DREQ1 DTR1 BOUT1 AG1 O Data Terminal Ready Outputs When low indicate to the modem or other data transfer device that the UART is ready to e...

Page 61: ..._C BE0 INIT B21 O Initialize When low initializes the printer This signal is in TRI STATE after a 1 is loaded into the corresponding control register bit Use an external 4 7 K pull up resis tor TFTD5...

Page 62: ...arallel Port Interface Signals Continued Signal Name Ball No Type Description Mux 3 4 13 Fast Infrared IR Port Interface Signals Signal Name Ball No Type Description Mux IRRX1 AK8 I IR Receive Primary...

Page 63: ...d as SDATA_IN function but not used tie SDATA_IN low F_GNT0 SDATA_IN2 AL8 I Serial Data Input 2 This input receives serial data from the secondary codec This signal has wakeup capability SYNC P30 O Se...

Page 64: ...de using the power button SUSP is an internal signal gen erated from the ACPI block Without an ACPI reset SUSP can be permanently asserted If the USE_SUSP bit in CCR2 of GX1 module is enabled Index C2...

Page 65: ...7 C30 RTS2 IDE_DACK1 SDTEST0 GPIO8 C31 CTS2 IDE_DREQ1 SDTEST4 GPIO9 C28 DCD2 IDE_IOW1 SDTEST2 GPIO10 B29 DSR2 IDE_IORDY1 SDTEST1 GPIO11 AJ8 RI2 IRQ15 GPIO12 N29 AB2C GPIO13 M29 AB2D GPIO14 D9 IOR DOCR...

Page 66: ...O SLIN ASTRB TFTD16 F_STOP U29 O AC97_RST F_DEVSEL V31 O GPIO16 PC_BEEP F_GNT0 U31 O SDATA_IN F_TRDY U30 O BIT_CLK INTR_O D22 O CPU Core Interrupt When enabled this signal provides for monitoring of...

Page 67: ...s These signals are used for internal testing only For normal operation leave unconnected unless programmed as one of their muxed options PLL5B TEST1 AG4 O PLL6B TEST0 AH3 O PLL2B GTEST F30 I Global T...

Page 68: ...ro tection If battery backup is not desired connect VBAT to VSS VSB AL5 PWR 3 3V Standby Power Supply Provides power to the Real Time Clock RTC and ACPI circuitry while the main power supply is turned...

Page 69: ...D Geode SC3200 Specification Update doc ument Reserved bits in the General Configuration block should read as written unless otherwise specified Table 4 1 General Configuration Block Register Summary...

Page 70: ...instead of Parallel Port signals Fast PCI monitoring output signals can be enabled in two ways by setting this bit to 1 or by strapping FPCI_MON ball A4 high The strapped value can be read back at MCR...

Page 71: ...IDE_DATA0 TFTD6 A24 AC1 IDE_DATA1 TFTD16 D23 AC2 IDE_DATA2 TFTD14 C23 AB4 IDE_DATA3 TFTD12 B23 AB1 IDE_DATA4 FP_VDD_ON A23 AA4 IDE_DATA5 CLK27M C22 AA3 IDE_DATA6 IRQ9 B22 AA2 IDE_DATA7 INTD A21 Y3 ID...

Page 72: ...1 Note 1 F_AD6 Note 2 W1 B20 SLIN ASTRB Note 1 TFTD16 Note 1 F_IRDY Note 2 W2 C20 PD3 Note 1 TFTD9 Note 1 F_AD3 Note 2 W3 D20 PD2 Note 1 TFTD8 Note 1 F_AD2 Note 2 Y1 A21 PD1 Note 1 TFTD7 Note 1 F_AD1...

Page 73: ...Flow Control Selects ball functions Ball 0 GPIO IDE Signals 1 Serial Port Signals Name Add l Dependencies Name Add l Dependencies AH4 C30 GPIO7 PMR 8 0 RTS2 PMR 8 0 IDE_DACK1 PMR 8 1 SDTEST0 PMR 8 1...

Page 74: ...cies J28 AK8 IRRX1 None SIN3 None J3 C11 IRTX None SOUT3 None 5 IOCS0SEL Select IOCS0 Selects ball function Works in conjunction with PMR 23 see PMR 23 for definition 4 INTCSEL Select INTC Selects bal...

Page 75: ...cess 9 ROMZWS Enable ZWS for ROMCS Access This bit enables internal activation of ZWS Zero Wait States control for ROMCS access 0 ZWS is not active for ROMCS access 1 ZWS is active for ROMCS access 8...

Page 76: ...lue 00h This register selects the IRQ signal of the combined WATCHDOG and High Resolution timer interrupt This interrupt is shareable with other interrupt sources 7 4 Reserved Write as read 3 0 CBIRQ...

Page 77: ...gnal is 1 or The GX1 module s internal SUSPA signal is 0 and the WD32KPD bit Offset 02h 8 is 0 The 32 KHz input clock is disabled when The GX1 module s internal SUSPA signal is 0 and the WD32KPD bit i...

Page 78: ...t 00h 01h WATCHDOG Timeout Register WDTO R W Reset Value 0000h This register specifies the programmed WATCHDOG timeout period 15 0 Programmed timeout period Offset 02h 03h WATCHDOG Configuration Regis...

Page 79: ...led when the GX1 module s inter nal SUSPA signal is 0 and the TM27MPD bit is 1 For more information about signal SUSPA see Section 4 4 2 1 Usage Hints on page 79 and the AMD Geode GX1 Processor Data B...

Page 80: ...0Dh TIMER Configuration Register TMCNFG R W Reset Value 00h This register enables the High Resolution Timer interrupt selects the Timer clock and disables the 27 MHz internal clock during low power st...

Page 81: ...functional description of the RTC Figure 4 2 Clock Generation Block Diagram 32 768 KHz Crystal External PCI Clock PLL5 Internal Fast PCI Clock PLL6 ACPI Clock 14 318 MHz PLL2 Dot Clock Core Clock ADL...

Page 82: ...can vary from 0 to 10 pF The rule of thumb in choosing these capacitors is CL C1 C2 C1 C2 CPARASITIC Example 1 Crystal CL 10 pF CPARASITIC 8 2 pF C1 3 6 pF C2 3 6 pF Example 2 Crystal CL 20 pF CPARASI...

Page 83: ...balls These can be read in the internal Fast PCI Clock field in the CCFC register GCB I O Offset 1Eh 9 8 See Table 4 8 on page 85 details on the CCFC register Note Not all speeds are supported For in...

Page 84: ...CI Interface uses a 33 3 MHz clock that is created by PLL5 and divided by 2 PLL5 uses the 27 MHz clock to output a 66 67 MHz clock PLL5 has a frequency accuracy of 0 1 AC97 The SC3200 generates the 24...

Page 85: ...rved 6 EXPCID Disable External PCI Clock 0 External PCI clock is enabled 1 External PCI clock is disabled 5 GPD Disable Graphic Pixel Reference Clock 0 PLL2 input clock is enabled 1 PLL2 input clock i...

Page 86: ...is used to generate the core clock These bits reflect the value of strap pins CLKSEL 1 0 00 33 3 MHz 01 48 MHz 10 66 7 MHz 11 33 3 MHz 7 4 Reserved 3 0 MVAL Multiplier Value This 4 bit value controls...

Page 87: ...hat provides RTC timekeeping Outstanding Features Full compatibility with ACPI Revision 1 0 requirements System Wakeup Control powered by VSB generates power up request and a PME power management even...

Page 88: ...4 0 Mbps FIR Selectable internal or external modulation demodula tion ASK IR and DASK IR options of SHARP IR Consumer IR TV Remote mode Consumer Remote Control supports RC 5 RC 6 NEC RCA and RECS 80 D...

Page 89: ...and Play ISA Specification Version 1 0a by Intel and Microsoft All sys tem resources assigned to the functional blocks I O address space DMA channels and IRQ lines are config ured in and managed by t...

Page 90: ...structure of the standard PnP config uration register file The SIO Control And Configuration registers are not banked and are accessed by the Index Data register pair only as described above However...

Page 91: ...after VSB is powered up The SIO module wakes up with the default setup as fol lows When a hardware reset occurs The configuration base address is 2Eh 15Ch or None according to the IO_SIOCFG_IN bit val...

Page 92: ...nfiguration Registers Index 60h 75h These registers are used to manage the resource allocation to the functional blocks The I O port base address descriptor 0 is a pair of registers at Index 60h 61h h...

Page 93: ...its 7 0 for I O Descriptor 0 Index 62h I O Port Base Address Bits 15 8 Descriptor 1 R W 7 0 Descriptor 1 A 15 8 Selects I O lower limit address bits 15 8 for I O Descriptor 1 Index 63h I O Port Base A...

Page 94: ...hannel 7 3 Reserved 2 0 DMA 1 Channel Select This bit field selects the DMA channel for DMA 1 The valid choices are 0 3 where a value of 0 selects DMA channel 0 1 selects channel 1 etc A value of 4 in...

Page 95: ...tch This bit controls bits 7 and 6 of this register Once this bit is set to 1 by software it can be cleared to 0 only by a hardware reset 0 Bits 7 and 6 of this register are R W bits Default 1 Bits 7...

Page 96: ...isters Table 5 6 Relevant RTC Configuration Registers Index Type Configuration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not access...

Page 97: ...the Extended RAM access Default 1 Writes to bytes 00h 1Fh of the Extended RAM are ignored 4 Block Extended RAM Read This bit controls read from bytes 00h 1Fh of the Extended RAM 0 No effect on Extend...

Page 98: ...uration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not accessible 1 00h 60h R W Base Address MSB register 00h 61h R W Base Address L...

Page 99: ...Table 5 10 IRCP SP3 Configuration Register Bit Description Index F0h Infrared Communication Port Serial Port 3 Configuration Register R W Reset Value 02h 7 Bank Select Enable Enables bank switching 0...

Page 100: ...75h RO Report no DMA assignment 04h 04h F0h R W Serial Ports 1 and 2 Configuration register 02h 02h Table 5 12 Serial Ports 1 and 2 Configuration Register Bit Description Index F0h Serial Ports 1 and...

Page 101: ...page 93 for descriptions of the oth ers Table 5 13 Relevant ACB1 and ACB2 Registers Index Type Configuration Register or Action Reset Value 30h R W Activate See also bit 0 of the SIOCF1 register 00h...

Page 102: ...are RO 00000b Bit 2 for A10 should be 0b 02h 61h R W Base Address LSB register Bits 1 and 0 A1 and A0 are RO 00b For ECP Mode 4 EPP or when using the Extended registers bit 2 A2 should also be 0b 78h...

Page 103: ...nal as the basic clock for timekeeping The 32 768 KHz clock can be sup plied by the internal oscillator circuit or by an external oscillator see Section 5 5 2 2 External Oscillator on page 104 5 5 2 1...

Page 104: ...f square or sine wave of 0 0V to VCORE amplitude The signal should have a duty cycle of approximately 50 It should be sourced from a battery backed source in order to oscillate during power down This...

Page 105: ...s mecha nism enables new time parameters to be loaded in the RTC Method 2 1 Access the RTC registers after detection of an Update Ended interrupt This implies that an update has just been completed an...

Page 106: ...power supply or VSB main battery To assure that the module uses power from VSB and not from VBAT the VSB voltage should be maintained above its minimum as detailed in Section 9 0 Electrical Specifica...

Page 107: ...off spurious bus transactions from the host may occur To protect the RTC internal regis ters from corruption all inputs are automatically locked out The lockout condition is asserted when VSB is lowe...

Page 108: ...wer down The RAMs are Standard RAM Extended RAM The memory maps and register content of the RAMs is provided in Section 5 5 4 RTC General Purpose RAM Map on page 113 The first 14 bytes and 3 programma...

Page 109: ...Day Of Week Register VPP PUR 07h R W DOM Date Of Month Register VPP PUR 08h R W MON Month Register VPP PUR 09h R W YER Year Register VPP PUR 0Ah R W CRA RTC Control Register A Bit specific 0Bh R W CR...

Page 110: ...er A CRA R W Reset Type Bit Specific This register controls test selection among other functions This register cannot be written before reading bit 7 of CRD 7 Update in Progress RO This bit is not aff...

Page 111: ...leared to 0 as long as bit 7 of the CRD Register is reads 0 In addition this bit is cleared to 0 when this register is read 0 No alarm detected since the last read 1 Alarm condition detected 4 Update...

Page 112: ...70 2 0 1 0 0 0 244141 3 0 1 0 1 0 488281 4 0 1 1 0 0 976562 5 0 1 1 1 1 953125 6 1 0 0 0 3 906250 7 1 0 0 1 7 812500 8 1 0 1 0 15 625000 9 1 0 1 1 31 250000 10 1 1 0 0 62 500000 11 1 1 0 1 125 000000...

Page 113: ...Change the backup battery while normal operating power is present and not in backup mode to maintain valid time and register information If a low leakage capacitor is connected to VBAT the battery may...

Page 114: ...f matching can be used as a wakeup event The CEIR address detection operates independently of the serial port with the IR which is powered down with the rest of the system Whenever an IR signal is det...

Page 115: ...Type Name Reset Value 00h R W1C WKSR Wakeup Events Status Register 00h 01h R W WKCR Wakeup Events Control Register 03h 02h R W WKCFG Wakeup Configuration Register 00h Table 5 28 Bank 1 CEIR Wakeup Co...

Page 116: ...n 0 Event not detected Default 1 Event detected Offset 01h Wakeup Events Control Register WKCR R W Reset Value 03h This register is set to 03h on power up of VPP or software reset Detected wakeup even...

Page 117: ...Address Mask If the corresponding bit is 0 the address bit is not masked enabled for compare If the corresponding bit is 1 the address bit is masked ignored during compare Bank 1 Offset 07h CEIR Addre...

Page 118: ...are not used when the RC 5 protocol is selected NEC protocol The header pulse width must fall within this range in order for the header to be considered valid The nominal value is 9 ms for a 38 KHz ca...

Page 119: ...mpled during the high state of the serial clock ABC Consequently throughout the clock s high period the data should remain stable see Figure 5 13 Any changes on the ABD line during the high state of t...

Page 120: ...ver must pull down the ABD line during the ACK clock pulse signalling that it has cor rectly received the last data byte and is ready to receive the next byte Figure 5 16 illustrates the ACK cycle Fig...

Page 121: ...Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands Control of the bus is initially determined according to address bits and cloc...

Page 122: ...lso check that ACBST 3 is cleared and clear it if required 2 Write the data byte to be transmitted to the ACBSDA When either ACBST 5 or ACBST 4 is set an interrupt is generated When the slave responds...

Page 123: ...vice continues to search the received message for a match If an address match or a global match is detected 1 The device asserts its ABD pin during the acknowl edge cycle 2 ACBCST 2 and ACBST 2 are se...

Page 124: ...ed below This register maintains the current ACB status On reset and when the ACB is disabled ACBST is cleared 00h 7 SLVSTP Slave Stop R W1C Writing 0 to SLVSTP is ignored 0 Writing 1 or ACB disabled...

Page 125: ...Condition or repeated Start and a Stop Condition including illegal Start or Stop Condition 1 In slave mode ACBCTL1 GCMEN is set and the address byte the first byte transferred after a Start Condition...

Page 126: ...master of the bus ACBST 1 1 setting START and then writing to ACBSDA generates a Start Condition If a transmission is already in progress a repeated Start Condition is generated This condition can be...

Page 127: ...cond level offsets EPP and second level offset registers are available only when the base address is 8 byte aligned Parallel Port functional block bit maps are shown in Table 5 35 and Table 5 36 Table...

Page 128: ...400h CFIFO Data Bits 400h DFIFO Data Bits 400h TFIFO Data Bits 400h CNFGA RSVD Bit 7 of PP Confg0 RSVD 401h CNFGB RSVD Interrupt Request Value Interrupt Select RSVD DMA Channel Select 402h ECR ECP Mod...

Page 129: ...P1 and SP2 Register and Bit Maps for UART Functionality The tables in this subsection provide register and bit maps for Banks 0 through 3 Figure 5 18 UART Mode Register Bank Architecture Bank 0 Bank 1...

Page 130: ...W BSR1 Bank Select 04h 07h RSVD Reserved 1 When bit 7 of this register is set to 1 bits 6 0 of BSR select the bank as shown in Table 5 38 on page 130 Table 5 40 Bank 2 Register Map Offset Type Name 0...

Page 131: ...SVD LOOP ISEN or DCDLP RILP RTS DTR MCR2 RSVD TX_DFR RSVD RTS DTR 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS 07h SPR1 Scratch Data ASCR2 RSVD TXUR4 RXACT4...

Page 132: ...RSVD ETDLBK LOOP RSVD EXT_SL 03h BSR BKSE BSR 6 0 Bank Select 04h EXCR2 LOCK RSVD PRESL 1 0 RSVD 05h RSVD Reserved 06h RXFLV RSVD RFL 4 0 07h TXFLV RSVD TFL 4 0 Table 5 45 Bank 3 Bit Map Register Bits...

Page 133: ...eight registers con trol IR SP3 operation All registers use the same 8 byte address space to indicate offsets 00h through 07h The BSR register selects the active bank and is common to all banks See F...

Page 134: ...BGD L Legacy Baud Generator Divisor Port Low Byte 01h R W LBGD H Legacy Baud Generator Divisor Port High Byte 02h RSVD Reserved 03h W LCR1 Link Control R W BSR1 Bank Select 04h 07h RSVD Reserved 1 Whe...

Page 135: ...RO TFRCC L Transmission Current Count Low Byte 05h R W TFRL H Transmission Frame Length High Byte RO TFRCC H Transmission Current Count High Byte 06h R W RFRML L Reception Frame Maximum Length Low Byt...

Page 136: ...ble 5 55 Bank 0 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h RXD RXD 7 0 Receive Data TXD TXD 7 0 Transmit Data 01h IER1 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER2 TMR_IE SFIF_IE TXEMP_ IE PLD_I...

Page 137: ...ect 04h EXCR2 LOCK RSVD PRESL 1 0 RF_SIZ 1 0 TF_SIZ 1 0 05h RSVD RSVD 06h TXFLV RSVD TFL 5 0 07h RXFLV RSVD RFL 5 0 Table 5 58 Bank 3 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h MID MID 3 0...

Page 138: ...X_LEN PHY_ERR BAD_CRC OVR1 OVR2 06h RFRL L LSTFRC RFRL 7 0 Low Byte Data LSTFRC 7 0 07h RFRL H RFRL 15 8 High Byte Data Table 5 61 Bank 6 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h IRCR3 SH...

Page 139: ...dependent USB interfaces Open Host Controller Interface OpenHCI specification compliant PCI Interface PCI 2 1 compliant PCI master for AC97 and IDE controllers Subtractive agent for unclaimed transact...

Page 140: ...Low Pin Count LPC Interface Based on Intel LPC Interface Specification Revision 1 0 Serial IRQ support 6 2 Module Architecture The Core Logic architecture provides the internal functional blocks show...

Page 141: ...or legacy DMA masters These memory cycles are always forwarded to the Fast PCI interface 6 2 1 4 External PCI Bus The external PCI bus is a fully compliant PCI bus PCI slots are connected to this bus...

Page 142: ...2 3 2 PIO Mode The IDE data port transaction latency consists of address latency asserted latency and recovery latency Address latency occurs when a PCI master cycle targeting the IDE data port is dec...

Page 143: ...er These registers and bit formats are described in Table 6 36 on page 259 Physical Region Descriptor Format Each physical memory region to be transferred is described by a Physical Region Descriptor...

Page 144: ...e Logic and the IDE via providing data toggling STROBE and DMARDY The IDE_DATA 15 0 is latched by receiver on each rising and falling edge of STROBE The transmitter can pause the burst cycle by holdin...

Page 145: ...e DOCR is active otherwise it is inactive DOCW DOCW is asserted on memory write transactions to DOCCS window i e when both DOCCS and MEMW are active DOCW is active otherwise it is inactive RD WR The s...

Page 146: ...ip between a PCI cycle and the corresponding ISA cycle generated Note Not all signals described in Figure 6 2 are available externally See Section 3 4 7 Sub ISA Interface Signals on page 57 for more i...

Page 147: ...isters on the on chip I O data bus When PCI data bus drivers of the Core Logic module are in TRI STATE data transfers between the PCI bus master and PCI bus devices are handled directly via the PCI da...

Page 148: ...sends a bus grant request to the PCI arbiter After the PCI bus has been granted the respective DACK is driven active The Core Logic module generates PCI memory read or write cycles in response to a DM...

Page 149: ...the number of balls on the device Cycle multiplexing is on a bus cycle by bus cycle basis see Figure 6 6 on page 150 where the internal Core Logic PCI bridge arbitrates between PCI cycles and Sub ISA...

Page 150: ...DMA interface signals are not available externally DMA Channels The Core Logic module supports seven DMA channels using two standard 8237 equivalent controllers DMA Con troller 1 contains Channels 0...

Page 151: ...ypes of transfers read write or ver ify The transfer type selected defines the method used to transfer a byte or WORD during one DMA bus cycle For read transfer types the Core Logic module reads data...

Page 152: ...set up by the system before a DMA operation The DMA Page register values are driven on PCI address bits AD 31 16 for 8 bit channels and AD 31 17 for 16 bit channels The middle address portion which se...

Page 153: ...with GPIO39 function See Table 6 4 The Core Logic module allows PCI interrupt signals INTA INTB INTC muxed with GPIO19 IOCHRDY and INTD muxed with IDE_DATA7 to be routed internally to any IRQ signal T...

Page 154: ...ontroller should be programmed with the value 02h slave ID and corresponds to the input on the master controller PIC Shadow Register The PIC registers are shadowed to allow for 0V Suspend to save rest...

Page 155: ...SMI for an NMI Note that NMI is not a ball 6 2 8 Keyboard Support The Core Logic module can actively decode the keyboard controller I O Ports 060h 062h 064h and 066h and gener ate an LPC bus cycle Ke...

Page 156: ...er planes It also supports systems with an external micro controller that is used as a power management controller 6 2 9 1 CPU States The SC3200 supports three CPU states C0 C1 and C3 the Core Logic C...

Page 157: ...ate The SC3200 keeps all context in this state This state corresponds to ACPI sleep state S1 with lower power and longer wake time than in SL1 SL3 Sleep State ACPI S3 In this state the SDRAM is placed...

Page 158: ...nage Transition of the system from a Sleep state to a Work state This is done by the hardware These events are defined as wakeup events Enabled wakeup events to set the WAK_STS bit F1BAR1 I O Offset 0...

Page 159: ...a wakeup event or an inter rupt is generated note that this is regardless of the PWRBTN_EN bit F1BAR1 I O Offset 0Ah 8 Power Button Sleep Event Detection of a high to low transition on the debounced P...

Page 160: ...d is dis cussed in Section 6 2 10 3 Peripheral Power Management on page 162 APM if available is used primarily by CPU power manage ment since the operating system is most capable of report ing the Idl...

Page 161: ...ter F1BAR0 I O Offset 08h The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM The data read from this register can be ignored If the Suspend...

Page 162: ...e timers are F0 Index 81h 7 Video Access Idle Timer Enable F0 Index 82h 7 Video Access Trap Enable F0 Index A6h 15 0 Video Timer Count F0 Index 83h 3 VGA Timer Enable F0 Index 8Bh 6 VGA Timer Base F0...

Page 163: ...eporting The sec ond level of SMI status reporting is set up very much like the top level There are two status reporting registers one read only mirror and one read to clear The data returned by readi...

Page 164: ...vice 1 Idle Timer 81h 4 A0h 15 0 C0h 31 0 CCh 7 0 85h 4 F5h 4 User Defined Device 2 Idle Timer 81h 5 A2h 15 0 C4h 31 0 CDh 7 0 85h 5 F5h 5 User Defined Device 3 Idle Timer 81h 6 A4h 15 0 C8h 31 0 CEh...

Page 165: ...FFh or COM4 I O Port 2E8h 2EFh Support trapping for low I O Port 00h 0Fh and or high I O Port C0h DFh DMA accesses Support hardware status register reads in Core Logic module minimizing SMI overhead S...

Page 166: ...dress of the JMP The target address must be on a 32 byte boundary so bits 4 0 must be written to 0 There is no data transfer with this PRD This PRD allows the creation of a looping mechanism If a PRD...

Page 167: ...by 08h and is now pointing to PRD_3 The SMI Status register is read to clear the End of Page status flag Since Audio Buffer_1 is now empty the software can refill it At the completion of PRD_2 an SMI...

Page 168: ...egisters The codec 32 bit related registers GPIO Status and Control Registers Codec GPIO Status Register F3BAR0 Memory Offset 00h Codec GPIO Control Register F3BAR0 Memory Offset 04h Codec Status Regi...

Page 169: ...ror and Status registers are the top level of hierarchy for the SMI Handler in determining the source of an SMI These two registers are at F1BAR0 Memory Offset 00h Status Mirror and 02h Sta tus The re...

Page 170: ...ermine top level source of SMI F3BAR0 Memory Offset 10h Read to Clear SMI De asserted after all SMI Sources are Cleared Bit 7 ABM5_SMI Bits 15 2 Bit 0 Bit 1 AUDIO_SMI Offset 02h Module to determine se...

Page 171: ...r to the LPC specification directly The goals of the LPC interface are to Enable a system without an ISA bus Reduce the cost of traditional ISA bus devices Use on a motherboard only Perform the same c...

Page 172: ...PCI 33 MHz clock signal PCICLK instead Core Logic module optional LPC signals LDRQ Encoded DMA Bus Master Request Only needed by peripheral that need DMA or bus mastering Peripherals may not share the...

Page 173: ...he Configuration Data Register CDR To access PCI configuration space write the Configuration Address 0CF8h Register with data that specifies the Core Logic module as the device on PCI being accessed a...

Page 174: ...ed GPIO Runtime and Configuration Registers sum marized in Table 6 15 00000001h Page 190 14h 17h 32 R W Base Address Register 1 F0BAR1 Sets the base address for the I O mapped LPC Configuration Regist...

Page 175: ...00h Page 210 8Eh 8 R W VGA Timer Count Register 00h Page 211 8Fh 92h Reserved 00h Page 211 93h 8 R W Miscellaneous Device Control Register 00h Page 211 94h 95h 16 R W Suspend Modulation Register 0000...

Page 176: ...r Defined Device 1 Control Register 00h Page 217 CDh 8 R W User Defined Device 2 Control Register 00h Page 217 CEh 8 R W User Defined Device 3 Control Register 00h Page 217 CFh Reserved 00h Page 217 D...

Page 177: ...IO Signal Configuration Select Register 00000000h Page 223 24h 27h 32 R W GPIO Signal Configuration Access Register 00000044h Page 224 28h 2Bh 32 R W GPIO Reset Control Register 00000000h Page 225 Tab...

Page 178: ...rved 00h Page 234 40h 43h 32 R W Base Address Register 1 F1BAR1 Sets the base address for the I O mapped ACPI Support Registers summarized in Table 6 19 00000001h Page 234 44h FFh Reserved 00h Page 23...

Page 179: ...0h Page 246 0Ah 0Bh 16 R W PM1A_EN PM1A Enable Register 0000h Page 247 0Ch 0Dh 16 R W PM1A_CNT PM1A Control Register 0000h Page 247 0Eh 8 R W ACPI_BIOS_STS Register 00h Page 248 0Fh 8 R W ACPI_BIOS_EN...

Page 180: ...00000000h Page 255 18h 1Bh 32 RO Base Address Register 2 F2BAR2 Reserved for possible future use by the Core Logic module 00000000h Page 255 1Ch 1Fh 32 RO Base Address Register 3 F2BAR3 Reserved for...

Page 181: ...er Registers for Audio Support Summary F3 Index Width Bits Type Name Reset Value Reference Table 6 37 00h 01h 16 RO Vendor Identification Register 100Bh Page 261 02h 03h 16 RO Device Identification Re...

Page 182: ...t Used Page 270 24h 27h 32 R W Audio Bus Master 0 PRD Table Address 00000000h Page 270 28h 8 R W Audio Bus Master 1 Command Register 00h Page 271 29h 8 RC Audio Bus Master 1 SMI Status Register 00h Pa...

Page 183: ...e use by the Core Logic module 00000000h Page 277 20h 23h 32 R W Base Address Register 4 F5BAR4 Reserved for possible future use by the Core Logic module 00000000h Page 277 24h 27h 32 R W Base Address...

Page 184: ...ge 283 0Ch 8 R W Cache Line Size 00h Page 283 0Dh 8 R W Latency Timer 00h Page 283 0Eh 8 RO Header Type 00h Page 283 0Fh 8 RO BIST Register 00h Page 283 10h 13h 32 R W Base Address 0 00000000h Page 28...

Page 185: ...87 28h 2Bh 32 R W HcBulkHeadED 00000000h Page 287 2Ch 2Fh 32 R W HcBulkCurrentED 00000000h Page 287 30h 33h 32 R W HcDoneHead 00000000h Page 287 34h 37h 32 R W HcFmInterval 00002EDFh Page 288 38h 3Bh...

Page 186: ...r Not Used Page 297 0C4h R W DMA Channel 5 Address Register Page 297 0C6h R W DMA Channel 5 Transfer Count Register Page 297 0C8h R W DMA Channel 6 Address Register Page 297 0CAh R W DMA Channel 6 Tra...

Page 187: ...Master Slave PIC OCW2 Page 304 020h 0A0h WO Master Slave PIC OCW3 Page 304 020h 0A0h RO Master Slave PIC Interrupt Request and Service Registers for OCW3 Commands Page 304 Keyboard Controller Registe...

Page 188: ...y are read a byte at a time status bits may be lost or not cleared 6 4 1 Bridge GPIO and LPC Registers Function 0 The register space designated as Function 0 F0 is used to configure Bridge features an...

Page 189: ...ctive Write 1 to clear 13 Received Master Abort This bit is set whenever a master abort cycle occurs A master abort occurs when a PCI cycle is not claimed except for special cycles Write 1 to clear 12...

Page 190: ...unction device bit 7 1 or not bit 7 0 Index 0Fh PCI BIST Register RO Reset Value 00h This register indicates various information about the PCI Built In Self Test BIST mechanism Note This mechanism is...

Page 191: ...ffset 00h 02h 9 Second level SMI status is reported at F1BAR0 I O Offset 04h 06h 5 4 Video Configuration Trap If this bit is set to 1 and an access occurs to one of the configuration registers in PCI...

Page 192: ...PCI Delayed Transactions for Access to I O Address 1F0h 1F7h Primary IDE Channel PIO mode uses repeated I O transactions that are faster when non delayed transactions are used 0 I O addresses complete...

Page 193: ...r clock configuration at power up Index 45h Reserved Reset Value 00h Index 46h PCI Functions Enable Register R W Reset Value FEh 7 6 Reserved Resets to 11 5 F5 PCI Function 5 When asserted set to 1 en...

Page 194: ...pass to IRQ0 3 PIT Counter 0 Enable 0 Sets GATE0 input low 1 Sets GATE0 input high 2 0 ISA Clock Divisor Determines the divisor of the PCI clock used to make the ISA clock which is typically programm...

Page 195: ...s to the configured ROM space asserts ROMCS enabling the write cycle to the Flash device on the ISA bus Otherwise ROMCS is inhibited for writes If strapped for LPC and this bit is set to 1 the cycle r...

Page 196: ...rts 2F8h 2FFh 0 Subtractive 1 Positive 2 COM1 Positive Decode Selects PCI positive or subtractive decoding for accesses to I O ports 3F8h 3FFh 0 Subtractive 1 Positive 1 Keyboard Controller Positive D...

Page 197: ...signals INTB and INTA Note The target interrupt must first be configured as level sensitive via I O Ports 4D0h and 4D1h in order to maintain PCI interrupt compatibility 7 4 INTB Ball C26 Target Inter...

Page 198: ...lock generator continues working when internal SUSP_3V is active 3 SUSP_3V Shut Down PLL6 Allow internal SUSP_3V to shut down PLL6 0 Clock generator is stopped when internal SUSP_3V is active 1 Clock...

Page 199: ...es 00011 4 Bytes All other combinations are reserved 00111 8 Bytes Index 73h Reserved Reset Value 00h Index 74h 75h IOCS0 Base Address Register R W Reset Value 0000h 15 0 I O Chip Select 0 Base Addres...

Page 200: ...Management Enable Register 1 R W Reset Value 00h 7 6 Reserved Must be set to 0 5 Codec SDATA_IN SMI When set to 1 this bit allows an SMI to be generated in response to an AC97 codec producing a posit...

Page 201: ...s 0 Disable 1 Enable If an access occurs in the programmed address range the timer is reloaded with the programmed count UDEF3 address programming is at F0 Index C8h base address register and CEh cont...

Page 202: ...s range is excluded COM2 I O Port 2F8h 2FFh if F0 Index 93h 1 0 11 this range is excluded COM3 I O Port 3E8h 3EFh COM4 I O Port 2E8h 2EFh Top level SMI status is reported at F1BAR0 I O Offset 00h 02h...

Page 203: ...r Defined Device 1 UDEF1 Access Trap If this bit is enabled and an access occurs in the programmed address range an SMI is generated UDEF1 address programming is at F0 Index C0h base address register...

Page 204: ...MI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported at F0 Index 86h F6h 4 6 Secondary Hard Disk Access Trap If this bit is enabled and an access occurs in the addr...

Page 205: ...F1BAR0 I O Offset 00h 02h 9 Second level SMI status is reported at F1BAR0 I O Offset 04h 06h 0 Index 84h Second Level PME SMI Status Mirror Register 1 RO Reset Value 00h The bits in this register are...

Page 206: ...ce 2 Idle Timer Count Register F0 Index A2h 0 No 1 Yes To enable SMI generation set F0 Index 81h 5 to 1 4 User Defined Device Idle Timer 1 Timeout Indicates whether or not an SMI was caused by expirat...

Page 207: ...ex 83h 6 to 1 4 Secondary Hard Disk Idle Timer SMI Status Indicates whether or not an SMI was caused by expiration of Secondary Hard Disk Idle Timer Count register F0 Index ACh 0 No 1 Yes To enable SM...

Page 208: ...To enable SMI generation set F1BAR1 I O Offset 0Ch 0 to 0 2 Codec SDATA_IN SMI Status Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on SDATA_IN 0 No 1 Yes To enabl...

Page 209: ...e I O address range listed below reloads General Purpose Timer 1 Keyboard Controller I O Ports 060h 064h COM1 I O Port 3F8h 3FFh if F0 Index 93h 1 0 10 this range is included COM2 I O Port 2F8h 2FFh i...

Page 210: ...Shift GP Timer 1 is treated as an 8 bit or 16 bit timer 0 8 bit The count value is that loaded into GP Timer 1 Count Register F0 Index 88h 1 16 bit The value loaded into GP Timer 1 Count Register is s...

Page 211: ...d 177h 3 2 Reserved Must be set to 0 1 Mouse on Serial Enable Mouse is present on a Serial Port 0 No 1 Yes If a mouse is attached to a serial port i e this bit is set to 1 that port is removed from th...

Page 212: ...n use so that it can be powered down The 16 bit value programmed here represents the period of hard disk inactivity after which the sys tem is alerted via an SMI The timer is automatically reloaded wi...

Page 213: ...F0 Index 81h 5 1 Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported at F0 Index 85h F5h 5 Index A4h A5h User Defined Device 3 Idle Timer Count Registe...

Page 214: ...ystem clocks Upon a Resume event the internal SUSP_3V signal is de asserted After a slight delay the Core Logic module de asserts the SUSP signal Once the clocks are stable the GX1 module de asserts S...

Page 215: ...ach shadow register in the sequence contains the last data written to that location The read sequence for this register is 1 PIC1 ICW1 2 PIC1 ICW2 3 PIC1 ICW3 4 PIC1 ICW4 Bits 7 5 of ICW4 are always 0...

Page 216: ...k chip and GX1 module PLL to stabilize before de asserting the internal SUSP signal Index BDh BFh Reserved Reset Value 00h Index C0h C3h User Defined Device 1 Base Address Register R W Reset Value 000...

Page 217: ...s 4 0 Mask for address bits A 4 0 If bit 7 1 Memory Bits 6 0 Mask for address memory bits A 15 9 512 bytes min and 64 KB max A 8 0 are ignored Note A 1 in a mask bit means that the address bit is igno...

Page 218: ...BAR1 I O Offset 15h 5 to 1 to allow SMI generation 0 GPWIO0 SMI Status Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin 0 No 1 Yes To enable SMI generation 1 Ensure that GP...

Page 219: ...mer Count Register F0 Index 98h 0 No 1 Yes To enable SMI generation set F0 Index 81h 0 1 Index F6h Second Level PME SMI Status Register 3 RC Reset Value 00h The bits in this register contain second le...

Page 220: ...which has a third level of status reporting at F0BAR0 I O 0Ch 1Ch A read only Mirror version of this register exists at F0 Index 87h If the value of the register must be read without clearing the SMI...

Page 221: ...tes whether or not an SMI was caused by an RTC interrupt 0 No 1 Yes This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1 I O Offset 0Ch 0 0 0 ACPI Timer SMI Status...

Page 222: ...ffset 08h 0Bh GPIEN0 GPIO Interrupt Enable 0 Register R W Reset Value 00000000h 31 16 Reserved Must be set to 0 15 0 GPIO Power Management Event PME Enable Bits 15 0 correspond to GPIO15 GPIO0 signals...

Page 223: ...sponding GPIO signal 0 Disable PME generation 1 Enable PME generation Notes 1 All of the enabled GPIO PMEs are always reported at F1BAR1 I O Offset 10h 3 2 Any enabled GPIO PME can be selected to gene...

Page 224: ...ll W4 111001 GPIO57 101010 GPIO42 111010 GPIO58 101011 GPIO43 111011 GPIO59 101100 GPIO44 111100 GPIO60 101101 GPIO45 111101 GPIO61 101110 GPIO46 111110 GPIO62 101111 GPIO47 111111 GPIO63 Note Note GP...

Page 225: ...pull up capability of the selected GPIO signal It supports open drain output signals with internal pull ups and TTL input signals 0 Disable 1 Enable Default Bits 1 0 of this register must 01 for this...

Page 226: ...ignal 0 PCI INTD ball AA2 1 LPC SERIRQ ball J31 19 INTC Source Selects the interface source of the INTC signal 0 PCI INTC ball C9 1 LPC SERIRQ ball J31 18 INTB Source Selects the interface source of t...

Page 227: ...cts the interface source of the IRQ0 signal 0 ISA IRQ0 Internal signal Connected to OUT0 System Timer of the internal 8254 PIT 1 LPC SERIRQ ball J31 Offset 04h 07h SERIRQ_LVL Serial IRQ Level Control...

Page 228: ...rface source for IRQ9 F0BAR1 I O Offset 00h 9 1 this bit allows signal polarity selection 0 Active high 1 Active low 8 IRQ8 Polarity If LPC is selected as the interface source for IRQ8 F0BAR1 I O Offs...

Page 229: ...24 frames 1011 28 frames 1111 32 frames 1 0 Start Frame Pulse Width 00 4 Clocks 01 6 Clocks 10 8 Clocks 11 Reserved Offset 0Ch 0Fh DRQ_SRC DRQ Source Register R W Reset Value 00000000h Note DRQx are i...

Page 230: ...d to LPC when using the internal SuperI O module and if IO_SIOCFG_IN F5BAR0 I O Offset 00h 26 25 10 12 LPC Ad Lib Addressing Ad Lib addresses I O Ports 388h 389h See bit 16 for decode 11 LPC ACPI Addr...

Page 231: ...fset 10h 6 13 12 LPC Microsoft Sound System MSS Address Select Selects I O Port 00 530h 537h 10 E80h E87h 01 604h 60Bh 11 F40h F47h Selected address range is enabled via F0BAR1 I O Offset 10h 5 11 10...

Page 232: ...I O Offset 02h 3 Second level status is reported at bit 6 of this register 8 SMI Configuration for LPC Error Enable Allows LPC errors to generate an SMI 0 Disable 1 Enable Top Level SMI status is rep...

Page 233: ...write operation on LPC 0 No 1 Yes Write 1 to clear 1 LPC Error DMA Status Indicates whether or not an error was generated during a DMA operation on LPC 0 No 1 Yes Write 1 to clear 0 LPC Error Memory...

Page 234: ...r RO Reset Value 068000h Index 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI BI...

Page 235: ...mand Indicates whether or not an SMI was caused by a Warm Reset command 0 No 1 Yes 12 SMI Source is NMI Indicates whether or not an SMI was caused by NMI activity 0 No 1 Yes 11 SMI Source is IRQ2 of S...

Page 236: ...t for GP timers UDEFx and PCI ISA function traps that are reported in bit 9 0 No 1 Yes The next level second level of SMI status is at F0 Index 84h F4h 87h F7h Offset 02h 03h Top Level PME SMI Status...

Page 237: ...are 0 No 1 Yes 7 SMI on an A20M Toggle Read to Clear Indicates whether or not an SMI was caused by an access to either Port 92h or the keyboard command which initiates an A20M SMI 0 No 1 Yes This meth...

Page 238: ...cess to ISA Legacy I O register space set F0 Index 41h 0 1 Trapped access to F1 register space set F0 Index 41h 1 1 Trapped access to F2 register space set F0 Index 41h 2 1 Trapped access to F3 regist...

Page 239: ...2 1 Trapped access to F3 register space set F0 Index 41h 3 1 Trapped access to F4 register space set F0 Index 41h 4 1 Trapped access to F5 register space set F0 Index 41h 5 1 4 SMI Source is Trapped...

Page 240: ...gister does not clear the SMI For more information see F1BAR0 I O Offset 22h 15 6 Reserved Always reads 0 5 ACPI BIOS SMI Status Indicates whether or not an SMI was caused by ACPI software raising an...

Page 241: ...Offset 0Ch 13 0 No 1 Yes To enable SMI generation set F1BAR1 I O Offset 18h 9 to 1 default 1 THT_EN SMI Status Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit F1BAR1...

Page 242: ...1 Yes To enable SMI generation set bit 1 to 1 16 EXT_SMI0 SMI Status Read to Clear Indicates whether or not an SMI was caused by an assertion of EXT_SMI0 0 No 1 Yes To enable SMI generation set bit 0...

Page 243: ...SMI Enable When this bit is asserted allow EXT_SMI5 to generate an SMI on negative edge events 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 00h 02h 10 Second level SMI status is repor...

Page 244: ...tatus is reported at bits 16 RC and 8 RO Offset 28h 4Fh Not Used Reset Value 00h Offset 50h FFh The I O mapped registers located here F1BAR0 I O Offset 50h FFh can also be accessed at F0 Index 50h FFh...

Page 245: ...r an SMI any SMI to be generated and serviced before transfer into C3 power state A read of this register causes an SMI if enabled F1BAR1 I O Offset 18h 11 1 default Top level SMI status is reported a...

Page 246: ...generation is always enabled Write 1 to clear 10 RTC_STS Real Time Clock Status Indicates if a Power Management Event PME was caused by the RTC generating an alarm RTC IRQ signal is asserted 0 No 1 Y...

Page 247: ...set F1BAR1 I O Offset 0Ch 0 1 The SCIs enabled via this register are globally enabled by setting F1BAR1 I O Offset 08h There is no second level of SCI status report ing for these bits 15 11 Reserved M...

Page 248: ...able 1 Enable This is a write only bit and reads of this bit always return a 0 To generate an SMI ACPI software writes the GBL_RLS bit which in turn sets the BIOS_STS bit F1BAR1 I O Offset 0Eh 0 and r...

Page 249: ...dicates if PME was caused by activity on GPWIO2 0 No 1 Yes Write 1 to clear For the PME to generate an SCI 1 Ensure that GPWIO2 is enabled as an input F1BAR1 I O Offset 15h 2 0 2 Set F1BAR1 I O Offset...

Page 250: ...SCI set F1BAR1 I O Offset 12h 4 1 and F1BAR1 I O Offset 0Ch 0 1 See Note 2 in the general description of this register above 3 GPIO_STS Indicates if PME was caused by activity on any of the GPIOs GPIO...

Page 251: ...his bit can be overridden via F1BAR1 I O Offset 15h 5 to force an SMI 8 GPWIO0_EN Allow GPWIO0 to generate an SCI 0 Disable 1 Enable See F1BAR1 I O Offset 07h 3 for debounce information The setting of...

Page 252: ...status is reported in F1BAR0 I O Offset 00h 02h 0 5 GPWIO_SMIEN1 Allow GPWIO1 to generate an SMI 0 Disable Default 1 Enable See F1BAR1 I O Offset 07h 3 for debounce information Bit 1 of this register...

Page 253: ...UTING Register R W Reset Value 00000F00h 31 17 Reserved 16 PCTL_DELAYEN Allow staggered delays on the activation and deactivation of the power control pins PWRCNT1 PWRCNT2 and ONCTL by 2 ms each 0 Dis...

Page 254: ...et 1Ch 1Fh ACPI Timer Register RO Reset Value xxxxxxxxh Note This register can also be read at F1BAR0 I O Offset 1Ch 31 24 Reserved 23 0 TMR_VAL Read Only This bit field contains the running count of...

Page 255: ...07h PCI Status Register RO Reset Value 0280h Index 08h Device Revision ID Register RO Reset Value 01h Index 09h 0Bh PCI Class Code Register RO Reset Value 010180h Index 0Ch PCI Cache Line Size Regist...

Page 256: ...t1 Address Setup Time value 1 cycle If Index 44h 31 1 Format 1 Bits 31 0 allow independent timing control for both command and data Format 1 settings for a Fast PCI clock frequency of 33 3 MHz PIO Mo...

Page 257: ...MHz UltraDMA Mode 0 00921250h UltraDMA Mode 1 00911140h UltraDMA Mode 2 00911030h Settings for a Fast PCI clock frequency of 66 7 MHz UltraDMA Mode 0 009436A1h UltraDMA Mode 1 00933481h UltraDMA Mode...

Page 258: ...selected in F2 Index 44h 31 bit 31 of this register is defined as reserved Index 58h 5Bh Channel 1 Drive 1 PIO Register R W Reset Value 00009172h Channel 1 Drive 1 Programmed I O Control Register See...

Page 259: ...ansferred from the drive is dis carded This bit should be reset after completion of data transfer Offset 01h Not Used Offset 02h IDE Bus Master 0 Status Register Primary R W Reset Value 00h 7 Simplex...

Page 260: ...W Reset Value 00h 7 Reserved Read Only 6 Drive 1 DMA Capable Allow Drive 1 to perform DMA transfers 0 Disable 1 Enable 5 Drive 0 DMA Capable Allow Drive 0 to perform DMA transfers 0 Disable 1 Enable 4...

Page 261: ...ble 1 Enable This bit must be enabled to access memory offsets through F3BAR0 See F3 Index 10h 0 Reserved Read Only Index 06h 07h PCI Status Register RO Reset Value 0280h Index 08h Device Revision ID...

Page 262: ...7h Codec GPIO Control Register R W Reset Value 00000000h 31 20 Reserved Must be set to 0 19 0 Codec GPIO Pin Data This field indicates the GPIO pin data that is sent to the codec in slot 12 on the SDA...

Page 263: ...el Audio SMI Status Register RC Reset Value 0000h The bits in this register contain second level SMI status reporting Top level is reported at F1BAR0 I O Offset 00h 02h 1 Reading this register clears...

Page 264: ...0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 12h 13h Second Level Audio SMI Status Mirror Register RO Reset Value 0000h Note The bits in this reg...

Page 265: ...if an SMI was caused by an I O trap 0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 14h 17h I O Trap SMI and Fast Write Status Register RO RC Reset...

Page 266: ...BAR0 I O Offset 00h 02h 1 SMI generation enabling is at F3BAR0 Memory Offset 18h 2 9 0 X Bus Address Read Only This bit field contains the captured ten bits of X Bus address Offset 18h 19h I O Trap SM...

Page 267: ...dress ranges selected by bits 1 0 an SMI is generated 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 1 Second level SMI status is reported at F3BAR0 Memory Offset 10h...

Page 268: ...rnal 1 Internal 0 Reserved Must be set to 0 Offset 1Ch 1Fh Internal IRQ Control Register R W Reset Value 00000000h Note Bits 31 16 of this register are Write Only Reads to these bits always return a v...

Page 269: ...al IRQ14 0 Disable 1 Enable 13 Reserved Set to 0 12 Assert Masked Internal IRQ12 0 Disable 1 Enable 11 Assert masked internal IRQ11 0 Disable 1 Enable 10 Assert Masked Internal IRQ10 0 Disable 1 Enabl...

Page 270: ...aster Error Indicates if hardware encountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it cau...

Page 271: ...ountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until thi...

Page 272: ...ware has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until this register is read to clear the e...

Page 273: ...OP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until this register is read to clear...

Page 274: ...if hardware encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause un...

Page 275: ...encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until this re...

Page 276: ...defined as allowing access to I O mapped registers this bit must be set to 1 BAR configuration is programmed through the corre sponding mask register see F5 Index 40h 44h 48h 4Ch 50h and 54h Index 06h...

Page 277: ...ddress Mask Determines the size of the BAR Every bit that is a 1 is programmable in the BAR Every bit that is a 0 is fixed 0 in the BAR Since the address mask goes down to bit 4 the smallest memory re...

Page 278: ...ister above for bit descriptions Note Whenever a value is written to this mask register F5BAR5 must also be written even if the value for F5BAR5 has not changed Index 58h F5BARx Initialized Register R...

Page 279: ...rface Function 5 32581C Index 64h 67h Scratchpad Usually used for Configuration Block Address R W Reset Value 00000000h BIOS writes a value of the Configuration Block Address Index 68h FFh Reserved Ta...

Page 280: ...ontrol the base address 00 Integrated SIO disable 01 Integrated SIO configuration access disable 10 Integrated SIO base address 02Eh 02Fh enable 11 Integrated SIO base address 015Ch 015Dh enable 24 IO...

Page 281: ...L AD26 for Chipset Register Space F0 F5 AD27 for USB Register Space PCIUSB Offset 08h 0Bh I O Control Register 3 R W Reset Value 00009000h 31 16 Reserved Write as read 15 13 IO_USB_XCVR_VADJ USB Volta...

Page 282: ...ice Identification Register RO Reset Value A0F8h Index 04h 05h Command Register R W Reset Value 00h 15 10 Reserved Must be set to 0 9 Fast Back to Back Enable Read Only USB only acts as a master to a...

Page 283: ...x 08h Device Revision ID Register RO Reset Value 08h Index 09h 0Bh PCI Class Code Register RO Reset Value 0C0310h This register identifies the generic function of the USB the specific register level p...

Page 284: ...writ ing 2 3 or 4 respectively Index 3Eh Min Grant Register RO Reset Value 00h This register specifies how long a burst is needed by the USB assuming a clock rate of 33 MHz The value in this register...

Page 285: ...so Interrupt EDs may be serviced While processing the Periodic List the HC will check this bit when it finds an isochronous ED 2 PeriodicListEnable When set this bit enables processing of the Periodi...

Page 286: ...hangeEnable 0 Ignore 1 Enable interrupt generation due to Ownership Change 29 7 Reserved Read Write 0s 6 RootHubStatusChangeEnable 0 Ignore 1 Enable interrupt generation due to Root Hub Status Change...

Page 287: ...HcHCCA Register R W Reset Value 00000000h 31 8 HCCA Pointer to HCCA base address 7 0 Reserved Read Write 0s Offset 1Ch 1Fh HcPeriodCurrentED Register R W Reset Value 00000000h 31 4 PeriodCurrentED Poi...

Page 288: ...e where in a frame the Periodic List pro cessing must begin Offset 44h 47h HcLSThreshold Register R W Reset Value 00000628h 31 12 Reserved Read Write 0s 11 0 LSThreshold This field contains a value us...

Page 289: ...RST It is written during system initialization to configure the Root Hub These bit should not be written during normal operation Offset 50h 53h HcRhStatus Register R W Reset Value 00000000h 31 ClearRe...

Page 290: ...viceAttached This bit defines the speed and bud idle of the attached device It is only valid when CurrentConnectStatus is set 0 Full Speed device 1 Low Speed device Write ClearPortPower Writing a 1 cl...

Page 291: ...s that the port has been disabled due to a hardware event cleared PortEna bleStatus 0 Port has not been disabled 1 PortEnableStatus has been cleared 16 ConnectStatusChange This bit indicates a connect...

Page 292: ...21 Reserved Read Write 0s 20 PortResetStatusChange This bit indicates that the port reset signal has completed 0 Port reset is not complete 1 Port reset is complete 19 PortOverCurrentIndicatorChange...

Page 293: ...emovable this bit is always 1 Write ClearPortEnable Writing 1 a clears PortEnableStatus Writing a 0 has no effect Note This register is reset by the UsbReset state Offset 60h 9Fh Reserved Reset Value...

Page 294: ...h 10Fh HceStatus Register R W Reset Value 00000000h 31 8 Reserved Read Write 0s 7 Parity Indicates parity error on keyboard mouse data 6 Timeout Used to indicate a time out 5 AuxOutputFull IRQ12 is as...

Page 295: ...DMA Channel Control Registers Bit Description I O Port 000h DMA Channel 0 Address Register R W Written as two successive bytes byte 0 1 I O Port 001h DMA Channel 0 Transfer Count Register R W Written...

Page 296: ...write 1 Extended write 4 Priority Mode 0 Fixed 1 Rotating 3 Timing Mode 0 Normal 1 Compressed 2 Channels 3 0 0 Disable 1 Enable 1 0 Reserved Must be set to 0 I O Port 009h Software DMA Request Registe...

Page 297: ...A Master Clear Command Channels 3 0 W I O Port 00Eh DMA Clear Mask Register Command Channels 3 0 W I O Port 00Fh DMA Write Mask Register Command Channels 3 0 W I O Port 0C0h DMA Channel 4 Address Regi...

Page 298: ...Terminal Count Indicates if TC was reached 0 No 1 Yes 2 Channel 6 Terminal Count Indicates if TC was reached 0 No 1 Yes 1 Channel 5 Terminal Count Indicates if TC was reached 0 No 1 Yes 0 Undefined Wr...

Page 299: ...hannels 7 4 WO Note Channels 5 6 and 7 are not supported 7 6 Transfer Mode 00 Demand 01 Single 10 Block 11 Cascade 5 Address Direction 0 Increment 1 Decrement 4 Auto initialize 0 Disabled 1 Enable 3 2...

Page 300: ...age Register R W Not supported I O Port 08Bh DMA Channel 5 Low Page Register R W Not supported I O Port 08Fh ISA Refresh Low Page Register R W Refresh address I O Port 481h DMA Channel 2 High Page Reg...

Page 301: ...Write Mode 00 Counter latch command 01 R W LSB only 10 R W MSB only 11 R W LSB followed by MSB 3 1 Current Counter Mode 0 5 0 BCD Mode 0 Binary 1 BCD Binary Coded Decimal I O Port 041h Write PIT Timer...

Page 302: ...I O Port 043h R W PIT Mode Control Word Register Notes 1 If bits 7 6 11 Register functions as Read Status Command and Bit 5 Latch Count Bit 4 Latch Status Bit 3 Select Counter 2 Bit 2 Select Counter...

Page 303: ...or base vector for interrupt controller 2 0 Reserved Must be set to 0 I O Port 021h 0A1h Master Slave PIC ICW3 after ICW2 is written WO Master PIC ICW3 7 0 Cascade IRQ Must be 04h Slave PIC ICW3 7 0 S...

Page 304: ...ve PIC OCW3 WO 7 Reserved Must be set to 0 6 5 Special Mask Mode 00 No operation 01 No operation 10 Reset Special Mask Mode 11 Set Special Mask Mode 4 Reserved Must be set to 0 3 Reserved Must be set...

Page 305: ...ding 0 Yes 1 No Interrupt Service Register 7 IRQ7 IRQ15 In Service 0 No 1 Yes 6 IRQ6 IRQ14 In Service 0 No 1 Yes 5 IRQ5 IRQ13 In Service 0 No 1 Yes 4 IRQ4 IRQ12 In Service 0 No 1 Yes 3 IRQ3 IRQ11 In S...

Page 306: ...O device to report an error Note that NMI is under SMI control 1 Ignores the IOCHK input signal and does not generate NMI 2 PERR SERR Enable Generate an NMI if PERR SERR is driven active to report an...

Page 307: ...49 Miscellaneous Registers Bit Description I O Port 0F0h 0F1h Coprocessor Error Register W Reset Value F0h A write to either port when the internal FERR signal is asserted causes the Core Logic Module...

Page 308: ...sitive shared 7 IRQ15 Edge or Level Sensitive Select Selects PIC IRQ15 sensitivity configuration 0 Edge 1 Level 6 IRQ14 Edge or Level Sensitive Select Selects PIC IRQ14 sensitivity configuration 0 Edg...

Page 309: ...ation using three line buffers YUV to RGB color space conversion Horizontal filtering and downscaling Supports 4 2 2 4 2 0 YUV formats and RGB 5 6 5 format Graphics Video Overlay and Blending Overlay...

Page 310: ...chronous video interface Horizontal vertical scalers Filters Mixer Blender Overlay with color chroma key Gamma correction Color space converters Alpha blender TFT interface Dot Clock PLL The following...

Page 311: ...In this mode the data never leaves the Video Processor module Direct Video mode can only be used under very specific condi tions which will be explained later If the VIP data is less than full frame...

Page 312: ...l Lines 2 3 Scan Lines 2 3 VSYNC Start VBI_Total_Count_Odd VBI_Line_Offset_Odd Not normally User Data Nominal VBI Lines Not normally User Data Not normally User Data VSYNC End Vertical Retrace Logical...

Page 313: ...z For the Direct Video FIFO the Video data is clocked out using the GX1 s Video port clock 75 116 or 133 MHz GX1 core clock divided by 2 or 4 7 2 1 1 Direct Video Mode As stated previously Direct Vide...

Page 314: ...r a given amount of time therefore reducing the memory bandwidth requirement The disad vantage is that there are some observable visual effects due to the reduction in resolution Figure 7 5 on page 31...

Page 315: ...a is stored in the GX1 module s frame buffer F4BAR2 Memory Offset 20h Video Data Odd Base Address F4BAR2 Memory Offset 24h Video Data Even Base Address F4BAR2 Memory Offset 28h Video Data Pitch The Vi...

Page 316: ...ne or more of the VBI lines or have an application decode the Closed Captioning information put in the graphics frame buffer The registers F4BAR2 Memory Offset 40h 44h and 48h tell the bus master the...

Page 317: ...5 For this format each pixel is described as a 16 bit value Bits 15 11 Red Bits 10 5 Green Bits 4 0 Blue YUV 4 2 0 This format is not supported by the GX1 mod ule The Horizontal Downscaler in the Vide...

Page 318: ...video window by a factor of up to 8 1 in 1 pixel increments The downscaler factor m is programmed in the Video Downscaler Control register F4BAR0 Memory Offset 3Ch 4 1 If bit 0 of this register is se...

Page 319: ...scalers After the video data has been buffered the upscaling algo rithm can be applied The Video Processor employs a Digi tal Differential Analyzer style DDA algorithm for both horizontal and vertical...

Page 320: ...the color space of the input graphics data which is RGB The video data can be in progressive or interlaced format while the graphics data is always in the progressive format The Mixer Blender can mix...

Page 321: ...use F4BAR0 Memory Offset 1Ch and 20h 7 2 3 3 Color Chroma Key A color chroma key mechanism is used to support the Mixer Blender logic There are two keys key1 is for the cur sor and key2 is for graphi...

Page 322: ...the GX1 module s video frame buffer which includes Capture Video mode see Section 7 2 1 2 Capture Video Mode on page 314 then the video data can be scaled both horizontally and verti cally The video d...

Page 323: ...ta Match Normal Color Key Video Data Match Normal Color Key Mixer Output x x x Yes x x Cursor Color x Not in Video Window x No x x Graphics Data Graphics Color Key COLOR_ CHROMA_SEL 0 Not in an Alpha...

Page 324: ...Yes Replace the value with the color register value Yes Start Notes 1 Alpha window should not be placed outside of the video window 2 Graphics inside Video is enabled via bit GFX_INS_VIDEO in the Vid...

Page 325: ...ls TFTD 11 6 for green signals TFTD 17 12 for red signals HSYNC and VSYNC sync signals TFTDCK data clock signal TFTDE data enable signal FP_VDD_ON power control signal Power Sequence Power sequence is...

Page 326: ...oscillator FOUT is calculated from FOUT m 1 n 1 x FREF The integrated PLL can generate any frequency by writing into the m and n bit fields FBAR0 Memory Offset 2Ch m bits 14 8 and n bits 3 0 Addition...

Page 327: ...Register 0 F4BAR0 Sets the base address for the memory mapped Video Configuration Registers within the Video Processor Refer to Table 7 7 on page 332 for programming infor mation regarding the regist...

Page 328: ...Fh 32 R W Alpha Window 1 Control Register 00000000h Page 340 70h 73h 32 R W Alpha Window 2 X Position Register 00000000h Page 341 74h 77h 32 R W Alpha Window 2 Y Position Register 00000000h Page 341 7...

Page 329: ...Reserved 00000000h Page 347 10h 13h 32 RO Video Current Line Register xxxxxxxxh Page 347 14h 17h 32 R W Video Line Target Register 00000000h Page 347 18h 1Fh Reserved 00000000h Page 347 20h 23h 32 R...

Page 330: ...ndex 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI BIST Register RO Reset Value...

Page 331: ...upt Pin Register R W Reset Value 03h This register selects which interrupt pin the device uses VIP uses INTC after reset INTA INTB or INTD can be selected by writing 1 2 or 4 respectively Index 3Eh FF...

Page 332: ...e left edge of the active display It represents the DWORD address of the source pixel which is to be displayed first For an unclipped window this value should be 0 For 4 2 0 format set bits 17 16 to 0...

Page 333: ...the graphics is used for color keying or the video data stream is used for chroma keying 0 Graphics data is compared to the color key 1 Video data is compared to the chroma key 19 17 PWR_SEQ_DLY Powe...

Page 334: ...Position Represents the vertical end position of the video window not inclusive This value is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 2 15 11 Res...

Page 335: ...can be used to allow a range of values to serve as the color key 31 24 Reserved 23 0 VID_CLR_MASK Video Color Mask This mask is a 24 bit value Zeros in the mask cause the corresponding bits in the gra...

Page 336: ...usly calculated values 0 Values previously calculated from the CLK_SEL bits bits 19 16 1 Values according to the m bits 14 8 n bits 3 0 and CLK_DIV_SEL bits 22 21 fields 19 16 CLK_SEL Clock Select Sel...

Page 337: ...xxx100h Signature values stored in this register can be read by the host This register is used for test purposes 31 8 SIG_VALUE Signature Value Read Only A 24 bit signature value is stored in this bit...

Page 338: ...o format 0 YUV format 1 RGB format Note Mixing and blending configurations are created using bits 13 11 9 of this register See Table 7 1 Valid Mixing Blending Configurations on page 321 If this bit is...

Page 339: ...ed 28 24 COLOR_REG_OFFSET Cursor Color Register Offset This field indicates a bit in the incoming graphics stream It is used to indicate which of the two possible cursor color registers should be used...

Page 340: ...w 1 Vertical Start Determines the vertical start position of Alpha Window 1 This value is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 1 Offset 68h 6B...

Page 341: ...tical Start Determines the vertical start position of Alpha Window 2 This value is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 1 Offset 78h 7Bh Alpha...

Page 342: ...Vertical End Determines the vertical start position of Alpha Window 3 This value is calculated according to the following formula Value Desired screen position V_TOTAL V_SYNC_END 1 Offset 88h 8Bh Alp...

Page 343: ...in the current frame 31 24 Reserved 23 16 ALPHA3_VAL Value for Alpha Window 3 15 8 ALPHA2_VAL Value for Alpha Window 2 7 0 ALPHA1_VAL Value for Alpha Window 1 Offset 98h 3FFh Reserved Offset 400h 403h...

Page 344: ...2 GX1_VSYNC_EDGE_SEL GX1 VSYNC Edge Select Selects which edge of the VSYNC signal should be synchronized with the GX1 module 0 Rising edge 1 Falling edge 1 CT_GENLOCK_EN Enable Continuous GenLock Fun...

Page 345: ...1 enabled 18 VBI Configuration Override When this bit is enabled bits 21 19 override the setup specified in bits 17 and 16 0 Disable 1 Enable 17 VBI Data Task Specifies the CCIR656 video stream task u...

Page 346: ...at beginning of next field Offset 08h 0Bh Video Interface Status Register R W Reset Value xxxxxxxxh 31 25 Reserved Read Only 24 Current Field Read Only 0 Even field is being processed 1 Odd field is...

Page 347: ...luding this one are written to the appropriate base registers and the Base Register Not Updated bit is cleared 31 0 Video Odd Base Address Base address where odd video data are stored in graphics memo...

Page 348: ...cs memory where VBI data for even fields is stored Changes to this register take effect at the beginning of the next field The value in this register is 16 byte aligned Note This register is double bu...

Page 349: ...ruction Support The TAP supports the following IEEE optional instructions IDCODE Presents the contents of the Device Identification register in serial format CLAMP Ensures that the Bypass register is...

Page 350: ...350 AMD Geode SC3200 Processor Data Book Debugging and Monitoring 32581C...

Page 351: ...the following table may cause permanent damage to the SC3200 reduce device reliability and result in premature failure even when there is no immediately apparent sign of failure Prolonged expo sure t...

Page 352: ...re connected on the boundary between voltage domains Table 9 3 Operating Conditions Symbol Note 1 Parameter Min Typ Max Unit Comments TC Operating case temperature 0 85 o C AVCCUSB Analog power supply...

Page 353: ...pplied to the device s core and I O supply pins This is equivalent to the ACPI spec ification s S1 state 9 1 5 2 Definition and Measurement Techniques of SC3200 Current Parameters These parameters des...

Page 354: ...equency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz using a display image of vertical stripes 4 pixel wide alternating between black and white with power management disa...

Page 355: ...Nominal CPU state Sleep 20 30 mA ICC for VCORE Note 2 ISBOFF SB Current VSB 3 3V Nominal CPU state Off 1 mA ISBLOFF SBL Current VSBL 1 8V Nominal CPU state Off 1 mA ICC for VSBL Note 3 IBAT BAT Curren...

Page 356: ...T_PRSNT P29 PD 100K LPC_ROM D6 PD 100K FPCI_MON A4 PD 100K DID 1 0 C6 C5 PD 100K ACCESS bus Note 2 AB1C N31 PU 22 5K AB1D N30 PU 22 5K AB2C N29 PU 22 5K AB2D M29 PU 22 5K Parallel Port AFD DSTRB D22 P...

Page 357: ...Input PCI compatible Section 9 2 3 INSTRP Input Strap ball min VIH is 0 6VIO with weak pull down Section 9 2 4 INT Input TTL compatible Section 9 2 5 INTS Input TTL compatible with Schmitt Trigger ty...

Page 358: ...1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 5 A VIN VSB 36 A VIN VSS VHIS Input HysteresisNote 1 250 mV Note 1 Not 100 tested Symbol Parameter Min Max Unit Comments VIH Input...

Page 359: ...t Comments VIH Input High Voltage 2 0 VIO 0 3 Note 1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 10 A VIN VIO 10 A VIN VSS Note 1 Not 100 tested Symbol Parameter Min Max Unit Co...

Page 360: ...0 A VIN VIO 10 A VIN VSS VDI Differential Input Sensitivity 0 2 V D D and Figure 9 1 VCM Differential Common Mode Range 0 8 2 5 V Includes VDI Range VSE Single Ended Receiver Threshold 0 8 2 0 V Note...

Page 361: ...Unit Comments VOL Output Low Voltage 0 1VIO V lOL 1500 A Symbol Parameter Min Max Unit Comments VOH Output High Voltage 2 4 V lOH p mA VOL Output Low Voltage 0 4 V lOL n mA Symbol Parameter Min Max U...

Page 362: ...conform to these default levels All AC tests are at VIO 3 14V to 3 46V 3 3V nominal TC 0 oC to 85 oC CL 50 pF unless otherwise specified Figure 9 2 Drive level and Measurement Points Table 9 11 Defau...

Page 363: ...ng window during which a synchronous input signal must be stable to ensure correct operation Figure 9 3 Memory Controller Drive Level and Measurement Points SDCLK_OUT VOH VREF VREF VREF C Valid Output...

Page 364: ...VOHD 2 ns t9 SDCLK_IN fall rise time between VILD VIHD 2 ns t10 SDCLK 3 0 SDCLK_OUT high time 233 MHz 4 0 ns 266 MHz 3 0 t11 SDCLK 3 0 SDCLK_OUT low time 233 MHz 4 0 ns 266 MHz 2 5 Note 1 Control out...

Page 365: ...4 Memory Controller Output Valid Timing Diagram Figure 9 5 Read Data In Setup and Hold Timing Diagram SDCLK 3 0 Control Output MA 12 0 BA 1 0 MD 63 0 t1 t2 t3 t6 t7 t7 VREF VOHD VOLD VREF t10 t11 SDC...

Page 366: ...rs Symbol Parameter Min Max Unit Comments tVP_C VPCKIN cycle time 18 ns tVP_S Video Port input setup time before VPCKIN rising edge 6 ns tVP_H Video Port input hold time after VPCKIN rising edge 0 ns...

Page 367: ...ter TFTDCK rising edge multiplexed on IDE 0 8 ns tOV TFTD 17 0 TFTDE valid time after TFTDCK rising edge multiplexed on Parallel Port 0 4 ns tCLK_RF TFTDCK rise fall time between 0 8V and 2 0V 3 ns No...

Page 368: ...B2C falling edge tSCLhighi AB1C AB2C high time 16 tCLK After AB1C AB2C rising edge tSDAfi AB1D AB2D fall time 300 ns tSDAri AB1D AB2D rise time 1 s tSDAhi AB1D AB2D hold time 0 After AB1C AB2C falling...

Page 369: ...AB1D AB2D valid time 7 tCLK tRD After AB1C AB2C falling edge Note 1 K is determined by bits 7 1 of the ACBCTL2 register LDN 05h 06h Offset 05h Note 2 tSCLhigho value depends on the signal capacitance...

Page 370: ...1C Figure 9 10 ACB Start Condition Timing Diagram Figure 9 11 ACB Data Bit Timing Diagram tCSTRsi tDHCsi Start Condition tCSTRhi AB1D AB1C tCSTRho tCSTRso tDHCso AB2D AB2C tSCLhigho tSCLlowo tSDAho tS...

Page 371: ...VOUT 0 1VIO Equation B Figure 9 13 0 18VIO VOUT 0 Test point Note 2 38VIO mA VOUT 0 18VIO ICL Low clamp current 25 VIN 1 0 015 mA 3 VIN 1 ICH High clamp current 25 VIN VIO 1 0 015 mA VIO 4 VIN VIO 1...

Page 372: ...n Test Point VIO 0 9 VIO DC Drive Point AC Drive Point 0 3 VIO 0 6 VIO 0 1 AC Drive Point DC Drive Point Test Point VIO Equation A for VIO VOUT 0 7VIO IOL 256 VIO VOUT VIO VOUT for 0V VOUT 0 18VIO Vol...

Page 373: ...Rate 50 mV ns Note 4 Note 1 Clock frequency is between nominal DC and 33 MHz Device operational parameters at frequencies under 16 MHz are not 100 tested The clock can only be stopped in a low state N...

Page 374: ...1 ms Note 3 Note 5 tRST CLK PCIRST active time after PCICLK stable 100 s Note 3 Note 5 tRST OFF PCIRST active to output float delay 40 ns Note 3 Note 5 Note 6 Note 1 See the timing measurement conditi...

Page 375: ...VTL 0 2 VIO V Note 1 VTEST 0 4 VIO V VSTEP rising edge 0 285 VIO V VSTEP falling edge 0 615 VIO V VMAX 0 4 VIO V Note 2 Input signal edge rate 1 V ns Note 1 The input test is performed with 0 1 VIO o...

Page 376: ...ditions Figure 9 18 PCI Reset Timing VTEST VTEST Input Valid tSU tH VTEST VMAX VTH VTL PCICLK Input VTH VTL 100 ms typ tRST tRST CLK tRST OFF TRI_STATE PCI Signals PCIRST PCICLK POWER POR tFAIL VIO No...

Page 377: ...to RE 8 M I O 160 9 19 Zero wait state tRCU1 MEMR DOCR RD TRDE inactive pulse width 16 M 103 9 19 tRCU2 MEMR DOCR RD TRDE inactive pulse width 8 M 163 9 19 tRCU3 IOR RD TRDE inactive pulse width 8 16...

Page 378: ...M I O 0 9 19 tHZ Read data floating after MEMR DOCR IOR inactive 8 16 M I O 41 9 19 tAW1 A 23 0 BHE valid before MEMW DOCW active 16 M 34 9 20 tAW2 A 23 0 BHE valid before IOW active 16 I O 100 9 20 t...

Page 379: ...b ISA Read Operation Timing Diagram tRDx tARx Valid Valid Valid Data tRCUx tRA tRVDS tRDH tHZ A 23 0 BHE D 15 0 tRDYAx tRDYH MEMW DOCW ROMCS DOCCS IOW WR IOCS 1 0 Read tIOCSA tIOCSH tWDAR D 15 0 Write...

Page 380: ...re 9 20 Sub ISA Write Operation Timing Diagram tWRx tAWx Valid Valid Valid Data tWCUx tWA tDH A 23 0 BHE TRDE D 15 0 IOCHRDY tRDYAx tRDYH DOCCS ROMCS tIOCSH IOCS 1 0 tDF tDVx tIOCSA IOW WR MEMW DOCW I...

Page 381: ...ameters Symbol Parameter Min Max Unit Comments tVAL Output Valid delay 0 17 ns After PCICLK rising edge tON Float to Active delay 2 ns After PCICLK rising edge tOFF Active to Float delay 28 ns After P...

Page 382: ...23 IDE Reset Timing Diagram Table 9 23 IDE General Timing Parameters Symbol Parameter Min Max Unit Comments tIDE_FALL IDE signals fall time from 0 9VIO to 0 1VIO 5 ns CL 40 pF tIDE_RISE IDE signals r...

Page 383: ...5 5 5 5 ns Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the sum o...

Page 384: ...tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Device keeps IDE_IORDY 0 1 released and no wait is generated 4 Device negates IDE_IORDY 0 1 before tA but cause...

Page 385: ...s Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the sum of the com...

Page 386: ...d is made by the host after tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Devices keep IDE_IORDY 0 1 released and no wait is generated 4 Device negates IDE_I...

Page 387: ...d pulse width min 215 50 25 ns tLR IDE_IOR 0 1 to IDE_DREQ 0 1 delay max 120 40 35 ns tLW IDE_IOW 0 1 to IDE_DREQ0 1 delay max 40 40 35 ns tM IDE_CS 0 1 valid to IDE_IOR 0 1 IDE_IOW 0 1 min 50 30 25 n...

Page 388: ...DE_IOW0 Notes 1 For Multiword DMA transfers the Device may negate IDE_DREQ 0 1 within the tL specified time once IDE_DACK 0 1 is asserted and reassert it again at a later time to resume the DMA operat...

Page 389: ...d 10 10 10 ns tZAH Minimum delay time required for output driv ers to assert or negate from released state 20 20 20 ns tZAD 0 0 0 ns tENV Envelope time from IDE_DACK 0 1 to IDE_IOW 0 1 STOP 0 1 and ID...

Page 390: ...nts are taken at the connector of the sender Figure 9 27 Initiating an UltraDMA Data in Burst Timing Diagram tUI tACK tENV tFS tFS tZAD tACK tZIORDY tAZ tACK tDVS tDVH tENV tZAD IDE_DATA 15 0 IDE_ADDR...

Page 391: ...IDE_DATA 15 0 at device IDE_DATA 15 0 at host IDE_IRDY0 DSTROBE0 at device IDE_IRDY0 DSTROBE0 at host Note IDE_DATA 15 0 and IDE_IRDY 0 1 DSTROBE 0 1 signals are shown at both the host and the device...

Page 392: ...tSR IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Notes 1 The host can assert IDE_IOW 0 1 STOP 0 1 to request termination of the UltraDMA burst...

Page 393: ...0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tZAH tAZ tSS tLI tACK tIORDZ tACK tMLI tLI tLI IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The definiti...

Page 394: ...DE_ADDR 2 0 CR tACK tDVH tDVS tACK tIORDYZ tACK tMLI tLI tRP tMLI tLI tRFS tAZ tZAH IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The defini...

Page 395: ...IDE_CS 0 1 IDE_ADDR 2 0 tUI tACK tENV tLI tUI tZIORDY tACK tDVS tDVH tACK IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device IDE_IOR0 HSTROBE0 host Note The definitions for...

Page 396: ...C IDE_DATA 15 0 at host IDE_DATA 15 0 at device IDE_IOR0 HSTROBE0 at host IDE_IOR0 HSTROBE0 at device Note IDE_DATA 15 0 and IDE_IOR 0 1 HSTROBE 0 1 signals are shown at both the device and the host t...

Page 397: ...S tSR IDE_IOR0 HSTROBE0 host IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device Notes 1 The device can de assert IDE_DREQ 0 1 to request termination of the UltraDMA burst n...

Page 398: ...0 1 IDE_ADDR 2 0 CR tLI tMLI tACK tLI tSS tLI tACK tDVH tDVS tACK tIORDYZ IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The definitions fo...

Page 399: ...0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tRFS tACK tIORDZ tACK tMLI tLI tRP tMLI tLI IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_DREQ0 device IDE_DACK0 host IDE_IOW0 STOP0 host Note The definition...

Page 400: ...OP width 160 175 ns 9 38 Note 4 Note 5 tUSB_DE1 Differential to EOP transition skew 2 5 ns 9 39 Note 4 Note 5 tUSB_RJ11 Receiver data jitter tolerance for con secutive transition 18 5 18 5 ns 9 40 Not...

Page 401: ...stream Note 4 tUSB_RJU22 Receiver data jitter tolerance for paired transactions 45 45 ns 9 40 Function downstream Note 4 Low Speed Receiver EOP Width Note 5 tUSB_RE21 Must reject as EOP 330 ns 9 38 tU...

Page 402: ...10 10 Differential Data Lines CL CL Full Speed 4 to 20 ns at CL 50 pF Low Speed 75 ns at CL 50 pF 300 ns at CL 350 pF tperiod_F Paired Transitions Consecutive Transitions Differential Data Lines Cross...

Page 403: ...rential Data to SE0 Skew N tperiod_F tUSB_DE1 N tperiod_L tUSB_DE2 tUSB_SE1 tUSB_SE2 tUSB_RE11 tUSB_RE12 tUSB_RE21 tUSB_RE22 Source Receiver tperiod_F Paired Transitions Consecutive Transitions Differ...

Page 404: ...tter 2 0 Receiver tSJT SIR leading edge jitter of nominal bit duration 2 5 Transmitter 6 5 Receiver Note 1 tBTN is the nominal bit time in UART Sharp IR SIR and Consumer Remote Control modes It is det...

Page 405: ...toler ance 0 1 tMJT MIR receiver edge jitter of nominal bit duration 2 9 tFPW FIR signal pulse width 120 130 ns Transmitter 90 160 ns Receiver tFDPW FIR signal double pulse width 245 255 ns Transmitte...

Page 406: ...Port Typical Data Exchange Timing Diagram Table 9 31 Standard Parallel Port Timing Parameters Symbol Parameter Min Typ Max Unit Comments tPDH Port data hold 500 ns Note 1 tPDS Port data setup 500 ns...

Page 407: ...AIT low 45 x ns tWW19ia WRITE inactive from WAIT low 45 x ns tWST19a DSTRB or ASTRB active from WAIT low 65 x ns tWEST DSTRB or ASTRB active after WRITE active 10 x x ns tWPDH PD 7 0 hold after WRITE...

Page 408: ...Mode Timing Parameters Symbol Parameter Min Max Unit Comments tECDSF Data setup before STB active 0 ns tECDHF Data hold after BUSY inactive 0 ns tECLHF BUSY active after STB active 75 ns tECHHF STB in...

Page 409: ...ters Symbol Parameter Min Max Unit Comments tECDSR Data setup before ACK active 0 ns tECDHR Data hold after AFD active 0 ns tECLHR AFD inactive after ACK active 75 ns tECHHR ACK inactive after AFD ina...

Page 410: ...eters Symbol Parameter Min Typ Max Unit Comments tRST_LOW AC97_RST active low pulse width 1 0 s tRST2CLK AC97_RST inactive to BIT_CLK startup delay 162 8 ns AC97_RST BIT_CLK tRST_LOW tRST2CLK Table 9...

Page 411: ...pulse width 32 56 40 7 48 84 ns Note 1 FSYNC SYNC frequency 48 0 KHz tSYNC_PD SYNC period 20 8 s tSYNC_H SYNC high pulse width 1 3 s tSYNC_L SYNC low pulse width 19 5 s FAC97_CLK AC97_CLK frequency 2...

Page 412: ...dge of BIT_CLK 15 0 ns tAC97_H Hold from falling edge of BIT_CLK 10 0 ns tAC97_OV SDATA_OUT or SYNC valid after rising edge of BIT_CLK 15 ns tAC97_OH SDATA_OUT or SYNC hold time after falling edge of...

Page 413: ...CLK rise time 2 6 ns tfallCLK BIT_CLK fall time 2 6 ns triseSYNC SYNC rise time 2 6 ns CL 50 pF tfallSYNC SYNC fall time 2 6 ns CL 50 pF triseDIN SDATA_IN rise time 2 6 ns tfallDIN SDATA_IN fall time...

Page 414: ...gure 9 52 AC97 Low Power Mode Timing Diagram Table 9 40 AC97 Low Power Mode Timing Parameters Symbol Parameter Min Typ Max Unit Comments ts2_pdown End of Slot 2 to BIT_CLK SDATA_IN low 1 0 s SYNC BIT_...

Page 415: ...ming Diagram Table 9 41 PWRBTN Timing Parameters Symbol Parameter Min Max Unit Comments tPBTNP PWRBTN pulse width 16 ms Note 1 tPBTNE Delay from PWRBTN events to ONCTL 14 16 ms Note 1 Not 100 tested P...

Page 416: ...r VSBL applied whichever is applied last 0 1 s PWRBTN is an input and must be powered by VSB t3 PWRBTN active pulse width 16 4000 ms If PWRBTN max is exceeded ONCTL will go inactive t4 ONCTL inactive...

Page 417: ...see Section 6 4 1 1 GPIO Sup port Registers on page 222 GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec Asserting POR has no effect on ACPI If POR is asserted and ACPI was active...

Page 418: ...quency 25 MHz t1 TCK period 40 ns t2 TCK high time 10 ns t3 TCK low time 10 ns t4 TCK rise time 4 ns t5 TCK fall time 4 ns t6 TDO valid delay 3 25 ns t7 Non test outputs valid delay 3 25 ns 50 pF load...

Page 419: ...AMD Geode SC3200 Processor Data Book 419 Electrical Specifications 32581C Figure 9 58 JTAG Test Timing Diagram TCK t8 Input Output TDO TDI t11 t13 t9 t7 t6 t12 t10 TMS Signals Signals...

Page 420: ...420 AMD Geode SC3200 Processor Data Book Electrical Specifications 32581C...

Page 421: ...ve thermal management via Sus pend Modulation of the GX1 module is employed A maximum junction temperature is not specified since a maximum case temperature is Therefore the following equation can be...

Page 422: ...ambient in C This method is necessary because ambi ent and case temperatures fluctuate constantly during nor mal operation of the system The system designer must be careful to choose the proper heats...

Page 423: ...a Book 423 Package Specifications 32581C 10 2 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 481 Terminal Ball Grid Array Cavity Up package Figur...

Page 424: ...424 AMD Geode SC3200 Processor Data Book Package Specifications 32581C Figure 10 3 BGU481 Package Bottom View...

Page 425: ...on page 421 for the BGU481 481 terminal Ball Grid Array Cavity Up package specification Core Frequency MHz Core Voltage VCORE Temp Degree C Package2 2 Consult your local AMD sales office to confirm av...

Page 426: ...Package Specifi cations chapters See Revision 2 1 for details 2 2 July 2002 Corrected pin definitions for ball K3 on BGD432 package and ball D12 on BGU481 package Were incorrectly called out as VIO ch...

Page 427: ...27 Appendix A Data Book Revision History 32581C C February 2007 Table 9 3 Operating Conditions on page 352 Change maximum VCORE and VSBL values from 1 89V to 1 99V Table A 1 Revision History Continued...

Page 428: ...One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 TWX 910 339 9280 TELEX 34 6306 www amd com...

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