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AMD Geode SC2200 Data Book Download Page 299

AMD Geode™ SC2200  Processor Data Book

311

Core Logic Module - ISA Legacy Register Space 

32580B

Table 6-45. Programmable Interval Timer Registers 

Bit

Description

I/O Port 040h

Write

PIT Timer 0 Counter

7:0

Counter Value.

Read

PIT Timer 0 Status

7

Counter Output.

 State of counter output signal.

6

Counter Loaded.

 Indicates if the last count written is loaded.

0: Yes.
1: No.

5:4

Current Read/Write Mode.

00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.

3:1

Current Counter Mode.

 0-5.

0

BCD Mode.

0: Binary.
1: BCD (Binary Coded Decimal).

I/O Port 041h

Write

PIT Timer 1 Counter (Refresh)

7:0

Counter Value.

Read

PIT Timer 1 Status (Refresh)

7

Counter Output.

 State of counter output signal.

6

Counter Loaded.

 Indicates if the last count written is loaded.

0: Yes.
1: No.

5:4

Current Read/Write Mode.

00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.

3:1

Current Counter Mode.

 0-5.

0

BCD Mode.

 

0: Binary.
1: BCD (Binary Coded Decimal).

Summary of Contents for Geode SC2200

Page 1: ...AMD Geode SC2200 Processor Data Book AMD Geode SC2200 Processor Data Book March 2006 Publication ID 32580B...

Page 2: ...infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in othe...

Page 3: ...3 2 Strap Options 45 3 3 Multiplexing Configuration 46 3 4 Signal Descriptions 52 4 0 General Configuration Block 75 4 1 Configuration Block Addresses 75 4 2 Multiplexing Interrupt Selection and Base...

Page 4: ...l Description 321 7 3 Register Descriptions 338 8 0 Debugging and Monitoring 365 8 1 Testability JTAG 365 8 2 Engineering Note Carmel Rev B1 DFT ACP 366 9 0 Electrical Specifications 369 9 1 General S...

Page 5: ...Figure 5 13 Bit Transfer 128 Figure 5 14 Start and Stop Conditions 128 Figure 5 15 ACCESS bus Data Transaction 129 Figure 5 16 ACCESS bus Acknowledge Cycle 129 Figure 5 17 A Complete ACCESS bus Data T...

Page 6: ...9 17 Input Timing Measurement Conditions 399 Figure 9 18 PCI Reset Timing 399 Figure 9 19 Sub ISA Read Operation Timing Diagram 402 Figure 9 20 Sub ISA Write Operation Timing Diagram 403 Figure 9 21...

Page 7: ...7 Rise and Fall Timing Diagram 436 Figure 9 52 AC97 Low Power Mode Timing Diagram 437 Figure 9 53 PWRBTN Trigger and ONCTL Timing Diagram 438 Figure 9 54 GPWIO and ONCTL Timing Diagram 438 Figure 9 55...

Page 8: ...8 AMD Geode SC2200 Processor Data Book List of Figures 32580B...

Page 9: ...ssignments 98 Table 5 3 Standard Configuration Registers 101 Table 5 4 SIO Control and Configuration Register Map 103 Table 5 5 SIO Control and Configuration Registers 103 Table 5 6 Relevant RTC Confi...

Page 10: ...45 Table 5 54 Bank 7 Register Map 145 Table 5 55 Bank 0 Bit Map 145 Table 5 56 Bank 1 Bit Map 146 Table 5 57 Bank 2 Bit Map 146 Table 5 58 Bank 3 Bit Map 146 Table 5 59 Bank 4 Bit Map 146 Table 5 60 B...

Page 11: ...fset USB Controller Registers 295 Table 6 43 DMA Channel Control Registers 305 Table 6 44 DMA Page Registers 310 Table 6 45 Programmable Interval Timer Registers 311 Table 6 46 Programmable Interrupt...

Page 12: ...O Data Transfer to from Device Timing Parameters 408 Table 9 32 IDE Multiword DMA Data Transfer Timing Parameters 410 Table 9 33 IDE UltraDMA Data Burst Timing Parameters 412 Table 9 34 USB Timing Par...

Page 13: ...Power Inter face ACPI version 1 0 compliant power management and an audio codec interface The SuperI O module has three Serial Ports UART1 UART2 and UART3 with fast infrared a Parallel Port two ACCESS...

Page 14: ...troller Hardware graphics frame buffer compress decompress Hardware cursor 32x32 pixels Video Processor Module Video Accelerator Flexible video scaling support of up to 8x horizontally and vertically...

Page 15: ...fers up to 33 MB s Universal Serial Bus USB USB OpenHCI v1 0 compliant Three ports SuperI O Module Real Time Clock RTC DS1287 MC146818 and PC87911 compatible Multi century calendar ACCESS bus ACB Inte...

Page 16: ...16 AMD Geode SC2200 Processor Data Book Overview 32580B...

Page 17: ...Revision 8 1 1 Specification Update document The device ID of the SC2200 processor is contained in the GX1 module Software can detect the revision by reading the DIR0 and DIR1 Configuration registers...

Page 18: ...RASA CASA WEA CS 1 0 CKEA DQM 7 0 Drive Strength 11 is strongest 00 is weakest 23 22 RSVD Reserved Write as 0 21 RSVD Reserved Must be written as 0 Wait state on the X Bus x_data during read cycles fo...

Page 19: ...program the SDRAM devices GX_BASE 8404h 8407h MC_MEM_CNTRL2 R W Reset Value 00000801h 31 14 RSVD Reserved Write as 0 13 12 SDCLKCTL SDCLK High Drive Slew Control Controls the high drive and slew rate...

Page 20: ...ece of output data This parameter significantly affects system performance Optimal setting should be used If an SODIMM is used BIOS can interrogate EEPROM across the ACCESS bus interface to determine...

Page 21: ...7 TE Test Enable TEST 3 0 0 TEST 3 0 are driven low normal operation 1 TEST 3 0 pins are used to output test information 16 TECTL Test Enable Shared Control Pins 0 RASB CASB CKEB WEB normal operation...

Page 22: ...bit bus at the Video Processor For more information about the GX1 module s interface to the Video Processor see the Display Controller chapter in the AMD Geode GX1 Processor Data Book 2 2 Video Proces...

Page 23: ...d IR Port Interface Signals on page 67 and Section 3 4 12 Parallel Port Interface Signals on page 66 The Core Logic module interface to the GX1 module con sists of seven miscellaneous connections the...

Page 24: ...s section provides a description of the reset flow of the SC2200 2 5 1 1 Power On Reset Power on reset is triggered by assertion of the POR sig nal Upon power on reset the following things happen Stra...

Page 25: ...PD 5 0 TFTD 11 6 PE TFTD14 SLCT TFTD15 SLIN ASTRB TFTD16 STB WRITE TFTD17 Parallel Port IDE_ADDR2 TFTD4 IDE_DATA15 TFTD7 IDE_IOR0 TFTD10 IDE_IOW0 TFTD9 IDE_CS0 TFTD5 IDE_IORDY0 TFTD11 IDE_DREQ0 TFTD8...

Page 26: ...CLK AC97_RST GPIO16 PC_BEEP Power CLK32 GPWIO 2 0 LED ONCTL PWRBTN PWRCNT 1 2 THRM TCK TDI TDO TMS TRST JTAG TEST1 PLL6B TEST0 PLL2B TEST3 GXCLK FP_VDD_ON TEST2 PLL5B GTEST Test and TDP TDN GPIO11 RI2...

Page 27: ...LPC Registers Function 0 on page 198 2 Configuration settings listed in this table are with regard to the Pin Multiplexing Register PMR See Section 4 2 Multiplexing Interrupt Selection and Base Addres...

Page 28: ...33 VSS AD7 VIO AD8 GP32 GP13 VIO VSS AD3 AD6 AD5 VSS AD4 ICS1 AD1 VCORE VSS GP12 AB1D AB1C VCORE SDO SYNC ACCK VSS VSS VSS VSS VCORE VCORE VCORE VCORE AD0 IAD2 AD2 VCORE IDAT15 IDAT14 IDAT13 VSS VIO V...

Page 29: ...INT O14 14 VIO PMR 23 3 0 and PMR 27 0 and FPCI_MON 0 TFTD13 O O1 4 PMR 23 3 1 and PMR 27 0 and FPCI_MON 0 F_AD7 O O14 14 PMR 23 3 0 and PMR 27 1 or FPCI_MON 1 A19 VSS GND A206 2 PD6 I O INT O14 14 V...

Page 30: ...N 1 B22 VSS GND B23 NC B24 VSS GND Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration B25 VSS GND B26 NC B276 DPOS_PORT2 I O INUSB OUSB AVC CUSB B286 DNEG_PORT2 I O INUSB OUSB AVC CUS...

Page 31: ...PU22 5 O2 5 PMR 18 1 and PMR 8 1 Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration C29 VIO PWR C30 GPIO7 I O PU22 5 INTS O1 4 VIO PMR 17 0 and PMR 8 0 RTS2 O PU22 5 O1 4 PMR 17 1 and...

Page 32: ...O PU22 5 O1 4 PMR 18 0 and PMR 8 1 SDTEST5 O PU22 5 O2 5 PMR 18 1 and PMR 8 1 Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration D29 SOUT2 O O8 8 VIO CLKSEL2 I PD100 INSTRP Strap See...

Page 33: ...2 4 0 The IRRX2 input is connected to the input path of GPIO38 There is no logic required to enable IRRX2 just a simple con nection Hence when GPIO38 is the selected func tion IRRX2 is also selected L...

Page 34: ...22 5 INT O3 5 PMR 23 3 1 and PMR 7 0 DOCCS O O3 5 PMR 23 3 1 and PMR 7 1 P1 AD4 I O INPCI OPCI VIO Cycle Multiplexed A4 O OPCI P2 IDE_CS1 O O1 4 VIO PMR 24 0 TFTDE O O1 4 PMR 24 1 Ball No Signal Name...

Page 35: ...Name I O PU PD Buffer1 Type Power Rail Configuration V31 GPIO16 I O PU22 5 INT O2 5 VIO PMR 0 0 and FPCI_MON 0 PC_BEEP O O2 5 PMR 0 1 0 and FPCI_MON 0 F_DEVSEL O O2 5 FPCI_MON 1 W1 VIO PWR W2 VSS GND...

Page 36: ...IO AD316 MD31 I O INT TS2 5 VIO AE1 IDE_ADDR1 O O1 4 VIO PMR 24 0 TFTD2 O O1 4 PMR 24 1 AE2 VSS GND Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AE3 VIO PWR AE4 VSS GND AE28 VSS...

Page 37: ...2 I O INT TS2 5 VIO AJ21 SDCLK0 O O2 5 VIO AJ22 VIO PWR AJ23 MA6 O O2 5 VIO AJ24 MA3 O O2 5 VIO AJ25 VIO PWR Ball No Signal Name I O PU PD Buffer1 Type Power Rail Configuration AJ266 MD11 I O INT TS2...

Page 38: ...I O INT TS2 5 VIO AL28 MA12 O O2 5 VIO AL296 MD23 I O INT TS2 5 VIO AL30 VIO PWR AL31 VSS GND 1 For Buffer Type definitions refer to Table 9 10 Buffer Types on page 376 2 Is 5V tolerant ACK AFD DSTRB...

Page 39: ...3 D15 AVCCUSB D27 AVSSCRT B14 C14 C15 AVSSPLL2 C16 AVSSPLL3 AK3 AVSSUSB C27 BA0 AJ13 BA1 AK14 BHE E4 BIT_CLK U30 BLUE A15 BOOT16 C8 BUSY WAIT B17 C BE0 L1 C BE1 J2 C BE2 F3 C BE3 H4 CASA AJ12 CKEA AL2...

Page 40: ...E_DATA7 AA2 IDE_DATA8 Y3 IDE_DATA9 Y2 IDE_DATA10 Y1 IDE_DATA11 W4 IDE_DATA12 W3 IDE_DATA13 V3 IDE_DATA14 V2 IDE_DATA15 V1 IDE_DREQ0 AC4 IDE_DREQ1 C31 IDE_IOR0 Y4 IDE_IOR1 D28 IDE_IORDY0 AD1 IDE_IORDY1...

Page 41: ..._IN U31 SDATA_IN2 AL8 SDATA_OUT P29 SDCLK_IN AJ27 SDCLK_OUT AK28 SDCLK0 AJ21 SDCLK1 W29 SDCLK2 AA28 SDCLK3 V29 SDTEST0 C30 SDTEST1 B29 SDTEST2 C28 SDTEST3 E28 SDTEST4 C31 SDTEST5 D28 SERIRQ J31 SERR H...

Page 42: ...BL AL6 Signal Name Ball No VSS Total of 92 A1 A13 A16 A19 A31 B1 B7 B10 B22 B24 B25 B30 D7 D13 D19 D25 G2 G4 G28 G30 K3 K30 M1 M31 N4 N15 N16 N17 N28 P15 P16 P17 R1 R2 R3 R4 R13 R14 R15 R16 R17 R18 R1...

Page 43: ...at reset by CLKSEL 3 0 Note Values for GCB I O Offset 10h 3 0 and 1Eh 3 0 are not the same CLKSEL1 SOUT1 AF3 PD100 CLKSEL2 SOUT2 D29 PD100 CLKSEL3 SYNC P30 PD100 BOOT16 ROMCS C8 PD100 Enable boot fro...

Page 44: ...with GPIO except GPIO12 GPIO13 and GPIO16 Table 3 5 Two Signal Group Multiplexing Ball No Default Alternate Signal Configuration Signal Configuration IDE TFT CRT PCI GPIO System AD3 IDE_ADDR0 PMR 24...

Page 45: ...PMR 22 1 L31 GPIO33 LAD1 L30 GPIO34 LAD2 L29 GPIO35 LAD3 L28 GPIO36 LDRQ K31 GPIO37 LFRAME K28 GPIO38 IRRX2 LPCPD J31 GPIO39 SERIRQ UART Internal Test E28 SIN2 PMR 28 0 SDTEST3 PMR 28 1 AC97 FPCI Mon...

Page 46: ...MR 27 1 or FPCI_MON 1 D22 AFD DSTRB TFTD2 INTR_O B17 BUSY WAIT TFTD3 F_C BE1 D21 ERR TFTD4 F_C BE0 B21 INIT TFTD5 SMI_O C21 PD0 TFTD6 F_AD0 A21 PD1 TFTD7 F_AD1 D20 PD2 TFTD8 F_AD2 C20 PD3 TFTD9 F_AD3...

Page 47: ...ree Signal Group Multiplexing Continued Ball No Default Alternate1 Alternate2 Signal Configuration Signal Configuration Signal Configuration Table 3 7 Four Signal Group Multiplexing Ball No Default Al...

Page 48: ...f 1 5 K must be used ROMCS LPC_ROM D6 I LPC_ROM This strap signal forces selecting of the LPC bus and sets bit F0BAR1 I O Offset 10h 15 LPC ROM Addressing Enable It enables the SC2200 to boot from a R...

Page 49: ...main unconnected X32O AJ3 X27I AG3 I O Crystal Connections Connected directly to a 27 000 MHz crystal Some of the internal clocks are derived from this clock If an external clock is used it should be...

Page 50: ...ite Enable RAS CAS WE and CKE are encoded to support the different SDRAM commands WEA is used with CS 1 0 DQM7 AB31 O Data Mask Control Bits During memory read cycles these outputs control whether SDR...

Page 51: ...The board designer should vary the length of the board trace to control skew between SDCLK_IN and SDCLK 3 4 2 Memory Interface Signals Continued Signal Name Ball No Type Description Mux 3 4 3 Video Po...

Page 52: ...et Resistor This signal sets the current level for the RED GREEN BLUE analog outputs Typically a 464 1 resistor is connected between this ball and AVSSCRT On Chip RAMDAC RED B12 O Analog Red Green and...

Page 53: ...ng PCICLK should receive the clock with as low a skew as possible FPCI_MON Strap PCICLK1 D6 O LPC_ROM Strap AD 31 24 See Table 3 3 on page 41 I O Multiplexed Address and Data A bus transaction con sis...

Page 54: ...ally connected to a pull up resistor IRDY F2 I O Initiator Ready IRDY is asserted to indicate that the bus master is able to complete the current data phase of the transaction IRDY is used in conjunct...

Page 55: ...When LOCK is asserted non exclusive transactions may pro ceed to an address that is not currently locked at least 16 bytes must be locked A grant to start a transaction on PCI does not guarantee contr...

Page 56: ...abled in the GX1 module s PCI Control Function 2 register Index 41h 5 SERR is asserted upon asser tion of PERR This signal is internally connected to a pull up resistor REQ1 A5 I Request Lines REQ 1 0...

Page 57: ...timing is as follows In a read cycle TRDE has the same timing as RD In a write cycle TRDE is asserted to active low at the time WR is asserted It continues being asserted for one PCI clock cycle afte...

Page 58: ...uest for LPC interface Note If LDRQ function is selected but not used tie LDRQ high GPIO36 LFRAME K31 O LPC Frame A low pulse indicates the beginning of a new LPC cycle or termination of a broken cycl...

Page 59: ...DE_IOW1 C28 O GPIO9 DCD2 SDTEST2 IDE_CS0 AF2 O IDE Chip Selects 0 and 1 These signals are used to select the command block registers in an IDE device TFTD5 IDE_CS1 P2 O TFTDE IDE_IORDY0 AD1 I I O Read...

Page 60: ...hen signal s should be tied high SIN2 E28 SDTEST3 SIN3 AK8 IRRX1 SOUT1 AF3 O Serial Outputs Send composite serial data to the com munications link peripheral device modem or other data transfer device...

Page 61: ...2 C28 I Data Carrier Detected When low indicates that the data transfer device e g modem is ready to establish a communications link Note If selected as DCD2 function but not used tie DCD2 high GPIO9...

Page 62: ..._C BE0 INIT B21 O Initialize When low initializes the printer This signal is in TRI STATE after a 1 is loaded into the corresponding control register bit Use an external 4 7 K pull up resis tor TFTD5...

Page 63: ...arallel Port Interface Signals Continued Signal Name Ball No Type Description Mux 3 4 13 Fast Infrared IR Port Interface Signals Signal Name Ball No Type Description Mux IRRX1 AK8 I IR Receive Primary...

Page 64: ...the transfer of data between the SC2200 and the AC97 codec CLKSEL3 Strap AC97_CLK P31 O Codec Clock It is twice the frequency of the Audio Bit Clock AC97_RST U29 O Codec Reset S3 to S5 wakeup is not...

Page 65: ...button must be toggled This can be done externally or internally GPIO63 is internally connected to PWRBTN To toggle the power button with software GPIO63 must be programmed as an output using the norm...

Page 66: ...7 C30 RTS2 IDE_DACK1 SDTEST0 GPIO8 C31 CTS2 IDE_DREQ1 SDTEST4 GPIO9 C28 DCD2 IDE_IOW1 SDTEST2 GPIO10 B29 DSR2 IDE_IORDY1 SDTEST1 GPIO11 AJ8 RI2 IRQ15 GPIO12 N29 AB2C GPIO13 M29 AB2D GPIO14 D9 IOR DOCR...

Page 67: ...O SLIN ASTRB TFTD16 F_STOP U29 O AC97_RST F_DEVSEL V31 O GPIO16 PC_BEEP F_GNT0 U31 O SDATA_IN F_TRDY U30 O BIT_CLK INTR_O D22 O CPU Core Interrupt When enabled this signal provides for monitoring of...

Page 68: ...l testing only For normal operation leave unconnected PLL5B TEST1 AG4 O PLL6B TEST0 AH3 O PLL2B GTEST F30 I Global Test This signal is used for internal testing only For normal operation this signal s...

Page 69: ...l is connected to the internal logic through a series resistor for UL pro tection If battery backup is not desired connect VBAT to VSS VSB AL5 PWR 3 3V Standby Power Supply Provides power to the Real...

Page 70: ...74 AMD Geode SC2200 Processor Data Book Signal Definitions 32580B...

Page 71: ...e SC2200 Processor Specification Update document Reserved bits in the General Configuration block should be read as written unless otherwise specified Table 4 1 General Configuration Block Register Su...

Page 72: ...tead of Parallel Port signals Fast PCI monitoring output signals can be enabled in two ways by setting this bit to 1 or by strapping FPCI_MON ball A4 high The strapped value can be read back at MCR 30...

Page 73: ...C3 IDE_DATA0 TFTD6 A24 AC1 IDE_DATA1 TFTD16 D23 AC2 IDE_DATA2 TFTD14 C23 AB4 IDE_DATA3 TFTD12 B23 AB1 IDE_DATA4 FP_VDD_ON A23 AA4 IDE_DATA5 CLK27M C22 AA3 IDE_DATA6 IRQ9 B22 AA2 IDE_DATA7 INTD A21 Y3...

Page 74: ...1 Note 1 F_AD6 Note 2 W1 B20 SLIN ASTRB Note 1 TFTD16 Note 1 F_IRDY Note 2 W2 C20 PD3 Note 1 TFTD9 Note 1 F_AD3 Note 2 W3 D20 PD2 Note 1 TFTD8 Note 1 F_AD2 Note 2 Y1 A21 PD1 Note 1 TFTD7 Note 1 F_AD1...

Page 75: ...Flow Control Selects ball functions Ball 0 GPIO IDE Signals 1 Serial Port Signals Name Add l Dependencies Name Add l Dependencies AH4 C30 GPIO7 PMR 8 0 RTS2 PMR 8 0 IDE_DACK1 PMR 8 1 SDTEST0 PMR 8 1...

Page 76: ...K8 IRRX1 None SIN3 None J3 C11 IRTX None SOUT3 None 5 IOCS0SEL Select IOCS0 Selects ball function Works in conjunction with PMR 23 see PMR 23 for definition 4 INTCSEL Select INTC Selects ball function...

Page 77: ...cess 9 ROMZWS Enable ZWS for ROMCS Access This bit enables internal activation of ZWS Zero Wait States control for ROMCS access 0 ZWS is not active for ROMCS access 1 ZWS is active for ROMCS access 8...

Page 78: ...00h This register selects the IRQ signal of the combined WATCHDOG and High Resolution timer interrupt This interrupt is shareable with other interrupt sources 7 4 Reserved Write as read 3 0 CBIRQ Con...

Page 79: ...gnal is 1 or The GX1 module s internal SUSPA signal is 0 and the WD32KPD bit Offset 02h 8 is 0 The 32 KHz input clock is disabled when The GX1 module s internal SUSPA signal is 0 and the WD32KPD bit i...

Page 80: ...his register selects the signal to be generated when the timer reaches 0 whether or not to disable the 32 KHz input clock during low power states and the prescaler value of the clock input 15 9 Reserv...

Page 81: ...ult value The input clock derived from the 27 MHz crystal oscillator is enabled when The GX1 module s internal SUSPA signal is 1 or The GX1 module s internal SUSPA signal is 0 and bit TM27MPD Offset 0...

Page 82: ...0Dh TIMER Configuration Register TMCNFG R W Reset Value 00h This register enables the High Resolution Timer interrupt selects the Timer clock and disables the 27 MHz internal clock during low power st...

Page 83: ...functional description of the RTC Figure 4 2 Clock Generation Block Diagram 32 768 KHz Crystal External PCI Clock PLL5 Internal Fast PCI Clock PLL6 ACPI Clock 14 318 MHz PLL2 Dot Clock Core Clock ADL...

Page 84: ...can vary from 0 to 10 pF The rule of thumb in choosing these capacitors is CL C1 C2 C1 C2 CPARASITIC Example 1 Crystal CL 10 pF CPARASITIC 8 2 pF C1 3 6 pF C2 3 6 pF Example 2 Crystal CL 20 pF CPARASI...

Page 85: ...0 balls These can be read in the internal Fast PCI Clock field in the CCFC register GCB I O Offset 1Eh 9 8 See Table 4 9 on page 92 details on the CCFC register Note Not all speeds are supported For i...

Page 86: ...CI Interface uses a 33 3 MHz clock that is created by PLL5 and divided by 2 PLL5 uses the 27 MHz clock to output a 66 67 MHz clock PLL5 has a frequency accuracy of 0 1 AC97 The SC2200 generates the 24...

Page 87: ...k is disabled 5 GPD Disable Graphic Pixel Reference Clock 0 PLL2 input clock is enabled 1 PLL2 input clock is disabled 4 Reserved 3 PLL3SD Shut Down PLL3 AC97 codec clock 0 PLL3 is enabled 1 PLL3 is s...

Page 88: ...33 3 MHz 01 48 MHz 10 66 7 MHz 11 33 3 MHz 7 4 Reserved 3 0 MVAL Multiplier Value This 4 bit value controls the multiplier in ADL The value is set according to the Maximum Clock Multiplier bits of th...

Page 89: ...provides RTC timekeeping Outstanding Features Full compatibility with ACPI Revision 1 0 requirements System Wakeup Control powered by VSB generates power up request and a PME power management event in...

Page 90: ...0 Mbps FIR Selectable internal or external modulation demodula tion ASK IR and DASK IR options of SHARP IR Consumer IR TV Remote mode Consumer Remote Control supports RC 5 RC 6 NEC RCA and RECS 80 DMA...

Page 91: ...and Play ISA Specification Version 1 0a by Intel and Microsoft All sys tem resources assigned to the functional blocks I O address space DMA channels and IRQ lines are config ured in and managed by t...

Page 92: ...tructure of the standard PnP config uration register file The SIO Control And Configuration registers are not banked and are accessed by the Index Data register pair only as described above However th...

Page 93: ...after VSB is powered up The SIO module wakes up with the default setup as fol lows When a hardware reset occurs The configuration base address is 2Eh 15Ch or None according to the IO_SIOCFG_IN bit val...

Page 94: ...Configuration Registers Index 60h 75h These registers are used to manage the resource allocation to the functional blocks The I O port base address descriptor 0 is a pair of registers at Index 60h 61h...

Page 95: ...bits 7 0 for I O Descriptor 0 Index 62h I O Port Base Address Bits 15 8 Descriptor 1 R W 7 0 Descriptor 1 A 15 8 Selects I O lower limit address bits 15 8 for I O Descriptor 1 Index 63h I O Port Base...

Page 96: ...DMA channel 7 3 Reserved 2 0 DMA 1 Channel Select This bit field selects the DMA channel for DMA 1 The valid choices are 0 3 where a value of 0 selects DMA channel 0 1 selects channel 1 etc A value of...

Page 97: ...tch This bit controls bits 7 and 6 of this register Once this bit is set to 1 by software it can be cleared to 0 only by a hardware reset 0 Bits 7 and 6 of this register are R W bits Default 1 Bits 7...

Page 98: ...gisters Table 5 6 Relevant RTC Configuration Registers Index Type Configuration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not acces...

Page 99: ...the Extended RAM access Default 1 Writes to bytes 00h 1Fh of the Extended RAM are ignored 4 Block Extended RAM Read This bit controls read from bytes 00h 1Fh of the Extended RAM 0 No effect on Extend...

Page 100: ...guration Register or Action Reset Value 30h R W Activate When bit 0 is cleared the registers of this logical device are not accessible 1 00h 60h R W Base Address MSB register 00h 61h R W Base Address...

Page 101: ...h Table 5 10 IRCP SP3 Configuration Register Bit Description Index F0h Infrared Communication Port Serial Port 3 Configuration Register R W Reset Value 02h 7 Bank Select Enable Enables bank switching...

Page 102: ...75h RO Report no DMA assignment 04h 04h F0h R W Serial Ports 1 and 2 Configuration register 02h 02h Table 5 12 Serial Ports 1 and 2 Configuration Register Bit Description Index F0h Serial Ports 1 and...

Page 103: ...page 101 for descriptions of the others Table 5 13 Relevant ACB1 and ACB2 Registers Index Type Configuration Register or Action Reset Value 30h R W Activate See also bit 0 of the SIOCF1 register 00h...

Page 104: ...are RO 00000b Bit 2 for A10 should be 0b 02h 61h R W Base Address LSB register Bits 1 and 0 A1 and A0 are RO 00b For ECP Mode 4 EPP or when using the Extended registers bit 2 A2 should also be 0b 78h...

Page 105: ...nal as the basic clock for timekeeping The 32 768 KHz clock can be sup plied by the internal oscillator circuit or by an external oscillator see Section 5 5 2 2 External Oscillator on page 112 5 5 2 1...

Page 106: ...f square or sine wave of 0 0V to VCORE amplitude The signal should have a duty cycle of approximately 50 It should be sourced from a battery backed source in order to oscillate during power down This...

Page 107: ...mecha nism enables new time parameters to be loaded in the RTC Method 2 1 Access the RTC registers after detection of an Update Ended interrupt This implies that an update has just been completed and...

Page 108: ...power supply or VSB main battery To assure that the module uses power from VSB and not from VBAT the VSB voltage should be maintained above its minimum as detailed in Section 9 0 Electrical Specifica...

Page 109: ...ff spurious bus transactions from the host may occur To protect the RTC internal regis ters from corruption all inputs are automatically locked out The lockout condition is asserted when VSB is lower...

Page 110: ...wer down The RAMs are Standard RAM Extended RAM The memory maps and register content of the RAMs is provided in Section 5 5 4 RTC General Purpose RAM Map on page 122 The first 14 bytes and 3 programma...

Page 111: ...RTC Control Register A Bit specific 0Bh R W CRB RTC Control Register B Bit specific 0Ch RO CRC RTC Control Register C Bit specific 0Dh RO CRD RTC Control Register D VPP PUR Programmable1 R W DOMA Dat...

Page 112: ...0 Timing registers not updated within 244 s 1 Timing registers updated within 244 s 6 4 Divider Chain Control These bits control the configuration of the divider chain for timing generation and regist...

Page 113: ...is read 0 No alarm detected since the last read 1 Alarm condition detected 4 Update Ended Interrupt Flag Cleared to 0 on RTC reset i e hardware or software reset or the RTC disabled In addi tion this...

Page 114: ...070 2 0 1 0 0 0 244141 3 0 1 0 1 0 488281 4 0 1 1 0 0 976562 5 0 1 1 1 1 953125 6 1 0 0 0 3 906250 7 1 0 0 1 7 812500 8 1 0 1 0 15 625000 9 1 0 1 1 31 250000 10 1 1 0 0 62 500000 11 1 1 0 1 125 000000...

Page 115: ...Change the backup battery while normal operating power is present and not in backup mode to maintain valid time and register information If a low leakage capacitor is connected to VBAT the battery may...

Page 116: ...f matching can be used as a wakeup event The CEIR address detection operates independently of the Serial Port with the IR which is powered down with the rest of the system Whenever an IR signal is det...

Page 117: ...Type Name Reset Value 00h R W1C WKSR Wakeup Events Status Register 00h 01h R W WKCR Wakeup Events Control Register 03h 02h R W WKCFG Wakeup Configuration Register 00h Table 5 28 Bank 1 CEIR Wakeup Co...

Page 118: ...n 0 Event not detected Default 1 Event detected Offset 01h Wakeup Events Control Register WKCR R W Reset Value 03h This register is set to 03h on power up of VPP or software reset Detected wakeup even...

Page 119: ...dress Mask If the corresponding bit is 0 the address bit is not masked enabled for compare If the corresponding bit is 1 the address bit is masked ignored during compare Bank 1 Offset 07h CEIR Address...

Page 120: ...re not used when the RC 5 protocol is selected NEC protocol The header pulse width must fall within this range in order for the header to be considered valid The nominal value is 9 msec for a 38 KHz c...

Page 121: ...mpled during the high state of the serial clock ABC Consequently throughout the clock s high period the data should remain stable see Figure 5 13 Any changes on the ABD line during the high state of t...

Page 122: ...ver must pull down the ABD line during the ACK clock pulse signalling that it has cor rectly received the last data byte and is ready to receive the next byte Figure 5 16 illustrates the ACK cycle Fig...

Page 123: ...Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands Control of the bus is initially determined according to address bits and cloc...

Page 124: ...lso check that ACBST 3 is cleared and clear it if required 2 Write the data byte to be transmitted to the ACBSDA When either ACBST 5 or ACBST 4 is set an interrupt is generated When the slave responds...

Page 125: ...vice continues to search the received message for a match If an address match or a global match is detected 1 The device asserts its ABD pin during the acknowl edge cycle 2 ACBCST 2 and ACBST 2 are se...

Page 126: ...ave Stop R W1C Writing 0 to SLVSTP is ignored 0 Writing 1 or ACB disabled 1 Stop Condition detected after a slave transfer in which ACBCST 2 or ACBCST 3 was set 6 SDAST SDA Status RO 0 Reading from AC...

Page 127: ...Condition including illegal Start or Stop Condition 1 ACBADDR 7 is set and the first 7 bits of the address byte the first byte transferred after a Start Condition match the 7 bit address in ACBADDR 1...

Page 128: ...t Condition is generated This condition can be used to switch the direction of the data flow between the master and the slave or to choose another slave device without separating them with a Stop Cond...

Page 129: ...cond level offsets EPP and second level offset registers are available only when the base address is 8 byte aligned Parallel Port functional block bit maps are shown in Table 5 35 and Table 5 36 Table...

Page 130: ...400h CFIFO Data Bits 400h DFIFO Data Bits 400h TFIFO Data Bits 400h CNFGA RSVD Bit 7 of PP Confg0 RSVD 401h CNFGB RSVD Interrupt Request Value Interrupt Select RSVD DMA Channel Select 402h ECR ECP Mod...

Page 131: ...P1 and SP2 Register and Bit Maps for UART Functionality The tables in this subsection provide register and bit maps for Banks 0 through 3 Figure 5 18 UART Mode Register Bank Architecture Bank 0 Bank 1...

Page 132: ...W LBGD H Legacy Baud Generator Divisor Port High Byte 02h RSVD Reserved 03h W LCR1 Line Control R W BSR1 Bank Select 04h 07h RSVD Reserved 1 When bit 7 of this register is set to 1 bits 6 0 of BSR sel...

Page 133: ...LS_IE TXLDL_IE RXHDL_IE 02h EIR1 FEN 1 0 RSVD RXFT IPR1 IPR0 IPF EIR2 RSVD TXEMP_EV RSVD 3 DMA_EV 4 MS_EV LS_EV or TXHLT_EV TXLDL_EV RXHDL_EV FCR RXFTH 1 0 TXFTH 1 0 RSVD TXSR RXSR FIFO_EN 03h LCR5 BK...

Page 134: ...as shown in Table 5 38 on page 139 Table 5 44 Bank 2 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h BGD L BGD 7 0 Low Byte 01h BGD H BGD 15 8 High Byte 02h EXCR1 BTEST RSVD ETDLBK LOOP RSVD EXT...

Page 135: ...eight registers con trol IR SP3 operation All registers use the same 8 byte address space to indicate offsets 00h through 07h The BSR register selects the active bank and is common to all banks See F...

Page 136: ...BGD L Legacy Baud Generator Divisor Port Low Byte 01h R W LBGD H Legacy Baud Generator Divisor Port High Byte 02h RSVD Reserved 03h W LCR1 Link Control R W BSR1 Bank Select 04h 07h RSVD Reserved 1 Whe...

Page 137: ...RO TFRCC L Transmission Current Count Low Byte 05h R W TFRL H Transmission Frame Length High Byte RO TFRCC H Transmission Current Count High Byte 06h R W RFRML L Reception Frame Maximum Length Low Byt...

Page 138: ...ble 5 55 Bank 0 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h RXD RXD 7 0 Receive Data TXD TXD 7 0 Transmit Data 01h IER1 RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER2 TMR_IE SFIF_IE TXEMP_ IE PLD_I...

Page 139: ...ect 04h EXCR2 LOCK RSVD PRESL 1 0 RF_SIZ 1 0 TF_SIZ 1 0 05h RSVD RSVD 06h TXFLV RSVD TFL 5 0 07h RXFLV RSVD RFL 5 0 Table 5 58 Bank 3 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h MID MID 3 0...

Page 140: ...X_LEN PHY_ERR BAD_CRC OVR1 OVR2 06h RFRL L LSTFRC RFRL 7 0 Low Byte Data LSTFRC 7 0 07h RFRL H RFRL 15 8 High Byte Data Table 5 61 Bank 6 Bit Map Register Bits Offset Name 7 6 5 4 3 2 1 0 00h IRCR3 SH...

Page 141: ...dependent USB interfaces Open Host Controller Interface OpenHCI specification compliant PCI Interface PCI 2 1 compliant PCI master for AC97 and IDE controllers Subtractive agent for unclaimed transact...

Page 142: ...Low Pin Count LPC Interface Based on Intel LPC Interface Specification Revision 1 0 Serial IRQ support 6 2 Module Architecture The Core Logic architecture provides the internal functional blocks show...

Page 143: ...or legacy DMA masters These memory cycles are always forwarded to the Fast PCI interface 6 2 1 4 External PCI Bus The external PCI bus is a fully compliant PCI bus PCI slots are connected to this bus...

Page 144: ...urs when a PCI master cycle targeting the IDE data port is decoded and the IDE_ADDR 2 0 and IDE_CS lines are not set up Address latency provides the setup time for the IDE_ADDR 2 0 and IDE_CS lines pr...

Page 145: ...o be transferred is described by a Physical Region Descriptor PRD as illus trated in Table 6 1 When the bus master is enabled Com mand register bit 0 1 data transfer proceeds until each PRD in the PRD...

Page 146: ...e Logic and the IDE via providing data toggling STROBE and DMARDY The IDE_DATA 15 0 is latched by receiver on each rising and falling edge of STROBE The transmitter can pause the burst cycle by holdin...

Page 147: ...CR is active otherwise it is inactive DOCW DOCW is asserted on memory write transactions to DOCCS window i e when both DOCCS and MEMW are active DOCW is active otherwise it is inactive RD WR The signa...

Page 148: ...ip between a PCI cycle and the corresponding ISA cycle generated Note Not all signals described in Figure 6 2 are available externally See Section 3 4 7 Sub ISA Interface Signals on page 61 for more i...

Page 149: ...isters on the on chip I O data bus When PCI data bus drivers of the Core Logic module are in TRI STATE data transfers between the PCI bus master and PCI bus devices are handled directly via the PCI da...

Page 150: ...sends a bus grant request to the PCI arbiter After the PCI bus has been granted the respective DACK is driven active The Core Logic module generates PCI memory read or write cycles in response to a DM...

Page 151: ...the number of balls on the device Cycle multiplexing is on a bus cycle by bus cycle basis see Figure 6 6 on page 160 where the internal Core Logic PCI bridge arbitrates between PCI cycles and Sub ISA...

Page 152: ...DMA interface signals are not available externally DMA Channels The Core Logic module supports seven DMA channels using two standard 8237 equivalent controllers DMA Con troller 1 contains Channels 0...

Page 153: ...ypes of transfers read write or ver ify The transfer type selected defines the method used to transfer a byte or WORD during one DMA bus cycle For read transfer types the Core Logic module reads data...

Page 154: ...set up by the system before a DMA operation The DMA Page register values are driven on PCI address bits AD 31 16 for 8 bit channels and AD 31 17 for 16 bit channels The middle address portion which se...

Page 155: ...with GPIO39 function See Table 6 4 The Core Logic module allows PCI interrupt signals INTA INTB INTC muxed with GPIO19 IOCHRDY and INTD muxed with IDE_DATA7 to be routed internally to any IRQ signal T...

Page 156: ...ontroller should be programmed with the value 02h slave ID and corresponds to the input on the master controller PIC Shadow Register The PIC registers are shadowed to allow for 0V Suspend to save rest...

Page 157: ...n SMI for an NMI Note that NMI is not a pin 6 2 8 Keyboard Support The Core Logic module can actively decode the keyboard controller I O Ports 060h 062h 064h and 066h and gener ate an LPC bus cycle Ke...

Page 158: ...er planes It also supports systems with an external micro controller that is used as a power management controller 6 2 9 1 CPU States The SC2200 supports three CPU states C0 C1 and C3 the Core Logic C...

Page 159: ...ate The SC2200 keeps all context in this state This state corresponds to ACPI sleep state S1 with lower power and longer wake time than in SL1 SL3 Sleep State ACPI S3 In this state the SDRAM is placed...

Page 160: ...ansition of the system from a Sleep state to a Work state This is done by the hardware These events are defined as wakeup events Enabled wakeup events to set the WAK_STS bit F1BAR1 I O Offset 08h 15 t...

Page 161: ...a wakeup event or an interrupt is generated note that this is regardless of the PWRBTN_EN bit F1BAR1 I O Offset 0Ah 8 Power Button Sleep Event Detection of a high to low transition on the debounced PW...

Page 162: ...d is dis cussed in Section 6 2 10 3 Peripheral Power Management on page 172 APM if available is used primarily by CPU power manage ment since the operating system is most capable of report ing the Idl...

Page 163: ...ter F1BAR0 I O Offset 08h The SMI Speedup Disable register prevents VSA software from entering Suspend Modulation while operating in SMM The data read from this register can be ignored If the Suspend...

Page 164: ...e timers are F0 Index 81h 7 Video Access Idle Timer Enable F0 Index 82h 7 Video Access Trap Enable F0 Index A6h 15 0 Video Timer Count F0 Index 83h 3 VGA Timer Enable F0 Index 8Bh 6 VGA Timer Base F0...

Page 165: ...eporting The sec ond level of SMI status reporting is set up very much like the top level There are two status reporting registers one read only mirror and one read to clear The data returned by readi...

Page 166: ...vice 1 Idle Timer 81h 4 A0h 15 0 C0h 31 0 CCh 7 0 85h 4 F5h 4 User Defined Device 2 Idle Timer 81h 5 A2h 15 0 C4h 31 0 CDh 7 0 85h 5 F5h 5 User Defined Device 3 Idle Timer 81h 6 A4h 15 0 C8h 31 0 CEh...

Page 167: ...FFh or COM4 I O Port 2E8h 2EFh Support trapping for low I O Port 00h 0Fh and or high I O Port C0h DFh DMA accesses Support hardware status register reads in Core Logic module minimizing SMI overhead S...

Page 168: ...dress of the JMP The target address must be on a 32 byte boundary so bits 4 0 must be written to 0 There is no data transfer with this PRD This PRD allows the creation of a looping mechanism If a PRD...

Page 169: ...by 08h and is now pointing to PRD_3 The SMI Status register is read to clear the End of Page status flag Since Audio Buffer_1 is now empty the software can refill it At the completion of PRD_2 an SMI...

Page 170: ...rs The codec 32 bit related registers GPIO Status and Control Registers Codec GPIO Status Register F3BAR0 Memory Offset 00h Codec GPIO Control Register F3BAR0 Memory Offset 04h Codec Status Register F...

Page 171: ...ffset 14h I O Trap SMI Enable Register F3BAR0 Memory Offset 18h Audio SMI Status Reporting Registers The Top SMI Status Mirror and Status registers are the top level of hierarchy for the SMI Handler i...

Page 172: ...External SMI Call internal SMI handler to take appropriate action GX1 Core Logic Module F1BAR0 Memory Read to Clear to determine top level source of SMI F3BAR0 Memory Offset 10h Read to Clear SMI De...

Page 173: ...er to the LPC specification directly The goals of the LPC interface are to Enable a system without an ISA bus Reduce the cost of traditional ISA bus devices Use on a motherboard only Perform the same...

Page 174: ...PCI 33 MHz clock signal PCICLK instead Core Logic module optional LPC signals LDRQ Encoded DMA Bus Master Request Only needed by peripheral that need DMA or bus mastering Peripherals may not share the...

Page 175: ...he Configuration Data Register CDR To access PCI configuration space write the Configuration Address 0CF8h Register with data that specifies the Core Logic module as the device on PCI being accessed a...

Page 176: ...ed GPIO Runtime and Configuration Registers sum marized in Table 6 15 00000001h Page 200 14h 17h 32 R W Base Address Register 1 F0BAR1 Sets the base address for the I O mapped LPC Configuration Regist...

Page 177: ...00h Page 221 8Eh 8 R W VGA Timer Count Register 00h Page 221 8Fh 92h Reserved 00h Page 221 93h 8 R W Miscellaneous Device Control Register 00h Page 221 94h 95h 16 R W Suspend Modulation Register 0000...

Page 178: ...r Defined Device 1 Control Register 00h Page 227 CDh 8 R W User Defined Device 2 Control Register 00h Page 227 CEh 8 R W User Defined Device 3 Control Register 00h Page 228 CFh Reserved 00h Page 228 D...

Page 179: ...IO Signal Configuration Select Register 00000000h Page 235 24h 27h 32 R W GPIO Signal Configuration Access Register 00000044h Page 235 28h 2Bh 32 R W GPIO Reset Control Register 00000000h Page 236 Tab...

Page 180: ...rved 00h Page 245 40h 43h 32 R W Base Address Register 1 F1BAR1 Sets the base address for the I O mapped ACPI Support Registers summarized in Table 6 19 00000001h Page 245 44h FFh Reserved 00h Page 24...

Page 181: ...h Page 256 0Ah 0Bh 16 R W PM1A_EN PM1A Enable Register 0000h Page 257 0Ch 0Dh 16 R W PM1A_CNT PM1A Control Register 0000h Page 258 0Eh 8 R W ACPI_BIOS_STS Register 00h Page 258 0Fh 8 R W ACPI_BIOS_EN...

Page 182: ...00000000h Page 266 18h 1Bh 32 RO Base Address Register 2 F2BAR2 Reserved for possible future use by the Core Logic module 00000000h Page 266 1Ch 1Fh 32 RO Base Address Register 3 F2BAR3 Reserved for...

Page 183: ...er Registers for Audio Support Summary F3 Index Width Bits Type Name Reset Value Reference Table 6 37 00h 01h 16 RO Vendor Identification Register 100Bh Page 272 02h 03h 16 RO Device Identification Re...

Page 184: ...t Used Page 281 24h 27h 32 R W Audio Bus Master 0 PRD Table Address 00000000h Page 281 28h 8 R W Audio Bus Master 1 Command Register 00h Page 282 29h 8 RC Audio Bus Master 1 SMI Status Register 00h Pa...

Page 185: ...ure use by the Core Logic module 00000000h Page 288 20h 23h 32 R W Base Address Register 4 F5BAR4 Reserved for possible future use by the Core Logic module 00000000h Page 288 24h 27h 32 R W Base Addre...

Page 186: ...ge 293 0Ch 8 R W Cache Line Size 00h Page 293 0Dh 8 R W Latency Timer 00h Page 293 0Eh 8 RO Header Type 00h Page 293 0Fh 8 RO BIST Register 00h Page 293 10h 13h 32 R W Base Address 0 00000000h Page 29...

Page 187: ...97 28h 2Bh 32 R W HcBulkHeadED 00000000h Page 297 2Ch 2Fh 32 R W HcBulkCurrentED 00000000h Page 297 30h 33h 32 R W HcDoneHead 00000000h Page 297 34h 37h 32 R W HcFmInterval 00002EDFh Page 298 38h 3Bh...

Page 188: ...r Not Used Page 307 0C4h R W DMA Channel 5 Address Register Page 307 0C6h R W DMA Channel 5 Transfer Count Register Page 307 0C8h R W DMA Channel 6 Address Register Page 307 0CAh R W DMA Channel 6 Tra...

Page 189: ...Master Slave PIC OCW2 Page 314 020h 0A0h WO Master Slave PIC OCW3 Page 314 020h 0A0h RO Master Slave PIC Interrupt Request and Service Registers for OCW3 Commands Page 314 Keyboard Controller Registe...

Page 190: ...ey are read a byte at a time status bits may be lost or not cleared 6 4 1 Bridge GPIO and LPC Registers Function 0 The register space designated as Function 0 F0 is used to configure Bridge features a...

Page 191: ...whenever the Core Logic module asserts SERR active Write 1 to clear 13 Received Master Abort This bit is set whenever a master abort cycle occurs A master abort occurs when a PCI cycle is not claimed...

Page 192: ...unction device bit 7 1 or not bit 7 0 Index 0Fh PCI BIST Register RO Reset Value 00h This register indicates various information about the PCI Built In Self Test BIST mechanism Note This mechanism is...

Page 193: ...gister space an SMI is generated Writes are trapped access to the register is denied Reads are snooped access to the register is allowed 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 I...

Page 194: ...sible on PCI Default 1 Accesses to Primary IDE channel I O addresses are delayed transactions on PCI For best performance of VIP this bit should be set to 1 unless PIO mode 3 or 4 are used 2 Enable PC...

Page 195: ...e reset used only for clock configuration at power up Index 45h Reserved Reset Value 00h Index 46h PCI Functions Enable Register R W Reset Value FEh 7 6 Reserved Resets to 11 5 F5 PCI Function 5 When...

Page 196: ...ter 0 output OUT0 to pass to IRQ0 3 PIT Counter 0 Enable 0 Sets GATE0 input low 1 Sets GATE0 input high 2 0 ISA Clock Divisor Determines the divisor of the PCI clock used to make the ISA clock which i...

Page 197: ...ROM space asserts ROMCS enabling the write cycle to the Flash device on the ISA bus Otherwise ROMCS is inhibited for writes If strapped for LPC and this bit is set to 1 the cycle runs on the LPC bus...

Page 198: ...r subtractive decoding for accesses to I O Ports 060h and 064h as well as 062h and 066h if enabled F4 Index 5Bh 7 1 0 Subtractive 1 Positive Note If F0BAR1 I O Offset 10h bits 10 0 and 16 1 then this...

Page 199: ...served 1100 IRQ12 0001 IRQ1 0101 IRQ5 1001 IRQ9 1101 Reserved 0010 Reserved 0110 IRQ6 1010 IRQ10 1110 IRQ14 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 Index 5Dh PCI Interrupt Steering Register 2 R W Re...

Page 200: ...n to 0 15 8 Reserved Must be written to FFh 7 4 ROM Size If F0 Index 52h 2 1 0000 16 MB FF000000h FFFFFFFFh 1000 8 MB FF800000h FFFFFFFFh 1100 4 MB FFC00000h FFFFFFFFh 1110 2 MB FFE00000h FFFFFFFFh 11...

Page 201: ...t field is used to select the range of IOCS0 00000 1 Byte 01111 16 Bytes 00001 2 Bytes 11111 32 Bytes 00011 4 Bytes All other combinations are reserved 00111 8 Bytes Index 77h Reserved Reset Value 00h...

Page 202: ...ration when system is power managed using CPU Suspend modulation 0 Disable 1 Enable The duration of the speedup is configured in the IRQ Speedup Timer Count Register F0 Index 8Ch 2 Traps Globally enab...

Page 203: ...d count UDEF1 address programming is at F0 Index C0h base address register and CCh control register Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported...

Page 204: ...ss occurs in the programmed address range an SMI is generated UDEF3 address programming is at F0 Index C8h Base Address register and CEh Control register 0 Disable 1 Enable Top level SMI status is rep...

Page 205: ...0h 02h 0 Second level SMI status is reported at F0 Index 86h F6h 0 Index 83h Power Management Enable Register 4 R W Reset Value 00h 7 Secondary Hard Disk Idle Timer Enable Turn on Secondary Hard Disk...

Page 206: ...imer s load is multi sourced and gets reloaded any time an enabled event F0 Index 89h 6 0 occurs GP Timer 1 programming is at F0 Index 8Bh 4 Top level SMI status is reported at F1BAR0 I O Offset 00h 0...

Page 207: ...ce 2 Idle Timer Count Register F0 Index A2h 0 No 1 Yes To enable SMI generation set F0 Index 81h 5 to 1 4 User Defined Device Idle Timer 1 Timeout Indicates whether or not an SMI was caused by expirat...

Page 208: ...ex 83h 6 to 1 4 Secondary Hard Disk Idle Timer SMI Status Indicates whether or not an SMI was caused by expiration of Secondary Hard Disk Idle Timer Count register F0 Index ACh 0 No 1 Yes To enable SM...

Page 209: ...o enable SMI generation set F1BAR1 I O Offset 0Ch 0 to 0 2 Codec SDATA_IN SMI Status Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on SDATA_IN 0 No 1 Yes To enable...

Page 210: ...e I O address range listed below reloads General Purpose Timer 1 Keyboard Controller I O Ports 060h 064h COM1 I O Port 3F8h 3FFh if F0 Index 93h 1 0 10 this range is included COM2 I O Port 2F8h 2FFh i...

Page 211: ...ift GP Timer 1 is treated as an 8 bit or 16 bit timer 0 8 bit The count value is that loaded into GP Timer 1 Count Register F0 Index 88h 1 16 bit The value loaded into GP Timer 1 Count Register is shi...

Page 212: ...n Serial Enable Mouse is present on a serial port 0 No 1 Yes If a mouse is attached to a serial port i e this bit is set to 1 that port is removed from the serial device list being used to monitor ser...

Page 213: ...t value programmed here represents the period of hard disk inactivity after which the sys tem is alerted via an SMI The timer is automatically reloaded with the count value whenever an access occurs t...

Page 214: ...Index 81h 5 1 Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 0 Second level SMI status is reported at F0 Index 85h F5h 5 Index A4h A5h User Defined Device 3 Idle Timer Count Register R...

Page 215: ...ystem clocks Upon a Resume event the internal SUSP_3V signal is de asserted After a slight delay the Core Logic module de asserts the SUSP signal Once the clocks are stable the GX1 module de asserts S...

Page 216: ...Each shadow register in the sequence contains the last data written to that location The read sequence for this register is 1 PIC1 ICW1 2 PIC1 ICW2 3 PIC1 ICW3 4 PIC1 ICW4 Bits 7 5 of ICW4 are always...

Page 217: ...the internal SUSP signal Index BDh BFh Reserved Reset Value 00h Index C0h C3h User Defined Device 1 Base Address Register R W Reset Value 00000000h 31 0 User Defined Device 1 Base Address This 32 bit...

Page 218: ...Index CEh User Defined Device 3 Control Register R W Reset Value 00h 7 Memory or I O Mapped Determines how User Defined Device 3 is mapped 0 I O 1 Memory 6 0 Mask If bit 7 0 I O Bit 6 0 Disable write...

Page 219: ...F1BAR1 I O Offset 15h 4 to 1 to allow SMI generation Index F5h Second Level PME SMI Status Register 2 RC Reset Value 00h The bits in this register contain second level status reporting Top level statu...

Page 220: ...status at both the second and top levels A read only Mirror version of this register exists at F0 Index 86h If the value of the register must be read without clearing the SMI source and consequently d...

Page 221: ...y of the GPIOs GPIO47 GPIO32 and GPIO15 GPIO0 0 No 1 Yes To enable SMI generation set F1BAR1 I O Offset 0Ch 0 0 F0BAR0 I O Offset 08h 18h selects which GPIOs are enabled to generate a PME and setting...

Page 222: ...atus Indicates whether or not an SMI was caused by an ACPI Timer F1BAR0 I O Offset 1Ch or F1BAR1 I O Offset 1Ch MSB toggle 0 No 1 Yes To enable SMI generation set F0 Index 83h 5 1 Index F8h FFh Reserv...

Page 223: ...nabled GPIO PMEs are always reported at F1BAR1 I O Offset 10h 3 2 Any enabled GPIO PME can be selected to generate an SCI or SMI at F1BAR1 I O Offset 0Ch 0 If SCI is selected then the individually sel...

Page 224: ...R1 I O Offset 12h 3 and the status is reported at F1BAR1 I O Offset 10h 3 If SMI is selected the individually selected GPIO PMEs generate an SMI and the status is reported at F1BAR0 I O Offset 00h 02h...

Page 225: ...ll W4 111001 GPIO57 101010 GPIO42 111010 GPIO58 101011 GPIO43 111011 GPIO59 101100 GPIO44 111100 GPIO60 101101 GPIO45 111101 GPIO61 101110 GPIO46 111110 GPIO62 101111 GPIO47 111111 GPIO63 Note Note GP...

Page 226: ...pull up capability of the selected GPIO signal It supports open drain output signals with internal pull ups and TTL input signals 0 Disable 1 Enable Default Bits 1 0 of this register must 01 for this...

Page 227: ...ignal 0 PCI INTD ball AA2 1 LPC SERIRQ ball J31 19 INTC Source Selects the interface source of the INTC signal 0 PCI INTC ball C9 1 LPC SERIRQ ball J31 18 INTB Source Selects the interface source of t...

Page 228: ...cts the interface source of the IRQ0 signal 0 ISA IRQ0 Internal signal Connected to OUT0 System Timer of the internal 8254 PIT 1 LPC SERIRQ ball J31 Offset 04h 07h SERIRQ_LVL Serial IRQ Level Control...

Page 229: ...rface source for IRQ9 F0BAR1 I O Offset 00h 9 1 this bit allows signal polarity selection 0 Active high 1 Active low 8 IRQ8 Polarity If LPC is selected as the interface source for IRQ8 F0BAR1 I O Offs...

Page 230: ...24 frames 1011 28 frames 1111 32 frames 1 0 Start Frame Pulse Width 00 4 Clocks 01 6 Clocks 10 8 Clocks 11 Reserved Offset 0Ch 0Fh DRQ_SRC DRQ Source Register R W Reset Value 00000000h Note DRQx are i...

Page 231: ...d to LPC when using the internal SuperI O module and if IO_SIOCFG_IN F5BAR0 I O Offset 00h 26 25 10 12 LPC Ad Lib Addressing Ad Lib addresses I O Ports 388h 389h See bit 16 for decode 11 LPC ACPI Addr...

Page 232: ...fset 10h 6 13 12 LPC Microsoft Sound System MSS Address Select Selects I O Port 00 530h 537h 10 E80h E87h 01 604h 60Bh 11 F40h F47h Selected address range is enabled via F0BAR1 I O Offset 10h 5 11 10...

Page 233: ...I O Offset 02h 3 Second level status is reported at bit 6 of this register 8 SMI Configuration for LPC Error Enable Allows LPC errors to generate an SMI 0 Disable 1 Enable Top Level SMI status is rep...

Page 234: ...write operation on LPC 0 No 1 Yes Write 1 to clear 1 LPC Error DMA Status Indicates whether or not an error was generated during a DMA operation on LPC 0 No 1 Yes Write 1 to clear 0 LPC Error Memory...

Page 235: ...r RO Reset Value 068000h Index 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI BI...

Page 236: ...rce is NMI Indicates whether or not an SMI was caused by NMI activity 0 No 1 Yes 11 SMI Source is IRQ2 of SIO Module Indicates whether or not an SMI was caused by IRQ2 of the SIO module 0 No 1 Yes The...

Page 237: ...cept for the read only bits because they have a second level of status reporting Clearing the second level status bits also clears the top level except for GPIOs GPIO SMIs have third level of SMI stat...

Page 238: ...No 1 Yes To enable SMI generation set F0 Index 83h 3 to 1 5 SMI Source is Video Retrace Read to Clear Indicates whether or not an SMI was caused by a video retrace event as decoded from the internal...

Page 239: ...Access to User Defined Device 3 Indicates whether or not an SMI was caused by a trapped I O or memory access to the User Defined Device 3 F0 Index C8h 0 No 1 Yes To enable SMI generation set F0 Index...

Page 240: ...User Defined Device 2 UDEF2 Indicates whether or not an SMI was caused by a trapped I O or memory access to User Defined Device 2 F0 Index C4h 0 No 1 Yes To enable SMI generation set F0 Index 82h 5 1...

Page 241: ...18h 8 to 1 default 0 SMI_CMD SMI Status Indicates whether or not an SMI was caused by a write to the ACPI SMI_CMD register F1BAR1 I O Offset 06h 0 No 1 Yes A write to the ACPI SMI_CMD register always...

Page 242: ...was caused by assertion of EXT_SMI7 0 No 1 Yes To enable SMI generation set bit 7 to 1 22 EXT_SMI6 SMI Status Read to Clear Indicates whether or not an SMI was caused by an assertion of EXT_SMI6 0 No...

Page 243: ...tion of EXT_SMI2 0 No 1 Yes To enable SMI generation set bit 2 to 1 9 EXT_SMI1 SMI Status Read Only Indicates whether or not an SMI was caused by an assertion of EXT_SMI1 0 No 1 Yes To enable SMI gene...

Page 244: ...status is reported at bits 18 RC and 10 RO 1 EXT_SMI1 SMI Enable When this bit is asserted allow EXT_SMI1 to generate an SMI on negative edge events 0 Disable 1 Enable Top level SMI status is reported...

Page 245: ...r an SMI any SMI to be generated and serviced before transfer into C3 power state A read of this register causes an SMI if enabled F1BAR1 I O Offset 18h 11 1 default Top level SMI status is reported a...

Page 246: ...generation is always enabled Write 1 to clear 10 RTC_STS Real Time Clock Status Indicates if a Power Management Event PME was caused by the RTC generating an alarm RTC IRQ signal is asserted 0 No 1 Y...

Page 247: ...on when the RTC generates an alarm RTC IRQ signal is asserted 0 Disable 1 Enable 9 Reserved Must be set to 0 8 PWRBTN_EN Power Button Enable Allow SCI generation when PWRBTN goes low while the system...

Page 248: ...ported at F1BAR0 I O Offset 00h 02h 0 1 ACPI Mode generates an SCI if the corresponding PME enable bit is set and status is reported at F1BAR1 I O Offset 08h and 10h Note This bit enables the ACPI sta...

Page 249: ...activity on GPWIO0 0 No 1 Yes Write 1 to clear For the PME to generate an SCI 1 Ensure that GPWIO0 is enabled as an input F1BAR1 I O Offset 15h 0 0 2 Set F1BAR1 I O Offset 12h 8 1 and F1BAR1 I O Offse...

Page 250: ...I the SCI_EN bit must also be set F1BAR1 I O Offset 0Ch 0 1 The SCIs enabled in this register are globally enabled by setting F1BAR1 I O Offset 0Ch 0 to 1 The status of the SCIs is reported in F1BAR1...

Page 251: ...served 6 GPWIO_SMIEN2 Allow GPWIO2 to generate an SMI 0 Disable Default 1 Enable A fixed high to low or low to high transition debounce period of 31 s exists in order for GPWIO2 to be recognized Bit 2...

Page 252: ...High See F1BAR1 I O Offset 07h 3 for debounce information 0 GPWIO0_DATA Reflects the level of GPWIO0 0 Low 1 High See F1BAR1 I O Offset 07h 3 for debounce information Offset 17h Reserved Reset Value...

Page 253: ...14 0011 IRQ3 0011 IRQ7 1011 IRQ11 1111 IRQ15 For more details see Section 6 2 6 3 Programmable Interrupt Controller on page 163 Offset 1Ch 1Fh PM_TMR ACPI Timer Register RO Reset Value xxxxxxxxh Note...

Page 254: ...ister RO Reset Value 0280h Index 08h Device Revision ID Register RO Reset Value 01h Index 09h 0Bh PCI Class Code Register RO Reset Value 010180h Index 0Ch PCI Cache Line Size Register RO Reset Value 0...

Page 255: ...me value 1 cycle If Index 44h 31 1 Format 1 Bits 31 0 allow independent timing control for both command and data Format 1 settings for a Fast PCI clock frequency of 33 3 MHz PIO Mode 0 9172D132h PIO M...

Page 256: ...MHz UltraDMA Mode 0 00921250h UltraDMA Mode 1 00911140h UltraDMA Mode 2 00911030h Settings for a Fast PCI clock frequency of 66 7 MHz UltraDMA Mode 0 009436A1h UltraDMA Mode 1 00933481h UltraDMA Mode...

Page 257: ...selected in F2 Index 44h 31 bit 31 of this register is defined as reserved Index 58h 5Bh Channel 1 Drive 1 PIO Register R W Reset Value 00009172h Channel 1 Drive 1 Programmed I O Control Register See...

Page 258: ...ansferred from the drive is dis carded This bit should be reset after completion of data transfer Offset 01h Not Used Offset 02h IDE Bus Master 0 Status Register Primary R W Reset Value 00h 7 Simplex...

Page 259: ...W Reset Value 00h 7 Reserved Read Only 6 Drive 1 DMA Capable Allow Drive 1 to perform DMA transfers 0 Disable 1 Enable 5 Drive 0 DMA Capable Allow Drive 0 to perform DMA transfers 0 Disable 1 Enable 4...

Page 260: ...ble 1 Enable This bit must be enabled to access memory offsets through F3BAR0 See F3 Index 10h 0 Reserved Read Only Index 06h 07h PCI Status Register RO Reset Value 0280h Index 08h Device Revision ID...

Page 261: ...7h Codec GPIO Control Register R W Reset Value 00000000h 31 20 Reserved Must be set to 0 19 0 Codec GPIO Pin Data This field indicates the GPIO pin data that is sent to the codec in slot 12 on the SDA...

Page 262: ...el Audio SMI Status Register RC Reset Value 0000h The bits in this register contain second level SMI status reporting Top level is reported at F1BAR0 I O Offset 00h 02h 1 Reading this register clears...

Page 263: ...0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 12h 13h Second Level Audio SMI Status Mirror Register RO Reset Value 0000h Note The bits in this reg...

Page 264: ...if an SMI was caused by an I O trap 0 No 1 Yes The next level third level of SMI status reporting is at F3BAR0 Memory Offset 14h Offset 14h 17h I O Trap SMI and Fast Write Status Register RO RC Reset...

Page 265: ...BAR0 I O Offset 00h 02h 1 SMI generation enabling is at F3BAR0 Memory Offset 18h 2 9 0 X Bus Address Read Only This bit field contains the captured ten bits of X Bus address Offset 18h 19h I O Trap SM...

Page 266: ...dress ranges selected by bits 1 0 an SMI is generated 0 Disable 1 Enable Top level SMI status is reported at F1BAR0 I O Offset 00h 02h 1 Second level SMI status is reported at F3BAR0 Memory Offset 10h...

Page 267: ...rnal 1 Internal 0 Reserved Must be set to 0 Offset 1Ch 1Fh Internal IRQ Control Register R W Reset Value 00000000h Note Bits 31 16 of this register are Write Only Reads to these bits always return a v...

Page 268: ...al IRQ14 0 Disable 1 Enable 13 Reserved Set to 0 12 Assert Masked Internal IRQ12 0 Disable 1 Enable 11 Assert masked internal IRQ11 0 Disable 1 Enable 10 Assert Masked Internal IRQ10 0 Disable 1 Enabl...

Page 269: ...aster Error Indicates if hardware encountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it cau...

Page 270: ...ountered a second EOP before software has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until thi...

Page 271: ...ware has cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software has cleared the first it causes the bus master to pause until this register is read to clear the e...

Page 272: ...OP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until this register is read to clear...

Page 273: ...if hardware encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause un...

Page 274: ...encountered a second EOP before software cleared the first 0 No 1 Yes If hardware encounters a second EOP end of page before software cleared the first it causes the bus master to pause until this re...

Page 275: ...defined as allowing access to I O mapped registers this bit must be set to 1 BAR configuration is programmed through the corre sponding mask register see F5 Index 40h 44h 48h 4Ch 50h and 54h Index 06h...

Page 276: ...ddress Mask Determines the size of the BAR Every bit that is a 1 is programmable in the BAR Every bit that is a 0 is fixed 0 in the BAR Since the address mask goes down to bit 4 the smallest memory re...

Page 277: ...he accessed offset registers are memory or I O mapped See F5 Index 40h F5BAR0 Mask Address Register above for bit descriptions Note Whenever a value is written to this mask register F5BAR5 must also b...

Page 278: ...C0007h 31 28 Reserved 27 IO_ENABLE_SIO_IR Enable Integrated SIO Infrared 0 Disable 1 Enable 26 25 IO_SIOCFG_IN Integrated SIO Input Configuration These two bits can be used to disable the integrated S...

Page 279: ...L AD26 for Chipset Register Space F0 F5 AD27 for USB Register Space PCIUSB Offset 08h 0Bh I O Control Register 3 R W Reset Value 00009000h 31 16 Reserved Write as read 15 13 IO_USB_XCVR_VADJ USB Volta...

Page 280: ...ice Identification Register RO Reset Value A0F8h Index 04h 05h Command Register R W Reset Value 00h 15 10 Reserved Must be set to 0 9 Fast Back to Back Enable Read Only USB only acts as a master to a...

Page 281: ...le acting as PCI master whether or not PERR was driven by USB 7 Fast Back to Back Capable The USB supports fast back to back transactions when the transactions are not to the same agent This bit is al...

Page 282: ...egister is used by device drivers and has no direct meaning to USB Index 3Dh Interrupt Pin Register R W Reset Value 01h This register selects which interrupt pin the device uses USB uses INTA after re...

Page 283: ...so Interrupt EDs may be serviced While processing the Periodic List the HC will check this bit when it finds an isochronous ED 2 PeriodicListEnable When set this bit enables processing of the Periodi...

Page 284: ...hangeEnable 0 Ignore 1 Enable interrupt generation due to Ownership Change 29 7 Reserved Read Write 0s 6 RootHubStatusChangeEnable 0 Ignore 1 Enable interrupt generation due to Root Hub Status Change...

Page 285: ...HcHCCA Register R W Reset Value 00000000h 31 8 HCCA Pointer to HCCA base address 7 0 Reserved Read Write 0s Offset 1Ch 1Fh HcPeriodCurrentED Register R W Reset Value 00000000h 31 4 PeriodCurrentED Poi...

Page 286: ...e where in a frame the Periodic List pro cessing must begin Offset 44h 47h HcLSThreshold Register R W Reset Value 00000628h 31 12 Reserved Read Write 0s 11 0 LSThreshold This field contains a value us...

Page 287: ...RST It is written during system initialization to configure the Root Hub These bit should not be written during normal operation Offset 50h 53h HcRhStatus Register R W Reset Value 00000000h 31 ClearRe...

Page 288: ...viceAttached This bit defines the speed and bud idle of the attached device It is only valid when CurrentConnectStatus is set 0 Full Speed device 1 Low Speed device Write ClearPortPower Writing a 1 cl...

Page 289: ...s that the port has been disabled due to a hardware event cleared PortEna bleStatus 0 Port has not been disabled 1 PortEnableStatus has been cleared 16 ConnectStatusChange This bit indicates a connect...

Page 290: ...21 Reserved Read Write 0s 20 PortResetStatusChange This bit indicates that the port reset signal has completed 0 Port reset is not complete 1 Port reset is complete 19 PortOverCurrentIndicatorChange...

Page 291: ...emovable this bit is always 1 Write ClearPortEnable Writing 1 a clears PortEnableStatus Writing a 0 has no effect Note This register is reset by the UsbReset state Offset 60h 9Fh Reserved Reset Value...

Page 292: ...Ch 10Fh HceStatus Register R W Reset Value 00000000h 31 8 Reserved Read Write 0s 7 Parity Indicates parity error on keyboard mouse data 6 Timeout Used to indicate a timeout 5 AuxOutputFull IRQ12 is as...

Page 293: ...6 43 DMA Channel Control Registers Bit Description I O Port 000h DMA Channel 0 Address Register R W Written as two successive bytes byte 0 1 I O Port 001h DMA Channel 0 Transfer Count Register R W Wr...

Page 294: ...write 1 Extended write 4 Priority Mode 0 Fixed 1 Rotating 3 Timing Mode 0 Normal 1 Compressed 2 Channels 3 0 0 Disable 1 Enable 1 0 Reserved Must be set to 0 I O Port 009h Software DMA Request Registe...

Page 295: ...A Master Clear Command Channels 3 0 W I O Port 00Eh DMA Clear Mask Register Command Channels 3 0 W I O Port 00Fh DMA Write Mask Register Command Channels 3 0 W I O Port 0C0h DMA Channel 4 Address Regi...

Page 296: ...Terminal Count Indicates if TC was reached 0 No 1 Yes 2 Channel 6 Terminal Count Indicates if TC was reached 0 No 1 Yes 1 Channel 5 Terminal Count Indicates if TC was reached 0 No 1 Yes 0 Undefined Wr...

Page 297: ...hannels 7 4 WO Note Channels 5 6 and 7 are not supported 7 6 Transfer Mode 00 Demand 01 Single 10 Block 11 Cascade 5 Address Direction 0 Increment 1 Decrement 4 Auto initialize 0 Disabled 1 Enable 3 2...

Page 298: ...age Register R W Not supported I O Port 08Bh DMA Channel 5 Low Page Register R W Not supported I O Port 08Fh ISA Refresh Low Page Register R W Refresh address I O Port 481h DMA Channel 2 High Page Reg...

Page 299: ...Write Mode 00 Counter latch command 01 R W LSB only 10 R W MSB only 11 R W LSB followed by MSB 3 1 Current Counter Mode 0 5 0 BCD Mode 0 Binary 1 BCD Binary Coded Decimal I O Port 041h Write PIT Timer...

Page 300: ...I O Port 043h R W PIT Mode Control Word Register Notes 1 If bits 7 6 11 Register functions as Read Status Command and Bit 5 Latch Count Bit 4 Latch Status Bit 3 Select Counter 2 Bit 2 Select Counter...

Page 301: ...or base vector for interrupt controller 2 0 Reserved Must be set to 0 I O Port 021h 0A1h Master Slave PIC ICW3 after ICW2 is written WO Master PIC ICW3 7 0 Cascade IRQ Must be 04h Slave PIC ICW3 7 0 S...

Page 302: ...ve PIC OCW3 WO 7 Reserved Must be set to 0 6 5 Special Mask Mode 00 No operation 01 No operation 10 Reset Special Mask Mode 11 Set Special Mask Mode 4 Reserved Must be set to 0 3 Reserved Must be set...

Page 303: ...ding 0 Yes 1 No Interrupt Service Register 7 IRQ7 IRQ15 In Service 0 No 1 Yes 6 IRQ6 IRQ14 In Service 0 No 1 Yes 5 IRQ5 IRQ13 In Service 0 No 1 Yes 4 IRQ4 IRQ12 In Service 0 No 1 Yes 3 IRQ3 IRQ11 In S...

Page 304: ...O device to report an error Note that NMI is under SMI control 1 Ignores the IOCHK input signal and does not generate NMI 2 PERR SERR Enable Generate an NMI if PERR SERR is driven active to report an...

Page 305: ...49 Miscellaneous Registers Bit Description I O Port 0F0h 0F1h Coprocessor Error Register W Reset Value F0h A write to either port when the internal FERR signal is asserted causes the Core Logic Module...

Page 306: ...sitive shared 7 IRQ15 Edge or Level Sensitive Select Selects PIC IRQ15 sensitivity configuration 0 Edge 1 Level 6 IRQ14 Edge or Level Sensitive Select Selects PIC IRQ14 sensitivity configuration 0 Edg...

Page 307: ...phics Video Overlay and Blending Overlay of video up to 16 bpp Supports chroma key and color key for both graphics and video streams Supports alpha blending with up to three alpha windows that can ove...

Page 308: ...ce Horizontal vertical scalers Filters Mixer Blender Overlay with color chroma key Gamma correction Color space converters Alpha blender Outputs CRT interface with DACs TFT interface Dot Clock PLL The...

Page 309: ...e In this mode the data never leaves the Video Processor module Direct Video mode can only be used under very specific condi tions which will be explained later If the VIP data is less than full frame...

Page 310: ...l Lines 2 3 Scan Lines 2 3 VSYNC Start VBI_Total_Count_Odd VBI_Line_Offset_Odd Not normally User Data Nominal VBI Lines Not normally User Data Not normally User Data VSYNC End Vertical Retrace Logical...

Page 311: ...ed out using the GX1 s Video port clock 75 116 or 133 MHz GX1 core clock divided by 2 or 4 7 2 1 1 Direct Video Mode As stated previously Direct Video mode is on by default so no registers need to be...

Page 312: ...eo Processor per a given amount of time therefore reducing the memory bandwidth requirement The disad vantage is that there are some observable visual effects due to the reduction in resolution Figure...

Page 313: ...ta is stored in the GX1 module s frame buffer F4BAR2 Memory Offset 20h Video Data Odd Base Address F4BAR2 Memory Offset 24h Video Data Even Base Address F4BAR2 Memory Offset 28h Video Data Pitch The V...

Page 314: ...ne or more of the VBI lines or have an application decode the Closed Captioning information put in the graphics frame buffer The registers F4BAR2 Memory Offset 40h 44h and 48h tell the bus master the...

Page 315: ...5 For this format each pixel is described as a 16 bit value Bits 15 11 Red Bits 10 5 Green Bits 4 0 Blue YUV 4 2 0 This format is not supported by the GX1 mod ule The Horizontal Downscaler in the Vide...

Page 316: ...video window by a factor of up to 8 1 in 1 pixel increments The downscaler factor m is programmed in the Video Downscaler Control register F4BAR0 Memory Offset 3Ch 4 1 If bit 0 of this register is se...

Page 317: ...scalers After the video data has been buffered the upscaling algo rithm can be applied The Video Processor employs a Digi tal Differential Analyzer style DDA algorithm for both horizontal and vertical...

Page 318: ...s data which is RGB The video data can be in progressive or interlaced format while the graphics data is always in the progressive format The Mixer Blender can mix blend either format of video data wi...

Page 319: ...use F4BAR0 Memory Offset 1Ch and 20h 7 2 3 3 Color Chroma Key A color chroma key mechanism is used to support the Mixer Blender logic There are two keys key1 is for the cursor and key2 is for graphic...

Page 320: ...ce is from the GX1 module s video frame buffer which includes Capture Video mode see Section 7 2 1 2 Capture Video Mode on page 324 then the video data can be scaled both horizontally and verti cally...

Page 321: ...ta Match Normal Color Key Video Data Match Normal Color Key Mixer Output x x x Yes x x Cursor Color x Not in Video Window x No x x Graphics Data Graphics Color Key COLOR_ CHROMA_SEL 0 Not in an Alpha...

Page 322: ...Yes Replace the value with the color register value Yes Start Notes 1 Alpha window should not be placed outside of the video window 2 Graphics inside Video is enabled via bit GFX_INS_VIDEO in the Vid...

Page 323: ...bit video DACs The integrated DACs drive the RED GREEN and BLUE inputs of the CRT Each integrated DAC is an 8 bit current output type which can run at a clock rate of up to 135 MHz The integrated DAC...

Page 324: ...ls TFTD 11 6 for green signals TFTD 17 12 for red signals HSYNC and VSYNC sync signals TFTDCK data clock signal TFTDE data enable signal FP_VDD_ON power control signal Power Sequence Power sequence is...

Page 325: ...n integrated oscillator FOUT is calculated from FOUT m 1 n 1 x FREF The integrated PLL can generate any frequency by writing into the CRT m and CRT n bit fields FBAR0 Memory Off set 2Ch Additionally 1...

Page 326: ...Register 0 F4BAR0 Sets the base address for the memory mapped Video Configuration Registers within the Video Processor Refer to Table 7 7 on page 343 for programming infor mation regarding the regist...

Page 327: ...Fh 32 R W Alpha Window 1 Control Register 00000000h Page 353 70h 73h 32 R W Alpha Window 2 X Position Register 00000000h Page 353 74h 77h 32 R W Alpha Window 2 Y Position Register 00000000h Page 353 7...

Page 328: ...Reserved 00000000h Page 362 10h 13h 32 RO Video Current Line Register xxxxxxxxh Page 362 14h 17h 32 R W Video Line Target Register 00000000h Page 362 18h 1Fh Reserved 00000000h Page 362 20h 23h 32 R...

Page 329: ...ndex 0Ch PCI Cache Line Size Register RO Reset Value 00h Index 0Dh PCI Latency Timer Register RO Reset Value 00h Index 0Eh PCI Header Type RO Reset Value 00h Index 0Fh PCI BIST Register RO Reset Value...

Page 330: ...upt Pin Register R W Reset Value 03h This register selects which interrupt pin the device uses VIP uses INTC after reset INTA INTB or INTD can be selected by writing 1 2 or 4 respectively Index 3Eh FF...

Page 331: ...e left edge of the active display It represents the DWORD address of the source pixel which is to be displayed first For an unclipped window this value should be 0 For 4 2 0 format set bits 17 16 to 0...

Page 332: ...ata Selects whether the graphics or video data goes to the Gamma Correction RAM GAMMA_EN F4BAR0 Memory Offset 28h 0 must be enabled for the selected data source to pass through the Gamma Correction RA...

Page 333: ...register is programmed relative to CRT horizontal sync input not physical screen position Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller Timing registers GX_B...

Page 334: ...8192 but the formula above fits a given source number of pixels into a destination win dow size Offset 14h 17h Video Color Key Register R W Reset Value 00000000h Provides the video color key The colo...

Page 335: ...riod This effect should go unnoticed during normal operation 7 0 Reserved Offset 24h 27h Reserved Offset 28h 2Bh Miscellaneous Register R W Reset Value 00001400h Configuration and control register for...

Page 336: ...ownscale Type Select 0 Type A Downscale formula is 1 m 1 m pixels are dropped 1 pixel is kept 1 Type B Downscale formula is m m 1 m pixels are kept 1 pixel is dropped 5 Reserved 4 1 DFS Downscale Fact...

Page 337: ...ermine the CRC check status SIGN_EN can then be reset to initialize the SIG_VALUE as an essential preparation for the next round of CRC check Offset 48h 4Bh Device and Revision Identification RO Reset...

Page 338: ...works in conjunction with bit COLOR_CHROMA_SEL F4BAR0 Mem ory Offset 4Ch 20 COLOR_CHROMA_SEL selects whether the graphics is used for color keying or the video data stream is used for chroma keying If...

Page 339: ...ters GX_BASE Memory Offset 8330h 26 19 and 8338h 10 3 respectively The value of H_TOTAL H_SYNC_END is some times referred to as horizontal back porch For more information see the GX1 Processor Series...

Page 340: ...Value 00000000h Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller Timing registers GX_BASE Memory Offset 8330h 26 19 and 8338h 10 3 respectively The value of H_...

Page 341: ...Reset Value 00000000h Note H_TOTAL and H_SYNC_END are values programmed in the GX1 module s Display Controller Timing registers GX_BASE Memory Offset 8330h 26 19 and 8338h 10 3 respectively The value...

Page 342: ...ent or decrement When this value reaches either the maximum or the minimum alpha value 255 or 0 it keeps that value i e it is not incremented decremented until it is reloaded via bit 17 LOAD_ALPHA 7 0...

Page 343: ...bit can be reset by writing 1 to it 21 9 Reserved 8 Reserved Set to 0 7 Reserved Set to 0 6 Reserved Set to 0 5 Reserved Set to 0 4 GENLOCK_TOUT_EN GenLock Timeout Enable 0 Disable 1 Enable timeout 3...

Page 344: ...ction 4 32580B Offset 43Ch 43Fh Continuous GenLock Timeout Register R W Reset Value 1FFF1FFFh 31 16 CGENTO1 Even Field Continuous GenLock Timeout 15 0 CGENTO0 Odd Field Continuous GenLock Timeout Tabl...

Page 345: ...ride 1 enabled 18 VBI Configuration Override When this bit is enabled bits 21 19 override the setup specified in bits 17 and 16 0 Disable 1 Enable 17 VBI Data Task Specifies the CCIR656 video stream t...

Page 346: ...at beginning of next field Offset 08h 0Bh Video Interface Status Register R W Reset Value xxxxxxxxh 31 25 Reserved Read Only 24 Current Field Read Only 0 Even field is being processed 1 Odd field is...

Page 347: ...luding this one are written to the appropriate base registers and the Base Register Not Updated bit is cleared 31 0 Video Odd Base Address Base address where odd video data are stored in graphics memo...

Page 348: ...cs memory where VBI data for even fields is stored Changes to this register take effect at the beginning of the next field The value in this register is 16 byte aligned Note This register is double bu...

Page 349: ...Support The TAP supports the following IEEE optional instructions IDCODE Presents the contents of the Device Identification register in serial format CLAMP Ensures that the Bypass register is connect...

Page 350: ...366 AMD Geode SC2200 Processor Data Book Debugging and Monitoring 32580B...

Page 351: ...e Table 9 2 on page 369 may cause permanent damage to the SC2200 reduce device reliability and result in premature failure even when there is no immediately apparent sign of failure Prolonged exposure...

Page 352: ...Note 1 Note 1 For VIH Input High Voltage VIL Input Low Voltage IOH Output High Current and IOL Output Low Current op erating conditions refer to Section 9 2 DC Characteristics on page 379 Parameter Mi...

Page 353: ...s is equivalent to the ACPI spec ification s S1 state 9 1 5 2 Definition and Measurement Techniques of SC2200 Current Parameters These parameters describe the current while the SC2200 is in the On sta...

Page 354: ...inal 50 MHz Note 2 Nominal Absolute Maximum Max Max 135 MHz Note 3 Max Note 1 See Table 9 3 on page 370 for nominal and maximum voltages Note 2 A DCLK frequency of 50 MHz is derived by setting the dis...

Page 355: ...CORE fCLK 266 MHz Core Current VCORE 1 8V Nominal CPU state Active Idle 380 fCLK 300 MHz Core Current VCORE 2 1V Nominal CPU state Active Idle 470 ICORESLP Core Current VCORE 1 8V Nominal CPU state Sl...

Page 356: ...s Table 9 8 Ball Capacitance and Inductance Symbol Parameter Min Typ Max Unit Comment CIN Input Pin Capacitance 4 7 pF Note 1 CIN Clock Input Capacitance 5 8 12 pF Note 1 CIO I O Pin Capacitance 10 12...

Page 357: ...T_PRSNT P29 PD 100K LPC_ROM D6 PD 100K FPCI_MON A4 PD 100K DID 1 0 C6 C5 PD 100K ACCESS bus Note 2 AB1C N31 PU 22 5K AB1D N30 PU 22 5K AB2C N29 PU 22 5K AB2D M29 PU 22 5K Parallel Port AFD DSTRB D22 P...

Page 358: ...Input PCI compatible Section 9 2 3 INSTRP Input Strap ball min VIH is 0 6VIO with weak pull down Section 9 2 4 INT Input TTL compatible Section 9 2 5 INTS Input TTL compatible with Schmitt Trigger typ...

Page 359: ...1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 5 A VIN VSB 36 A VIN VSS VHIS Input HysteresisNote 1 250 mV Note 1 Not 100 tested Symbol Parameter Min Max Unit Comments VIH Input...

Page 360: ...t Comments VIH Input High Voltage 2 0 VIO 0 3 Note 1 V VIL Input Low Voltage 0 5 Note 1 0 8 V IIL Input Leakage Current 10 A VIN VIO 10 A VIN VSS Note 1 Not 100 tested Symbol Parameter Min Max Unit Co...

Page 361: ...0 A VIN VIO 10 A VIN VSS VDI Differential Input Sensitivity 0 2 V D D and Figure 9 1 VCM Differential Common Mode Range 0 8 2 5 V Includes VDI Range VSE Single Ended Receiver Threshold 0 8 2 0 V Note...

Page 362: ...Unit Comments VOL Output Low Voltage 0 1VIO V lOL 1500 A Symbol Parameter Min Max Unit Comments VOH Output High Voltage 2 4 V lOH p mA VOL Output Low Voltage 0 4 V lOL n mA Symbol Parameter Min Max U...

Page 363: ...form to these default levels All AC tests are at VIO 3 14V to 3 46V 3 3V nominal TC 0 oC to 85 oC CL 50 pF unless otherwise specified Figure 9 2 General Drive level and Measurement Points Table 9 11 D...

Page 364: ...le sampling window during which a synchronous input signal must be stable to ensure correct operation Figure 9 3 Drive Level and Measurement Points SDCLK_OUT VOH VREF VREF VREF C Valid Output n 1 A B...

Page 365: ...t9 SDCLK_IN fall rise time between VILD VIHD 2 ns t10 SDCLK 3 0 SDCLK_OUT high time 233 MHz 4 0 ns 266 MHz 3 0 300 MHz 2 5 t11 SDCLK 3 0 SDCLK_OUT low time 233 MHz 4 0 ns 266 MHz 2 5 300 MHz 2 5 Note...

Page 366: ...4 Memory Controller Output Valid Timing Diagram Figure 9 5 Read Data In Setup and Hold Timing Diagram SDCLK 3 0 Control Output MA 12 0 BA 1 0 MD 63 0 t1 t2 t3 t6 t7 t7 VREF VOHD VOLD VREF t10 t11 SDC...

Page 367: ...rs Symbol Parameter Min Max Unit Comments tVP_C VPCKIN cycle time 18 ns tVP_S Video Port input setup time before VPCKIN rising edge 6 ns tVP_H Video Port input hold time after VPCKIN Rising edge 0 ns...

Page 368: ...SS bus timing and are controlled by software Figure 9 7 TFT Timing Diagram Table 9 14 TFT Timing Parameters Symbol Parameter Min Max Unit Comments tOV TFTD 17 0 TFTDE valid time after TFTDCK rising ed...

Page 369: ...ax output capacitance 15 pF PSRR Power supply rejection ratioNote 6 3 5 At 0 to 1 MHz Note 1 Black level Blank level 0 mA 0V Note 2 The maximum difference between the ideal straight conversion line an...

Page 370: ...B2C falling edge tSCLhighi AB1C AB2C high time 16 tCLK After AB1C AB2C rising edge tSDAfi AB1D AB2D fall time 300 ns tSDAri AB1D AB2D rise time 1 s tSDAhi AB1D AB2D hold time 0 After AB1C AB2C falling...

Page 371: ...AB1D AB2D valid time 7 tCLK tRD After AB1C AB2C falling edge Note 1 K is determined by bits 7 1 of the ACBCTL2 register LDN 05h 06h Offset 05h Note 2 tSCLhigho value depends on the signal capacitance...

Page 372: ...0B Figure 9 10 ACB Start Condition Timing Diagram Figure 9 11 ACB Data Bit Timing Diagram tCSTRsi tDHCsi Start Condition tCSTRhi AB1D AB1C tCSTRho tCSTRso tDHCso AB2D AB2C tSCLhigho tSCLlowo tSDAho tS...

Page 373: ...OUT 0 1VIO Equation B Figure 9 13 0 18VIO VOUT 0 Test point Note 2 38VIO mA VOUT 0 18VIO ICL Low clamp current 25 VIN 1 0 015 mA 3 VIN 1 ICH High clamp current 25 VIN VIO 1 0 015 mA VIO 4 VIN VIO 1 SL...

Page 374: ...n Test Point VIO 0 9 VIO DC Drive Point AC Drive Point 0 3 VIO 0 6 VIO 0 1 AC Drive Point DC Drive Point Test Point VIO Equation A for VIO VOUT 0 7VIO IOL 256 VIO VOUT VIO VOUT for 0V VOUT 0 18VIO Vol...

Page 375: ...Rate 50 mV ns Note 4 Note 1 Clock frequency is between nominal DC and 33 MHz Device operational parameters at frequencies under 16 MHz are not 100 tested The clock can only be stopped in a low state N...

Page 376: ...1 ms Note 3 Note 5 tRST CLK PCIRST active time after PCICLK stable 100 s Note 3 Note 5 tRST OFF PCIRST active to output float delay 40 ns Note 3 Note 5 Note 6 Note 1 See the timing measurement conditi...

Page 377: ...VTL 0 2 VIO V Note 1 VTEST 0 4 VIO V VSTEP rising edge 0 285 VIO V VSTEP falling edge 0 615 VIO V VMAX 0 4 VIO V Note 2 Input signal edge rate 1 V ns Note 1 The input test is performed with 0 1 VIO o...

Page 378: ...ditions Figure 9 18 PCI Reset Timing VTEST VTEST Input Valid tSU tH VTEST VMAX VTH VTL PCICLK Input VTH VTL 100 ms typ tRST tRST CLK tRST OFF TRI_STATE PCI Signals PCIRST PCICLK POWER POR tFAIL VIO No...

Page 379: ...to RE 8 M I O 160 9 19 Zero wait state tRCU1 MEMR DOCR RD TRDE inactive pulse width 16 M 103 9 19 tRCU2 MEMR DOCR RD TRDE inactive pulse width 8 M 163 9 19 tRCU3 IOR RD TRDE inactive pulse width 8 16...

Page 380: ...M I O 0 9 19 tHZ Read data floating after MEMR DOCR IOR inactive 8 16 M I O 41 9 19 tAW1 A 23 0 BHE valid before MEMW DOCW active 16 M 34 9 20 tAW2 A 23 0 BHE valid before IOW active 16 I O 100 9 20 t...

Page 381: ...b ISA Read Operation Timing Diagram tRDx tARx Valid Valid Valid Data tRCUx tRA tRVDS tRDH tHZ A 23 0 BHE D 15 0 tRDYAx tRDYH MEMW DOCW ROMCS DOCCS IOW WR IOCS 1 0 Read tIOCSA tIOCSH tWDAR D 15 0 Write...

Page 382: ...re 9 20 Sub ISA Write Operation Timing Diagram tWRx tAWx Valid Valid Valid Data tWCUx tWA tDH A 23 0 BHE TRDE D 15 0 IOCHRDY tRDYAx tRDYH DOCCS ROMCS tIOCSH IOCS 1 0 tDF tDVx tIOCSA IOW WR MEMW DOCW I...

Page 383: ...ameters Symbol Parameter Min Max Unit Comments tVAL Output Valid delay 0 17 ns After PCICLK rising edge tON Float to Active delay 2 ns After PCICLK rising edge tOFF Active to Float delay 28 ns After P...

Page 384: ...23 IDE Reset Timing Diagram Table 9 24 IDE General Timing Parameters Symbol Parameter Min Max Unit Comments tIDE_FALL IDE signals fall time from 0 9VIO to 0 1VIO 5 ns CL 40 pF tIDE_RISE IDE signals r...

Page 385: ...5 5 5 5 ns Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the sum o...

Page 386: ...tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Device keeps IDE_IORDY 0 1 released and no wait is generated 4 Device negates IDE_IORDY 0 1 before tA but cause...

Page 387: ...s Note 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recov ery time or command inactive time The actual cycle time equals the sum of the com...

Page 388: ...d is made by the host after tA from the assertion of IDE_IOR 0 1 or IDE_IOW 0 1 3 Device never negates IDE_IORDY 0 1 Devices keep IDE_IORDY 0 1 released and no wait is generated 4 Device negates IDE_I...

Page 389: ...d pulse width min 215 50 25 ns tLR IDE_IOR 0 1 to IDE_DREQ 0 1 delay max 120 40 35 ns tLW IDE_IOW 0 1 to IDE_DREQ0 1 delay max 40 40 35 ns tM IDE_CS 0 1 valid to IDE_IOR 0 1 IDE_IOW 0 1 min 50 30 25 n...

Page 390: ...DE_IOW0 Notes 1 For Multiword DMA transfers the Device may negate IDE_DREQ 0 1 within the tL specified time once IDE_DACK 0 1 is asserted and reassert it again at a later time to resume the DMA operat...

Page 391: ...d 10 10 10 ns tZAH Minimum delay time required for output driv ers to assert or negate from released state 20 20 20 ns tZAD 0 0 0 ns tENV Envelope time from IDE_DACK 0 1 to IDE_IOW 0 1 STOP 0 1 and ID...

Page 392: ...nts are taken at the connector of the sender Figure 9 27 Initiating an UltraDMA Data in Burst Timing Diagram tUI tACK tENV tFS tFS tZAD tACK tZIORDY tAZ tACK tDVS tDVH tENV tZAD IDE_DATA 15 0 IDE_ADDR...

Page 393: ...IDE_DATA 15 0 at device IDE_DATA 15 0 at host IDE_IRDY0 DSTROBE0 at device IDE_IRDY0 DSTROBE0 at host Note IDE_DATA 15 0 and IDE_IRDY 0 1 DSTROBE 0 1 signals are shown at both the host and the device...

Page 394: ...tSR IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Notes 1 The host can assert IDE_IOW 0 1 STOP 0 1 to request termination of the UltraDMA burst...

Page 395: ...0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tZAH tAZ tSS tLI tACK tIORDZ tACK tMLI tLI tLI IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The definiti...

Page 396: ...DE_ADDR 2 0 CR tACK tDVH tDVS tACK tIORDYZ tACK tMLI tLI tRP tMLI tLI tRFS tAZ tZAH IDE_IRDY0 DSTROBE0 device IDE_IOR0 HDMARDY0 host IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The defini...

Page 397: ...IDE_CS 0 1 IDE_ADDR 2 0 tUI tACK tENV tLI tUI tZIORDY tACK tDVS tDVH tACK IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device IDE_IOR0 HSTROBE0 host Note The definitions for...

Page 398: ...C IDE_DATA 15 0 at host IDE_DATA 15 0 at device IDE_IOR0 HSTROBE0 at host IDE_IOR0 HSTROBE0 at device Note IDE_DATA 15 0 and IDE_IOR 0 1 HSTROBE 0 1 signals are shown at both the device and the host t...

Page 399: ...S tSR IDE_IOR0 HSTROBE0 host IDE_DACK0 host IDE_DREQ0 device IDE_IOW0 STOP0 host IDE_IORDY0 DDMARDY0 device Notes 1 The device can de assert IDE_DREQ 0 1 to request termination of the UltraDMA burst n...

Page 400: ...0 1 IDE_ADDR 2 0 CR tLI tMLI tACK tLI tSS tLI tACK tDVH tDVS tACK tIORDYZ IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_IOW0 STOP0 host IDE_DACK0 host IDE_DREQ0 device Note The definitions fo...

Page 401: ...0 1 IDE_ADDR 2 0 CR tACK tDVH tDVS tRFS tACK tIORDZ tACK tMLI tLI tRP tMLI tLI IDE_IOR0 HSTROBE0 host IDE_IORDY0 DDMARDY0 device IDE_DREQ0 device IDE_DACK0 host IDE_IOW0 STOP0 host Note The definition...

Page 402: ...OP width 160 175 ns 9 38 Note 4 Note 5 tUSB_DE1 Differential to EOP transition skew 2 5 ns 9 39 Note 4 Note 5 tUSB_RJ11 Receiver data jitter tolerance for con secutive transition 18 5 18 5 ns 9 40 Not...

Page 403: ...stream Note 4 tUSB_RJU22 Receiver data jitter tolerance for paired transactions 45 45 ns 9 40 Function downstream Note 4 Low Speed Receiver EOP Width Note 5 tUSB_RE21 Must reject as EOP 330 ns 9 38 tU...

Page 404: ...10 10 Differential Data Lines CL CL Full Speed 4 to 20 ns at CL 50 pF Low Speed 75 ns at CL 50 pF 300 ns at CL 350 pF tperiod_F Paired Transitions Consecutive Transitions Differential Data Lines Cross...

Page 405: ...rential Data to SE0 Skew N tperiod_F tUSB_DE1 N tperiod_L tUSB_DE2 tUSB_SE1 tUSB_SE2 tUSB_RE11 tUSB_RE12 tUSB_RE21 tUSB_RE22 Source Receiver tperiod_F Paired Transitions Consecutive Transitions Differ...

Page 406: ...tter 2 0 Receiver tSJT SIR leading edge jitter of nominal bit duration 2 5 Transmitter 6 5 Receiver Note 1 tBTN is the nominal bit time in UART Sharp IR SIR and Consumer Remote Control modes It is det...

Page 407: ...toler ance 0 1 tMJT MIR receiver edge jitter of nominal bit duration 2 9 tFPW FIR signal pulse width 120 130 ns Transmitter 90 160 ns Receiver tFDPW FIR signal double pulse width 245 255 ns Transmitte...

Page 408: ...Port Typical Data Exchange Timing Diagram Table 9 32 Standard Parallel Port Timing Parameters Symbol Parameter Min Typ Max Unit Comments tPDH Port data hold 500 ns Note 1 tPDS Port data setup 500 ns...

Page 409: ...AIT low 45 x ns tWW19ia WRITE inactive from WAIT low 45 x ns tWST19a DSTRB or ASTRB active from WAIT low 65 x ns tWEST DSTRB or ASTRB active after WRITE active 10 x x ns tWPDH PD 7 0 hold after WRITE...

Page 410: ...Mode Timing Parameters Symbol Parameter Min Max Unit Comments tECDSF Data setup before STB active 0 ns tECDHF Data hold after BUSY inactive 0 ns tECLHF BUSY active after STB active 75 ns tECHHF STB in...

Page 411: ...ters Symbol Parameter Min Max Unit Comments tECDSR Data setup before ACK active 0 ns tECDHR Data hold after AFD active 0 ns tECLHR AFD inactive after ACK active 75 ns tECHHR ACK inactive after AFD ina...

Page 412: ...eters Symbol Parameter Min Typ Max Unit Comments tRST_LOW AC97_RST active low pulse width 1 0 s tRST2CLK AC97_RST inactive to BIT_CLK startup delay 162 8 ns AC97_RST BIT_CLK tRST_LOW tRST2CLK Table 9...

Page 413: ...pulse width 32 56 40 7 48 84 ns Note 1 FSYNC SYNC frequency 48 0 KHz tSYNC_PD SYNC period 20 8 s tSYNC_H SYNC high pulse width 1 3 s tSYNC_L SYNC low pulse width 19 5 s FAC97_CLK AC97_CLK frequency 2...

Page 414: ...dge of BIT_CLK 15 0 ns tAC97_H Hold from falling edge of BIT_CLK 10 0 ns tAC97_OV SDATA_OUT or SYNC valid after rising edge of BIT_CLK 15 ns tAC97_OH SDATA_OUT or SYNC hold time after falling edge of...

Page 415: ...CLK rise time 2 6 ns tfallCLK BIT_CLK fall time 2 6 ns triseSYNC SYNC rise time 2 6 ns CL 50 pF tfallSYNC SYNC fall time 2 6 ns CL 50 pF triseDIN SDATA_IN rise time 2 6 ns tfallDIN SDATA_IN fall time...

Page 416: ...gure 9 52 AC97 Low Power Mode Timing Diagram Table 9 41 AC97 Low Power Mode Timing Parameters Symbol Parameter Min Typ Max Unit Comments ts2_pdown End of Slot 2 to BIT_CLK SDATA_IN low 1 0 s SYNC BIT_...

Page 417: ...Diagram Table 9 42 PWRBTN Timing Parameters Symbol Parameter Min Max Unit Comments tPBTNP PWRBTN pulse width 16 ms Note 1 tPBTNE Delay from PWRBTN events to ONCTL 14 16 ms Note 1 Not 100 tested PWRBTN...

Page 418: ...r VSBL applied whichever is applied last 0 1 s PWRBTN is an input and must be powered by VSB t3 PWRBTN active pulse width 16 4000 ms If PWRBTN max is exceeded ONCTL will go inactive t4 ONCTL inactive...

Page 419: ...see Section 6 4 1 1 GPIO Sup port Registers on page 233 GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec Asserting POR has no effect on ACPI If POR is asserted and ACPI was active...

Page 420: ...quency 25 MHz t1 TCK period 40 ns t2 TCK high time 10 ns t3 TCK low time 10 ns t4 TCK rise time 4 ns t5 TCK fall time 4 ns t6 TDO valid delay 3 25 ns t7 Non test outputs valid delay 3 25 ns 50 pF load...

Page 421: ...AMD Geode SC2200 Processor Data Book 439 Electrical Specifications 32580B Figure 9 58 JTAG Test Timing Diagram TCK t8 Input Output TDO TDI t11 t13 t9 t7 t6 t12 t10 TMS Signals Signals...

Page 422: ...440 AMD Geode SC2200 Processor Data Book Electrical Specifications 32580B...

Page 423: ...ve thermal management via Sus pend Modulation of the GX1 module is employed A maximum junction temperature is not specified since a maximum case temperature is Therefore the following equation can be...

Page 424: ...ambient in C This method is necessary because ambi ent and case temperatures fluctuate constantly during nor mal operation of the system The system designer must be careful to choose the proper heats...

Page 425: ...ta Book 445 Package Specifications 32580B 10 2 Physical Dimensions The figures in this section provide the mechanical package outlines for the BGU481 Thermally Enhanced Ball Grid Array package Figure...

Page 426: ...446 AMD Geode SC2200 Processor Data Book Package Specifications 32580B Figure 10 3 BGU481 Package Bottom View...

Page 427: ...t of 15 A Non B parts have a maximum IBAT current of 50 A Refer to Table 9 7 on page 373 for details Core Frequency MHz Core Voltage VCORE Temp Degree C Package2 2 Consult your local AMD sales office...

Page 428: ...sting on external web site Changes made to the Architecture Overview Signal Defini tions Core Logic Module Video Processor Module Electrical Specifications and Package Specifica tions chapters 3 0 Aug...

Page 429: ...One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 TWX 910 339 9280 TELEX 34 6306 www amd com...

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