6
AMD Geode™ LX Processor DDR2 BIOS Porting Guide
46959A - March 2009
Application Note
the CPLD are typically 0. Set SW_EN# high and
BA[1:0] to 01b.
Next, in MC_CF07_DATA register, set MSR_BA=01b
and PROG_DRAM=1. Then clear PROG_DRAM.
6)
Issue a LOAD MODE command to MR to reset the
DLL. Regardless of whether the DLL is running, AMD
does not recommend omitting this step.
Some memory devices require A[8]=1 and all other
A[n]=0 during this step. The JEDEC spec does not
indicate zeroing all other address pins. Therefore, it is
up to the BIOS to decide how to proceed during this
step. The other fields in the MR may be constructed
from existing settings in the MC.
Similar to the other LOAD MODE commands, set
SW_EN#=1 and BA[1:0]=00b. In the memory control-
ler, set MSR_BA=00b and PROG_DRAM=1. Then
clear PROG_DRAM.
7)
Wait 200 clock cycles, then issue a PRECHARGE ALL
command. As before, set the CPLD registers so that
A[10] will be high and all other A[n] signals are incon-
sequential. Keep SW_EN# high. Set the FORCE_PRE
bit in the MC_CFCLK_DBUG register to insert the
command before the subsequent step.
8)
Generate two REFRESH commands by twice setting
then clearing the REF_TST bit in the CM_CF07_DATA
register. Clear the FORCE_PRE bit between the two
REFRESH commands to avoid an extra PRECHARGE
ALL command.
9)
Issue a LOAD MODE command to MR to bring the
DLL out of reset. In the CPLD, set A[8]=0. Other A[n]
settings may need to be calculated.
– The burst length is in the MC_CF8F_DATA register
as TRUNC_DIS. Of course, 4 is the only common
setting, so this part may be abbreviated.
– The CAS# Latency may also be retrieved from the
MC_CF8F_DATA register. Due to the memory
controller restriction, this may be otherwise hard-
coded to 2.
– The Write Recovery for Autoprecharge field is
calculated using information in SPD[36], which is
new for DDR2.
Set SW_EN#=1 and BA[1:0]=00b. In the memory con-
troller, set MSR_BA=00b and PROG_DRAM=1. Then
clear PROG_DRAM.
10) Issue a LOAD MODE command to EMR(1) with OCD
set to Default. A[1:0] (driver strength and DLL enable)
are retrieved from MC_CF07_DATA. Set A[9:7]=111b
for OCD default. Set SW_EN#=1 and BA[1:0]=01b. In
MC_CF07_DATA set MSR_BA=01b and PROG_DRAM
=1. Then clear PROG_DRAM.
11) Issue a LOAD MODE command to EMR(1) to exit
OCD programming. A[1:0] (driver strength and DLL
enable) are retrieved from MC_CF07_DATA. Set
A[9:7]=000b for OCD default. Set SW_EN#=1 and
BA[1:0]=01b. In MC_CF07_DATA set MSR_BA=01b
and PROG_DRAM=1. Then clear PROG_DRAM.
12) Now the BIOS is finished with the CPLD and should
give control of the A[12:0] and BA[1:0] signals to the
memory controller. Write any value to REG_B with
SW_EN#=0.
13) Program the refresh rate in the REF_INT field of
MC_CF07_DATA. This process is identical to that used
with DDR technology. Each DIMM indicates its sup-
ported rate in SPD[12]. The BIOS determines an inter-
val that is sufficiently short for both DIMMs.
Note, however, that the location for this step has
moved for DDR2. The reason is that I2C accesses to
an On-DIMM CPLD are very slow. If REF_INT is pro-
grammed earlier, the memory controller generates
REFRESH commands during the initialization
sequence. This disrupts initialization and prevents the
DRAM from operating properly.
There are some additional settings recommended by AMD.
•
Typically the GLCP_DELAY_CONTROLS register is set
up very early in POST, and usually with hardcoded
values. AMD recommends an initial setting of
F2F100FF_56960304 in this register.
•
If there is no DIMM1, the SDCLK[5,3,1] should be
disabled in the GLCP_DELAY_CONTROLS register. Set
b[55] to do this.
•
Program the PMode Sensitivity Counter values in the
MC_CF_PMCTR register. Typical values are PMode0
counter set to 0 for most aggressive, and PMode1
counter set to 200h.
•
Program the PMode1 Up Delay field of
MC_CF1017_DATA to 209 clocks.
