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Summary of Contents for Geode LX CS5536

Page 1: ...attern presented on A 15 0 when the command is initiated Note however that A 15 13 0 and BA 2 0 in all cases Software on the LX processor issues LOAD MODE com mands by writing the MC_CF07_DATA registe...

Page 2: ...equired is a lower memory volt age Because the CPLD is contained on the DIMM assembly the only bus available for communication is I2C The CPLD s I2C address is A0 A1 i e the same as DIMM0 The CPLD als...

Page 3: ...command by setting and then clearing the PROG_DRAM bit in the MC_CF07_DATA register AMD also recommends setting the MSR_BA field same register to the desired BA 1 0 levels same procedure as initializi...

Page 4: ...upports 2 or 4 banks but DDR2 devices may support 4 or 8 The Dn_CB fields should be programmed with a 1 to indi cate 4 banks The BIOS should not allow configura tions indicating 8 banks Calculate the...

Page 5: ...CE_PRE bit in the MC_CFCLK_DBUG register to insert the PRE CHARGE ALL Additionally the PRECHARGE ALL command requires that A 10 be set high This presents a minor architectural problem The BIOS will no...

Page 6: ...n in SPD 36 which is new for DDR2 Set SW_EN 1 and BA 1 0 00b In the memory con troller set MSR_BA 00b and PROG_DRAM 1 Then clear PROG_DRAM 10 Issue a LOAD MODE command to EMR 1 with OCD set to Default...

Page 7: ...e memory i e cycle time multiplied by the normal CAS Latency The reason for this restriction is that the LX processor s mem ory controller must operate with a Write Latency of 1 clock DDR2 defines CAS...

Page 8: ...antability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intende...

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