AMD ATI CTM, Technical Reference Manual

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Setting Predicate Bits 31
© 2006 Advanced Micro Devices, Inc. ATI CTM Guide v. 1.01
• RNDR_TGT_D - Write to render target D register
The OUT_FMT_* registers describe render targets A through D. The results are stored and the final value is sent out
when the program terminates. If a channel in an output target is written more than once, the final value written is what
will be sent out. The RGB and alpha unit may write to different targets in the same instruction.
The output may be predicated using PRED_SEL and PRED_INV.
You may also perform uncached output (or UMRT writes), which are sent out immediately, but you cannot perform
cached and uncached writes in the same program. The selection of the kind of program (a program that uses cached
writes or one that uses uncached writes) is selected by CTM based on information supplied with the program itself.
An output instruction in a UMRT program must either write all channels, or no channels. The green and blue channels
will be interpreted as the (X,Y) coordinates, the alpha channel must be zero, and the red channel contains the 32-bit
floating-point value to write. A UMRT program writes only one 32-bit value per output instruction.
The type of UMRT write performed is controlled by the RGB TARGET field (the alpha unit's TARGET field is
ignored). To perform a UMRT write, set the RGB TARGET field to one of the following values:
• RNDR_TGT_UMRT_SAME_IDX - Write using a shared index for all processors.
• RNDR_TGT_UMRT_SAME_IDX_TEX_SEM_ACQUIRE - and acquire texture semaphore to synchronize
reads.
• RNDR_TGT_UMRT_PER_PROCESSOR_IDX - Write using distinct index for each processor (at 1/4 speed).
• RNDR_TGT_UMRT_PER_PROCESSOR_IDX_TEX_SEM_ACQUIRE - and acquire texture semaphore to
synchronize reads.
If the program is reading back results written with uncached writes, then the program should use one of the
TEX_SEM_ACQUIRE choices to synchronize uncached writes and reads. Additional information on the texture
semaphore is given in the texture instruction overview, below.
3.3.9 Setting Predicate Bits
Each instruction may optionally set one or more predicate bits. ALU instructions (as opposed to OUTPUT
instructions) interpret the OMASK fields as a predicate writemask. The TARGET field determines when to set the
bits associated with each channel:
• PRED_OP_EQUAL - Set when channel is zero.
• PRED_OP_LESS - Set when channel is negative.
• PRED_OP_GREATER_EQUAL - Set when channel is non-negative.
• PRED_OP_NOT_EQUAL - Set when channel is non-zero.
The enumeration's names are based on the assumption that they will be primarily used after a subtraction of two
values. That's not the only possible use, of course. The RGB and alpha units may use different functions to set the
predicate in the same instruction.
In order to achieve the remaining common comparisons, <= and >, one can simply reverse the order of the values
being subtracted, or reverse both signs, and use the >= and < operations respectively.
You can simultaneously write to the predicate register and a temporary register, and you can perform a predicated
temporary register write if you are also writing the predicate register. However, the old value of the predicate will
only be applied to the temporary register's write mask; it will not be applied to the predicate write mask. In other
words, if the predicate is 0x7, your temporary write mask is 0xf and your predicate write mask is 0xf, you will write
only RGB components to the temporary register, but you will write to all 4 predicate bits.
If the instruction result is clamped, the comparison happens on the post-clamped result. If output modifier is disabled,
denormals may be compared -- denormals are equivalent to zero.