DMA Controller
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Am186™CC/CH/CU Microcontrollers User’s Manual
so that the address never exceeds the boundary of the buffer. Software must manually wrap
the buffer address back to the start of the buffer whenever an interrupt signifies the end of
the buffer. This is not too burdensome for UART transmit buffers because there is no hard
latency requirement for asynchronous transmission, but this could be a problem for receive
buffers if the interrupt latency could cause characters to be missed.
8.5.7
SmartDMA Channels
The Am186CC/CH/CU microcontrollers each contain SmartDMA channels, compatible with
the DMA in the AMD Am79C90 C-LANCE (Local Area Network Controller for Ethernet).
This LANCE-compatible buffer descriptor ring interface provides a method for transmission
and reception of data across multiple memory buffers. The ring descriptor interface also
provides a method for reporting status on multiple received and transmitted packets while
ensuring that status information is always correctly linked with the associated data.
Unlike the general-purpose DMA channels, which can be used for memory-to-memory or
I/O-to-I/O transfers, the SmartDMA channels are highly specialized. These channels must
be used in pairs. Each pair consists of a transmit channel and a receive channel.
The
transmit channels transfer data from memory to a transmitting device (such as an HDLC
transmitter). Receive channels transfer data from a receiving device (such as an HDLC
receiver) to memory.
Four of the eight SmartDMA channels (two pairs) in the Am186CC microcontroller are
dedicated for use with the on-board HDLC channels. The remaining four SmartDMA
channels (two pairs) can support either the third or fourth HDLC channel or USB endpoints
A, B, C, or D.
The four SmartDMA channels (two pairs), SDMA0 and SDMA1, in the Am186CH HDLC
microcontroller support the two on-board HDLC channels.
The four SmartDMA channels (two pairs), SDMA2 and SDMA3, in the Am186CU USB
microcontroller support USB endpoints A, B, C, or D.
This section describes these SmartDMA channels.
8.5.7.1
SmartDMA Channels Introduction
With a traditional DMA controller, such as the general-purpose DMA, the typical mode of
operation is to DMA transfer a buffer of information (either filling a receive buffer, or emptying
a transmit buffer) and program the DMA controller to interrupt the CPU when the end of
the buffer is reached.
However, if the data rate is high relative to system loading and interrupt latency, data could
be lost before the interrupt service routine reinitializes the DMA controller to point to the
next buffer. For some peripherals, such as UARTs, this problem is easily solved by the
ability of the general-purpose DMA controller to manage a circular buffer. If such a circular
buffer is managed correctly, DMA is never halted to wait on CPU interrupt activity.
A circular buffer does not work as well for packet-oriented communications such as HDLC
and USB because of the requirement to delineate packet boundaries. Also, in a typical
system, each packet can be routed to a different destination, so the data would have to be
copied out of the circular buffer and into another peripheral’s circular buffer.
SmartDMA channels solve these problems by maintaining a circular queue of buffer
descriptors—a
descriptor ring—rather than a circular data buffer. The hardware itself
updates a buffer descriptor when a full buffer is transferred, then automatically fetches the
next descriptor and starts transferring data to the new buffer. Because the hardware
CC
CH
CU
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...