DRAM Controller
6-6
Am186™CC/CH/CU Microcontrollers User’s Manual
6.5.5.2
DRAM Refresh Intervals
During a refresh cycle, the AD bus drives the address to FFFFh, which prevents the PCS
and MCS signals from asserting inadvertently. PCS and MCS decode should never contain
the address FFFFFh. The UCS signal does not assert during a refresh cycle. If two banks
of DRAM are being used in a system (i.e., RAS0 and RAS1), then both banks are refreshed
at the same time.
The interval counter (CDRAM register and EDRAM register) is expanded by two bits over
earlier Am186 microcontrollers. The refresh counter has a maximum timer count that
reaches 163.9 µs at 50 MHz. See Table 6-5 and Equation 6-1.
The normal refresh rate on a DRAM is 15.6 µs. This refresh rate allows for each of the 1024
row addresses to be refreshed in the required 16 ms. Some DRAMs might have different
refresh rates for low-power DRAMs and special considerations. Table 6-5 demonstrates
the typical values that a programmer might want to use for refresh time intervals to be placed
into the RC bit field of the CDRAM register.
The Am186CC/CH/CU microcontrollers support DRAMs with a CAS-before-RAS refreshing
scheme. A refresh is generated based on the system clock frequency. The maximum count
value for a refresh is 163.9 µs at 50 MHz. The CAS-before-RAS refresh cycle is seven clock
cycles long. An 11-bit counter inserts a refresh bus cycle after the last bus cycle concludes
to run the CAS-before-RAS cycle.
Equation 6-1 Refresh Interval Time Equation
6.5.6
Hardware-Related Considerations
■
The LCS memory space supports use of either the DRAM interface or the SRAM
interface, not both.
■
An external bus master needs to be able to deassert HOLD in response to HLDA going
inactive for DRAM refresh cycles to take place.
6.5.7
Software-Related Considerations
Do not program the refresh period too small. If you do, the system does not have time to
execute code.
Table 6-5
Refresh Interval Times
CPU
Frequency
Clock
Period
CDRAM
Counter
(hex)
CDRAM
Counter
(decimal)
Refresh
Interval
Time
50 MHz
20 ns
30Ch
780d
15.6 µs
40 MHz
25 ns
270h
624d
15.6 µs
25 MHz
40 ns
186h
390d
15.6 µs
CDRAM Counter Value (Decimal) =
Refresh Interval Time
Clock Period
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...