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DMA Controller
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Am186™CC/CH/CU Microcontrollers User’s Manual
If the OWN bit is 0, the software owns the current descriptor. In this case, the SmartDMA
transmit channel periodically polls the descriptor until the OWN bit becomes 1. The
transmit channel does not advance past a descriptor for which the OWN bit is 0. For
information about forcing a poll, see “SmartDMA Channel Descriptor Polling” on
page 8-41.
3. If the OWN bit is 1 in the current descriptor, the transmit channel checks to see if the
start-of-packet bit (STP) bit is set to 1.
If the STP bit is 0, the transmit channel enters Search-For-Start-of-Packet mode. This
mode simply clears the OWN bit in the current descriptor and advances to the next
descriptor ring entry. The transmit channel then returns to Initialization mode, repeating
these steps until it finds an entry with both the OWN and STP bits set to 1.
4. If the OWN and STP bits are both set to 1, the transmit channel reads the length of the
buffer from the descriptor ring (BCNT bits in Word 2) and programs that value into an
internal terminal count register. The address of the buffer associated with this descriptor
is read from the descriptor (LADR and HADR bits) into the SDxCTAD source address
register. The transmit channel then enters normal-transmit mode.
5. In transmit mode, the channel transmits one byte of data from the memory buffer to the
destination device for every DRQ. After each transfer, the source address in SDxCTAD
is incremented and the internal transfer count is decremented.
6. When the internal terminal count is reached, the transmit channel checks the end-of-
packet (ENP) bit.
a. If the ENP bit is 0 in the current descriptor, the transmit channel attempts to acquire
the next buffer. The transmit channel releases the current buffer by clearing the OWN
bit (unless the TXS0 bit is set). It then advances to the next descriptor in the ring. If
the OWN bit is 0 (the software owns the descriptor), the transmit channel periodically
polls the descriptor until OWN becomes 1. If an error condition occurs (e.g., a FIFO
underflow) before the transmit channel acquires the next descriptor, the error causes
the requesting transmit source to shut down and the SmartDMA channel to be
reprogrammed. If the transmit channel successfully acquires the next descriptor, the
new buffer address and terminal count are loaded into the appropriate internal
registers.
b. When the terminal count is reached for a buffer for which the ENP bit is set, the transmit
channel enters Transmit-End mode. In this mode, the transmit channel signals the
end-of-packet to the device by asserting an internal signal during the transfer of the
last data byte. The SmartDMA transmit channel waits for the packet to be sent
successfully, then advances the index to the next buffer.
If a complete packet is transmitted, the channel releases the current buffer by clearing
the OWN bit before attempting to advance to the next buffer. If a packet is incomplete
when the channel has reached terminal count on the buffer, it releases control of the
buffer and advances to the next buffer in the ring. If the TXS0 bit is set, the channel
moves to the next buffer without clearing the OWN bit.
Whenever a packet needs to be retransmitted, the transmit channel must be disabled
and the Current Buffer Descriptor (SDxCBD) register must be programmed with the
index of the buffer descriptor containing the STP bit for that packet. The transmit
channel does not report any status in the buffer descriptor other than clearing the
OWN bit.
Note: Before disabling the transmit channel, you should stop the HDLC channel.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...