Altos ACS8600 User Manual Download Page 73

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Summary of Contents for ACS8600

Page 1: ...INFORMATION PURPOSES ONLY IT WILL BE CHANGED WITHOUT NOTICE THE INFORMATION CONTAINED HEREIN REPRESENTS THE MOST CURRENT INFORMATION AVAILABLE AT THE TIME OF PRINTING HOWEVER THE INFORMATION HAS NOT B...

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Page 3: ...ested and found to co ply with the limits for a_Class A co puting device pursuant to Subpart J of Part 15 of FCC Rules which are designed to provide reasonable protection against such interference whe...

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Page 5: ...ORMATION PURPOSES ONLY1 IT WILL BE CHARGED WITBOur NOTICE THE INFORMATION CONTAINED HEREIN RBPRESRmS THE MOST CURRElft IllIFORIlATION AVAILABLE AT THE TIRE OF PRINTING HOWEVER l BE IlI FORMATION BAS N...

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Page 7: ...ectors SECONDARY SYSTEM ENCLOSURE PHYSICAL DETAILS Size weight Front Panel Controls Rear Panel Connectors FEATURES AND CAPABILITIES SYSTEM CONFIGURATIONS Hardware Functional Description CENTRAL PROCES...

Page 8: ...Drive 2 5 SYSTEM CONFIGURATION 2 7 CONNECTING PERIPHERAL EQUIPMENT 2 8 Console Terminal 2 8 CONNECTING THE POWER SOURCE TO THE COMPUTER 2 9 Section 3 RUNNING THE ALTOS DIGNOSTIC EXECUTIVE ADX PROGRAM...

Page 9: ...of this manual The Specification contains its own Table of Contents List of Figures and List of Tables see Section 7 APPENDICES A SHIPPING DAMAGE AND REPAIR PROCEDURES A I B TROUBLE SHOOTING PROCEDURE...

Page 10: ...Unit Version 1 11 1 5 ACS 8688 Computer System Architecture 2 1 2 2 2 3 Block Diagram 1 16 Unlocking the l8 Mbyte Bard Disk Unlocking the 28 or 48 Mbyte Bard Disk ACS 8688 Computer System Rear Panel T...

Page 11: ...stems has designed a publication structure that differs from most user manuals The purpose of this structure is fourfold 1 To provide accurate system information to the user as quickly as possible 2 T...

Page 12: ...Column 3 illustrates Supporting Manuals which include pre printed manuals produced by developers of related software products that operate on the ACS 8699 Computer System This group may also include m...

Page 13: ...0 j a til VI a f I r I I I I I I I 1 I I I I _e i I I r b I I I I I Lo i N r I I I I I I I I I I il Figure l l ACS 86 Computer Syste Organization Illustration r _ _ z 1 r I I __ I I I I I I i If 0 II...

Page 14: ...rt ftj fA JUM M11 i Skee S Y 7 e lit Chd4JUT S n e e r r rENt Cltte dIJ Fr SVt Qe 1 AJT L e poi2 T WA iAIJT I C P RD C he C t F L eeT I I I C O E il Le Tif It I Ii I j I Ii I II II i I I i I I Figure...

Page 15: ...both hardware and software Section 2 SETTING UP THE COMPUTER SYSTEM provides instructions for removing the computer and its components from the shipping container identifying the components storing r...

Page 16: ...endix A ALTOS WARRANTY DESC IPTION AND SHIPPING DAMAGE REPAIR PROCEDURES describe the Altos Warranty and provide instructions for filing the End User Registration Card and the Dealer Registration Card...

Page 17: ...tem components 3 Assemble the publications and verify that all are present When the shipping container is unpacked insert the supplements into their proper place in the manual 3 Refer to Section 3 for...

Page 18: ...IC EXECUTIVE ADX PROGRAM is provided in Section 3 A description of four Operating System Supplements Control Program Monitor CP M 86 Multi Program Monitor MP M 86 XENIX and OASIS 16 Operating Sy_stems...

Page 19: ...ocessor one 8089 DMA handles direct memory accessing for I O processing The optional mathematical processor 8087 Floating Point Processor handles mathematical functions Although each processor is opti...

Page 20: ...re houses on request Syste Functional Description The ACS8600 Computer System is an advanced design 16 bit general purpose computer manufactured by Altos Computer Systems System design supports up to...

Page 21: ...r I OI c SECTIO 1 IRTRODUCTION SYSTCU K8ET 61II1D swrt Figure 1 3 ACS 8600 Computer System Hard Disk Floppy Disk Version Figure 1 4 ACS 8600 Computer System Hard Disk Magnetic Tape Unit Version Revisi...

Page 22: ...SET Switch to left of ON OFF switch Rear Panel Connectors see Figure 2 3 AC Power Receptacle Fuse Holder Parallel Port Interface Connector DB 37 Hard Disk Expansion Connectors 29 pin and 58 pin Consol...

Page 23: ...g Rigid disk controller for one or two 8 inch Winchester type rigid fixed disk drives One programmable parallel interface capable of controlling a high speed parallel input line printers Ten serial in...

Page 24: ...r type hard disk drive and either an eight inch 588 Kbyte single sided floppy diskette drive or a cartridge type l7 Mbyte Magnetic Tape Unit MTU One additional secondary enclosure containing power sup...

Page 25: ...es instructions fetched by the 8 86 and will bus request the 8 86 as required to perform the arithmetic operations SYSTEM MEMORY System Memory is implemented with 64 Kbyte dynamic RAM devices and 2732...

Page 26: ...aaallr CGmraIIr 1II m8Ia s tIt e nnt PrQCWiGis s _ 8IJ61 MImary Managw Randam Etrar CGilIc tIoft CJi CUH I y ECC EIuoI SU MMIaI I o 1ay _______ a _ _ H1gIIs a III 11I r Une PrIrar aus I III Figure 1 5...

Page 27: ...t errors However single bit errors are the most frequently occurring errors When an error is detected the syndrome and the address associated with the error are latched and the CPU is interrupted When...

Page 28: ...of the three error reporting registers supported by the memory manager This 16 bit register indicates the type of memory access violation that has occur red Two other I O ports are used to report the...

Page 29: ...uffered with a unidirectional buffer that provides three bits of input and five bits of output The buffer ing on Port C supports the handshake and interrupt signals used by port B in mode one SERIAL C...

Page 30: ...nected through rear panel connections on the primary enclorure This expansion capability allows system users to add custom interfaces to the system The interface supports both 8 bit and l6 bit bus mas...

Page 31: ...ort Magnetic Tape Controller board Central Processing Unit board Hard Rigid Disk Drive Unit Hard Disk Controller board Printed Circuit Board Kilobyte one thousand bytes Megabyte one million bytes The...

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Page 33: ...components SBLBC rIE A COIIPUTBR SITE The ACS 8600 Computer System is rugged and dependable under any reasonable conditions however it operates most sa tisfactor ily when conditions are as close to id...

Page 34: ...Turn the shipping container right side up and carefully cut the binding tape and open the container IOB Ose reasonable care in opeDing the shipping container sharp or pointed iDstruaents ay pierce th...

Page 35: ...m User Manual accompanied by the following One Cover Letter One Checkoff Sheet One Warranty Card Four Quality Control Reports System Checkoff Sheet System Checkout Sheet Burn In Summary Sheet Quality...

Page 36: ...ve 1 Loosen the drive motor nut with a hex socket or hex nut driver from the hard disk spindle motor Figure 2 3 Rotate the locking cli p away from the pulley Do not rotate the pulley Re tighten the nu...

Page 37: ...IRSTALLATIOB computer Chassis with Bottom Plate Mounted It 0 I I J o 0 Computer Chassis with Bottom Plate Removed and Locking Devices Exposed Figure 2 1 Unlocking the l Mbyte Hard Disk Revision B Mar...

Page 38: ...OB 2 DlSTALLATIOR computer Chassis with Bottom Plate Mounted o o Computer Chassis with Bottom Plate Removed and Locking Devices Exposed Figure 2 2 Unlocking the 29 or 49 Mbyte Hard Disk Revision B Mar...

Page 39: ...ossible radio TV interference all interface cables should have a grounded shield and be electrically and mechanically secure to the units to which they are connected Altos Diagnostic Executive ADX pro...

Page 40: ...he pins in a one to one correspondence All cables should be fastened with the connector retaining screws to provide a proper shield ground path RS 232 C serial communications 96ee Baud Asynchronous Mo...

Page 41: ...Install the three pronged power cord in the rear panel AC receptacle and plug it into a power source wall plug etc Be certain that the floppy disk transport or the magnetic tape cartridge transport i...

Page 42: ...led the computer will not boot successfully Press the round RESET button to the left of the POWER switch on the computer front panel to restart the boot process then within two seconds press any key T...

Page 43: ...ion Connectors t _ _ PORTS Multibus Expansion Connectors 11111 PS2 BT RT II iIM _ _ PORT 6 PORT 4 SERIAL PORTS Magnetic Tape Unit Drive Connector o 6 8 82 Figure 2 3 ACS Computer System Rear Panel Rev...

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Page 45: ...nder supervision of the diagnostic executive to ver ify opera tion of the system and its components ADX prepares the computer system for installation of the selected Operating System Follow the instru...

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Page 47: ...lated to the Operating System s purchased is provided with the system Each supplement provides specific step by step installation procedures for one particular operating system and also introduces you...

Page 48: ...of RAM One to sixteen disk drives of up to 8 Mbytes each An ASCII console device such as a CRT terminal KP 86 KOLTI USER OPBRATrRG SYSTBK MP M is a multi user 16 bit multi tasking operating system des...

Page 49: ...MATION WAS NOT READY WHEN THIS MANUAL WAS PRINTED PROGRAIIIIIRG LARGUAGBS BASIC COBOL PASCAL and FORTRAN languages are also distributed and supported by Altos Computer Systems APPLICATIOB PROGRAIIS Al...

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Page 51: ...TY PROGRAMS USER INSTRUCTIONS which should be inserted in this part of the manual when the shipping container is unpacked Supplement 5 describes Altos Utility Programs available for use with the syste...

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Page 53: ...pansion interfaces a 18 28 or 48 Mbyte Winchester type hard disk drive and ei ther an eight inch S88 Kbyte single Sided floppy diskette drive or a cartridge type l7 Mbyte Magnetic Tape Unit MTU as sho...

Page 54: ...rence Table Kit Number Add 10 Add 12 Add 14 Add 10 MTU Add 12 MTU Add 14 MTU Add RAM Add MTU 3 Add Primary Media l0 Mbyte Hard Disk 20 Mbyte Hard Disk 40 Mbyte Hard Disk 10 Mbyte Hard Disk 20 Mbyte Ha...

Page 55: ...IRPORIIATIOR The ACS 86 0 System Specifications have been included in this preliminary User Manual so that the information can be distributed as soon as possible This information will be incorporated...

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Page 57: ...g this document should be directed to Altos Computer Systems Attn Jim Willott 2369 Bering Drive San Jose CA 95131 Phone 498 946 6788 Copyright C 1988 by Altos Computer Systems Inc This document may no...

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Page 59: ...Page 65 previously read J6 l5 6 10 ACKNOWLEDGE from LP It has been changed to read J6 l5 8 10 ACKNOWLEDGE from LP Additional related changes This Change Notice has been added as Page i Pages ii and ii...

Page 60: ...as listed below Jumper 18 22R Pin 11 to Pin 11 Jumper 19 22R Pin 13 to Pin 14 On Btch Revision J juapers 18 and 19 are located near device ocation 10 WARRIBG On Btcb Revisions B and earlier Revisions...

Page 61: ...C CPU Boards do not bave Jumper 17 in tbe parallel interface If tbe user plans to use the parallel interface 8255 sucb that Port B is program ed in Mode I tbe trace between 28S Pin 16 and 29 1 Pin 5...

Page 62: ...itry 4 3 3 Memory Manager Section 4 3 4 Expansion Memory 4 3 5 Boot Memory Flexible Diskette Controller Rigid Disk Controllers and Interface Parallel Interface Serial Interfaces 4 7 1 primary Serial C...

Page 63: ...ION BLOCK DIAGRAM 6 3 3 MEMORY SECTION BLOCK DIAGRAM 7 3 4 FLEXIBLE DISKETTE CONTROLLER BLOCK DIAGRAM 10 4 1 I O PORT DECODER BLOCK DIAGRAM 14 4 2 MEMORY CONTROLLER BLOCK DIAGRAM 21 4 3 MEMORY ADDRESS...

Page 64: ...r USCELLANEOUS CONTROL BITS 63 4 24 I O PORT 055 HEX BITS 4 AND 5 DMA REQUEST SELECT 63 4 25 PARALLEL INTERFACE PINS AND CAPABILITIES 64 4 26 PARALLEL CENTRONICS INTERFACE CONNECTOR 65 4 27 BAUD RATE...

Page 65: ...etection and correction and a wide variety of mass storage peripherals The system memory is provided with unique memory management hardware that improves the ef f icient use of main memory The ACS 869...

Page 66: ...e main memory providing address translation write protection and access control for each four kilobyte block of main memory Bootstrap and configuration control read only memory permitting system ini t...

Page 67: ...ystem configurations some of which are listed below in Table 2 2 A ten twenty or forty megabyte Winchester type rigid disk An eight inch flexible diskette drive one half megabyte single sided or one m...

Page 68: ...and will bus request the 8086 as required to perform the arithmetic The block diagram for the ACS 8600 System Memory is shown in Figure 3 3 page 7 The system Memory is implemented with 64K dynamic ra...

Page 69: ...PRBLIlIIlIARY 8688 DSER IlAllDAL SBC rIOR 7 SYS lBJI SPBCS Figure 3 1 ACS 8688 SYSTEM BLOCK DIAGRAM Specification Revision 4 2 Kay 27 1982 Page 5...

Page 70: ...PRBLIIIIlIARY 86 1 OSBR IIAIIOAL SBc rION 7 SYSTBII SPBCS Figure 3 2 CPO SBCTION BLOCK DIAGRAM Specification Revision 4 2 Ray 27 1982 Page 6...

Page 71: ...PRBLIIIIIlARY 86 OSER IIAIIOAL SBCrIOR 7 SYSTEM SPECS Figure 3 3 MEMORY SECTION BLOCK DIAGRAM Specification Revision 4 2 Ray 27 1982 Page 7...

Page 72: ...sses which allow it to access one million 1 948 576 bytes of memory however this memory must be accessed in blocks of 64K 65 536 bytes Limited protection is provided by the fact that the memory beyond...

Page 73: ...large scale integrated devices and can support up to four eight inch flexible diskette drives operating in either single density or double density recording mode The ACS 8600 system provides addition...

Page 74: ...PRBLIIIDIARY 8611 usa IIAIIUAL SBC rIOB 7 SYSDII SPECS Figare 3 4 FLDIBLB DISOftE mlft ROLLBR BLOCK DIAGRAM Specification Revision 4 2 1Ia r 27 1982 Page 11...

Page 75: ...both transmit and receive clocks to supportbi synchronous serial devices Each serial channel has a corresponding programmable timer for baud rate generation to allow for independent baud rates This bo...

Page 76: ...86 as required to perform the arithmetic Since the three processors of the central processing unit are arranged in a local configuration they must be supplied with a common clock he clock used by the...

Page 77: ...f the decoder on the Tape Controller board is shown on sheet one of the Tape Controller Board Schematic while the logic contained on the CPU board is shown on sheet eighteen of the ACS 86fiJfiJ CPU Bo...

Page 78: ...PRBLIIIIlIARY 8611 USER IIAlIUAL SECTIOR 7 SYS lB1I SPECS Figure 4 1 I O PORT DECODER BLOCK DIAGRAII Specification Revision 4 2 May 27 1982 Page 14...

Page 79: ...98 ACCESSES PORT 9998 ACCESSES PORT 0998 ERROR ADDRESS 1 READ ONLY ACCESSES PORT 9910 ACCESSES PORT 0019 ACCESSES PORT 9919 ACCESSES PORT 9919 ACCESSES PORT 9919 ACCESSES PORT 9919 ACCESSES PORT 9919...

Page 80: ...6 USER MODE FLAG ROM ENABLE COLD START 9931 ACCESSES PORT 9939 9932 ACCESSES PORT 9939 9933 ACCESSES PORT 9939 9934 9935 9936 9937 9938 9939 993A 993B 993C 0030 993E 993F ACCESSES PORT 9939 ACCESSES P...

Page 81: ...L CH B CONTROL R W CONSOLE 1 INTERVAL TIMER CONTROL WRITE ONLY DECODED BUT NOT USED ROM PORT HI STRAPPING OPTIONS INPUT DECODED BUT NOT USED ROM roRT HI FLOPPY SELECT NMI INHIB DECODED BUT NOT USED RO...

Page 82: ...I 0 6F I DECODED BUT NOT USED I 070 0 71 072 e73 74 e75 0 76 0 77 0e78 79 07A 7B 007C o 7D 7E 7F I I 16 I 16 BIT ECC DIAGNOSTIC LATCH I 1 DECODED BUT NOT USED I I ACCESSES PORT 0070 I I ACCESSES PORT...

Page 83: ...NSION RESERVED FOR MULTIBUS I O MEM MAGR PORT 1 16 BIT R W USE ONLY EVEN NUMBERED PORTS MEM EX 0200 0202 0204 SUB BLOCK NUMBER WITH LSB 0 FOR LS 9 BITS OF ADDRESS MAGR PORT 2 16 BIT R W USE ONLY EVEN...

Page 84: ...he Error Cor rection Circuitry and notifies the CPU when memory data is ready The Memory Controller Block Diagram is shown on the next page and the logic is shown on sheet six of the ACS 86 CPU Board...

Page 85: ...PRBLlllIllARY 8611 osa IIABOAL SBC lIOI1 7 SYSUIl SPECS Figure 4 2 IlEIKlRY CONBOLLBR BLOCK DIAGRAII Specification Revision 4 2 May 27 1982 Page 21...

Page 86: ...9 9 9 1 9 CHECK BIT 1 982 HEX 9 9 9 1 9 9 CHECK BIT 2 984 HEX 9 9 1 9 9 9 CHECK BIT 3 988 HEX 9 9 1 9 1 1 DATA BIT 1 98B HEX 9 9 1 1 1 9 DATA BIT 9 98E HEX 9 1 9 9 9 9 CHECK BIT 4 999 HEX 9 1 9 9 1 1...

Page 87: ...latch are given below in Table 4 3 while the various modes of operation are given on page 25 in Table 4 4 Memory diagnostic software can take advantage of these capabilities to validate the functiona...

Page 88: ...ne of four diagnostic modes Mode zero causes the chip to operate under software control in the same manner as it would if it were not in diagnostic mode When the Correct Mode Control bit is zero the E...

Page 89: ...orrectl Four types of memory are defined CODE DATA STACK and EXTRA DATA and a segment register is provided for each memory type The 8086 generates addresses which allow it to access one million 1 048...

Page 90: ...PRBLIIIIJIARY 86 USER IIAIIUAL SBC fIOR 7 SYS BII SPBCS Figure 4 3 IlEIIORY ADDRESS GERERA IOR IN mE ACS 86 Specification Revision 4 2 r May 27 r 1982 Page 26...

Page 91: ...the stack segment register are limit checked to detect the presents of impending stack overflow If the page being accessed is marked as a Stack Boundary Segment and if a wr i te is perf ormed in the...

Page 92: ...status registers of the memory management hardware are accessed through three sixteen bit read only I O ports The 512 I O ports are the even numbered ports from 0200 hex through 05FF hex and must be a...

Page 93: ...F 9216 9416 9C 9C999 9CFFF 9218 9418 9D 9D999 9DFFF 921A 941A 9E 9E999 9EFFF 921C 941C 9F 9F999 9FFFF 921E 941E 19 19999 19FFF 9229 9429 11 11999 11FFF 9222 9422 12 12999 12FFF 9224 9424 13 13999 13FF...

Page 94: ...2C 2CBBB 2CFFF B258 B458 2D 2DBBB 2DFFF B25A B45A 2E 2EBBB 2EFFF B25C B45C 2F 2FBBB 2FFFF B25E B45E 3B 3BBBB 3BFFF B26B B46B 31 31BBB 31FFF B262 B462 32 32BBB 32FFF B264 B464 33 33BBB 33FFF B266 B466...

Page 95: ...98 0498 4D 4D001 J 4DFFF 1 J29A 1 J49A 4E 4E001 J 4EFFF 1 J29C 1 J49C 4F 4F001 J 4FFFF 1 J29E 1 J49E 51 J 50000 51 JFFF 02AO 04AO 51 51000 51FFF 02A2 1 J4A2 52 52001 J 52FFF 02A4 1 J4A4 53 531 J00 53F...

Page 96: ...B 6B999 6BFFF 92D6 94D6 6C 6C999 6CFFF 92DS 94DS 6D 6D999 6DFFF 92DA 94DA 6E 6E999 6EFFF 92DC 94DC 6F 6F999 6FFFF 92DE 94DE 79 79999 79FFF 92E9 94E9 71 71999 71FFF 92E2 94E2 72 72999 72FFF 92E4 94E4 7...

Page 97: ...000 8CFFF 0318 0518 8D 8D000 8DFFF 031A 051A 8E 8E000 8EFFF 031C 051C 8F 8F000 8FFFF 031E 051E 90 90000 90FFF 0320 052rl1 91 91000 91FFF 0322 0522 92 92000 92FFF 0324 0524 93 93000 93FFF 0326 0526 g4...

Page 98: ...0556 AC AC000 ACFFF 0358 0558 AD AD000 ADFFF 035A 055A AE AE000 AEFFF 035C 055C AF AF000 AFFFF 035E 055E B0 B0000 B0FFF 0360 0560 Bl BI000 BIFFF 0362 0562 B2 B2000 B2FFF 0364 0564 B3 B3000 B3FFF 0366...

Page 99: ...F 0396 0596 CC CC000 CCFFF 0398 0598 CD CD000 CDFFF 039A 059A CE CE000 CEFFF 039C 059C CF CF000 CFFFF 039E 059E D0 D0000 D0FFF 03A0 05A0 Dl D1000 DIFFF 03A2 05A2 D2 D2000 D2FFF 03A4 05A4 D3 D3000 D3FF...

Page 100: ...3D6 9SD6 EC EC999 ECFFF 93D8 9SD8 ED ED999 EDFFF 93DA 9SDA EE EE999 EEFFF 03DC 9SDC EF EF999 EFFFF 93DE 9SDE F9 F9909 F9FFF 93E9 9SE9 Fl F1009 FIFFF 03E2 0SE2 F2 F2909 F2FFF 03E4 9SE4 F3 F3999 F3FFF 9...

Page 101: ...in application mode Therefore bit seven also controls the ability of the S9S7 to write into the indicated memory page regardless of the state of the Application User Mode flip flop This bit operates i...

Page 102: ...t used forced to 8 on read 5 ALLOW EXP PROC WRITE 1 6 ALLOW DMA MATH PROC WRITE 1 7 ALLOW USER WRITE 1 8 ALLOW SYSTEM WRITE 1 9 ALLOW EXP PROC ACCESS 1 18 ALLOW DMA MATH PROC ACCESS 1 11 ALLOW USER AC...

Page 103: ...r and is described in Table 4 8 on page 42 This sixteen bit register is read through I O port 90 hex and indicates the reason for the non maskable interrupt After processing the non maskable interrupt...

Page 104: ...5 PHYSICAL ADDRESS 17 1 6 I PHYSICAL ADDRESS 18 1 1 7 1PHYSICAL ADDRESS 19 1 1 8 1 not used undefined I 9 1not used undefined 1 19 1 not used undef ined I 1 1 11 1 not used undefined I 1 1 12 I not us...

Page 105: ...askable interrupt The specific error is reported through the viola ti on por t descr ibed above I O por t BI B hex contains the least significant sixteen bits of the last address strobed onto the CPU...

Page 106: ...P PROC WRITE VIOLATION 1 9 6 DMA PROC WRITE VIOLATION 1 9 7 USER WRITE VIOLATION 1 9 1 1 8 LATCHED BUS ACCESS TIME OUT ERROR 9 I J 9 EXP PROC ACCESS VIOLATION 9 1 19 DMA PROC ACCESS VIOLATION 9 II USE...

Page 107: ...Y ERROR ADDRESS 5 1 6 MEMORY ERROR ADDRESS 6 1 7 MEMORY ERROR ADDRESS 7 1 8 MEMORY ERROR ADDRESS 8 1 9 MEMORY ERROR ADDRESS 9 1 IS MEMORY ERROR ADDRESS IS 1 11 MEMORY ERROR ADDRESS 11 1 1 12 MEMORY ER...

Page 108: ...IT 5 1 6 MEMORY ERROR 8 7 MULTI BIT MEMORY ERROR 8 8 APPLICATION USER MODE 1 1 9 ROM ENABLE 1 1 18 not used forced to 8 1 11 WARM START FLAG 8 COLD I WARM 1 12 MEMORY ERROR ADDRESS 16 1 13 MEMORY ERRO...

Page 109: ...ed ap plication is for the operating system to request application mode just prior to returning to the execution of an application program The Application Mode flip flop is reset to Operating System M...

Page 110: ...nored 5 not used ignored 6 not used ignored 7 not used ignored 8 WARM START FLAG WRITE ONLY 1 9 not used ignored IS not used ignored 11 not used ignored 12 not used ignored 13 not used ignored 14 not...

Page 111: ...equired The circuitry involved is depicted on sheets nine and ten of the ACS 86 CPU Board schematic This memory overlays the upper most eight kilobytes of the one mega byte RAM memory space when 2732...

Page 112: ...outine The bootstrapping routine will permit the selective execution of additional diagnostic tests which are stored one of the mass storage devices before loading and starting the operating system Th...

Page 113: ...hen bit two of I O port 055 hex is a zero the controller operates in single density mode Double density mode is the default mode at power on and after I O port initialization Bit three of I O port 055...

Page 114: ...ot used 1 7 not used Table 4 13 I O PORT 153 IIEX FLOPPY DRIVE SELECT BIT BIT NAME TRUE 1 o BUSY 1 1 1 INDEX SEEK DMA REQ READ WRITE 1 1 I 2 TRK 0 SEEK LOST DATA RD I WRT I 1 1 3 CRC ERROR 1 1 4 SEEK...

Page 115: ...other states of these bits For further details on the programming and use of the SB S 9 consult n e 8 I I i bmil User s lIangal published by Intel document number 9SBB722 B3 Bit four of I O port 53 he...

Page 116: ...one in I O port 955 hex provides software control over this signal Current rigid disk controllers look for a zero to one transition on this bit to signal the end of the disk transfer The rigid disk d...

Page 117: ...addressed by way of four I O ports 020 o22 024 and 0 26 hex The follow ing ta b1e summar i z esthe po r t usage Port I Read I Write 1 1 020H I X I Drive and head numbers 022H I Da ta I Old cylinder nu...

Page 118: ...o do an internal recalibration of the head positioning circuitry This takes about 2 seconds to complete Bit number 7 6 5 4 3 2 1 9 I Hex 1 1 NULL 9 9 9 9 9 9 9 9 99 READ W HEADER 9 9 9 9 9 9 9 1 91 RE...

Page 119: ...f it occurred in the header the operation was aborted and the data field was not read If it occurred in the data field the data was already transferred before the error was detected RECORD NOT FOUND i...

Page 120: ...ort 024 hex Port 22 hex has multiple functions Before doing a SEEK the old cylinder is entered into this port in the same manner as the new cylinder Before doing a READ or WRITE the sector number is e...

Page 121: ...desired cylinder using the SEEK command Then a header image consisting of four bytes an 0FE hex cylinder number head number and sector number must be placed in memory and written out to the disk by th...

Page 122: ...position At the time of formatting the controller fills in every byte of the data field with n04E hexn Following the formatting of a track any attempt to read a sector on that track that has not been...

Page 123: ...ince the sector register is overwritten by data during a write to disk the sector number must be rewritten into port 022 hex before the next read or write command can be issued When switching between...

Page 124: ...g all the sync bytes are provided by the controller However when FORMATTING the drive a sync byte of 0FE hex must precede the header bytes The drive should always be selected before issuing any comman...

Page 125: ...mber and the head number needs no translation The number of the bad sector s is determined from the table on the next page This gives the range in bytes for each sector relative to the index pulse The...

Page 126: ...ser s Kanoal published by Intel document number 9899722 93 4 6 Parallel Interface The ACS 8699 provides a 24 bit programmable parallel interface The logic involved in this interface is shown on sheet...

Page 127: ...PERATION 1 1 1 1 2 DOUBLE DENSITY FLOPPY ENABLE 1 1 1 3 FLOPPY DISK CONTROLLER RESET 1 1 1 4 DIRECT MEMORY ACCESS SELECT 0 DMA 0 1 I 1 5 DIRECT MEMORY ACCESS SELECT 1 DMA 1 1 6 PARALLEL INTF CH A INPU...

Page 128: ...OUT J6 23 12 P 42 B 4 MODE or 1 IN or OUT J6 3 34 P 42 B 5 MODE or 1 IN or OUT J6 27 14 P 42 B 6 MODE or 1 IN or OUT J6 28 33 P 42 B 7 MODE or 1 IN or OUT J6 13 7 P 44 B MODE OUT P 42 INT J6 16 27 I P...

Page 129: ...1 DATA 2 to LP J6 26 32 4 1 DATA 3 to LP J6 25 13 5 1 DATA 4 to LP J6 23 12 6 1 DATA 5 to LP J6 30 34 7 1 DATA 6 to LP J6 27 14 8 1 DATA 7 to LP J6 28 33 9 1 DATA 8 to LP J6 14 26 1 I DATA STROBE to...

Page 130: ...ntained on an Intelligent Serial Concentrator Board One channel on the CPU board can be strapped for either synchronous or asynchronous operation The multipurpose channel on the CPU board can be strap...

Page 131: ...strapped to this channel to interface to a high speed network implemented with two twisted pairs of wires a single twisted pair of wires or a co axial cable or a special network transceiver All netwo...

Page 132: ...ble 4 27 assume that the serial interface device 8274 is operating in sixteen times X16 CLOCK mode BAUD RATE 1 DIVISOR 1 1 1 513 1 1536 1 75 1 1 24 1 1113 1 698 1 134 5 1 571 1 1513 1 512 1 31313 1 25...

Page 133: ...egister is read Initialization is accomplished according to the parameters in the register group pointed to by the Initialization Register The initialization register will be read only after the first...

Page 134: ...Buffer Address bits 8 15 IR 99DH Ch 9 Transmit Buffer Address bits 16 23 IR 99EH Ch 9 Transmit Buffer Length bits a 7 IR 99FH 1 Ch 9 Transmit Buffer Length bits 8 15 1 IR 919H I Ch 9 Receive Buffer A...

Page 135: ...location may be tested to identify an unini tialized controller or ini tializa tion in progress Version numbers are stored in a two part format The most significant five bits of the byte contain the...

Page 136: ...ling interrupts Bit three is used by the controller to report bus errors back to the 8 87 A bus error is generated by the main memory when a multi bit memory error is detected by the memory error dete...

Page 137: ...NEL LSB 1 9 TRANSMIT INTERRUPT CHANNEL i 1 10 TRANSMIT INTERRUPT channel i MSB 1 11 TRANSMIT INTERRUPT PENDING 1 12 not used 1 13 not used 1 14 not used 1 1 15 not used 1 1 Table 4 38 SERIAL CONCBN l...

Page 138: ...ore characters are transferred to the buffer Bit fil Bit 1 Bits 2 3 Bits 4 5 Bit 6 Bit 7 Bits 8 11 Bit 12 Bit 13 Bit 14 Bit 15 1 Parity enable 1 Parity even fil Illegal 1 1 Stop bit 2 1 5 Stop bits 3...

Page 139: ...OR Framing Error receive Receive Character s Ready unused always 13 unused always 13 unused always 13 Transmitter Ready unused always 13 unused always 13 unused always 13 receive none none none transm...

Page 140: ...egister containing the base addresses of the receive buffer to be used in Ring Buffer Mode The Receive Data Buffer Length Register is a sixteen bit register containing the length of the receive data b...

Page 141: ...er array to an even number This can simplify the generation and handling of the array under some languages Software interface to the Altos Intelligent Serial I O Concentrator can best be divided into...

Page 142: ...ncrement the New Command Register after setting up the other registers for each command The controller will acknowledge receipt of a command by clearing bit 7 of the command byte While there is genera...

Page 143: ...Increment nNew Command Register n Exit To receive a character in TTY mode use the following procedure Test if last command still pending exit or loop if true Test if receive character available exit o...

Page 144: ...ing procedure to check the state of the Modem status lines Test if last command still pending exit or loop if true Test if modem status changed exit or loop if false Read status test for errors Issue...

Page 145: ...rt numbers drives from one to eight and tracks from one to four Port B is assigned to I O port address IiJDB hex and is used to read the status of the tape transport These bits are summarized in Table...

Page 146: ...PE MARKER 5 TAPE PASSED EARLY END OF TAPE MARKER 6 TAPE AT LOAD POINT 7 TAPE UNIT READY Table 4 35 I O PORT lOB HEX TAPB DRrvE STATUS BIT BIT NAME TRUE MOVE TAPE REVERSE 1 1 MOVE TAPE FORWARD 1 2 MOVE...

Page 147: ...ace Interrupt Level Four 14 Multibus Interface Interrupt Level Five 15 Multibus Interface Interrupt Level Six 16 Multibus Interface Interrupt Level Seven 17 Interrupt Request from Tape Controller 18 I...

Page 148: ...PU SERIAL CHANNELS PORTS 048 04E 1 1 Table 4 37 IlASTER IftERRUPT CONTROLLER MASK REG PORT 15AD Control Register 1 BIT 1 BIT NAME 1 TRUE 1 1 1 1 o 1 INTERRUPT REQ LEVEL BIT 0 4 46 1 1 1 1 1 1 1 INTERR...

Page 149: ...SEE TABLE 4 49 1 1 1 7 NOT USED DON CARE Table 4 39 IlASTER IftERROP l ClITLR COMMAIID REG 3 PORT 1588 _ _ BIT BIT NAME ENA DIS 9 HARD DISK INTERRUPT 9 1 1 FLEXIBLE DISKETTE INTERRUPT 9 1 2 8987 INTER...

Page 150: ...47 1 9 7 COMMAND BIT 2 SEE TABLE 4 47 1 Table 4 41 SLAVB IR lERRUPT CRTLR 1 COMMAND REG 2 PORT 169B BIT BIT NAME I TRUE 1 1 1 9 READ REGISTER CMD 9 SEE TABLE 4 48 1 1 1 1 1 READ REGISTER CMD 1 SEE TAB...

Page 151: ...S INTERRUPT REQUEST 6 9 1 7 MULTIBUS INTERRUPT REQUEST 7 9 1 Table 4 43 SLAVE INTERRUPT CftLR 2 MASK REG PORT 6AB Control Register 1 BIT BIT NAME TRUE INTERRUPT REQ LEVEL BIT 9 4 46 1 1 INTERRUPT REO...

Page 152: ...ARE Table 4 45 SLAVE IftERRUPT CR rLR 2 COMMARD REG 3 PORT 1688 BIT 2 BIT 1 BIT 9 INTERRUPT REQUEST LEVEL ACTED UPON 1 1 9 9 9 INTERRUPT REQUEST LEVEL ZERO 1 1 9 9 1 INTERRUPT REQUEST LEVEL ONE 1 9 1...

Page 153: ...LEAR 1 1 1 ROTATE ON SPECIFIC EOI 1 1 0 SET PRIORITY COMMAND 0 1 0 NO OPERATION Table 4 47 IftERRUPT CONTROLLER COMMAIIDS Uses Interrupt Request Level Bits Table 46 1 BIT 1 1 BIT 0 1 READ REGISTER COM...

Page 154: ...ect lthe integrity of the ACS 8699 the operating system and the other users that may be using the system the Multibus interface does not permit bus masters external to the ACS 8699 to access any I O p...

Page 155: ...ECS Address Lines ADR through AD13 Data Lines DAT through DATF Control Lines IORC IOWC MRDC MWTC INTA and XACK Interrupt Lines INT through INT7 Clock Lines BCLK and CCLK System Initialization Line INI...

Page 156: ...anaing weight 89 Pounds Shipping weight Front Panel Controls AC ON OFF Switch RESET Switch Rear Panel Connections AC Power Fuse Console RS 232C Connectors DB 25 Parallel Interface Connector DB 37 Mult...

Page 157: ...nel Connections AC Power Fuse Expansion Connectors Depends on peripherals used refer to Main System Connectors Maximum AC Inrush Current 6 A at 115 V 69 Hz 3 sec Maximum Input Power 3 A at 115 V 69 Hz...

Page 158: ...86rara system Single User CP M 86 Multiple User XENIX OASIS 86 MP M 86 Altos Computer Systems offers the follow ing languages for support of end user applications on the ACS 86rara system CIS COBOL R...

Page 159: ...ON lAX DESCRIBE FEATURES AU W IMPLEMENTED QB W AVAILABLE QB AC S ti U SYSTEII WARNING IL O PORTS REFERENCED Di THIS SPECIFICATION IIAX l l AGREE li ID D B IL O PORTS DEF INED Di D B SECTION L 2 m D B...

Page 160: ...drives This jumper sets the cylinder number at which write precompensation takes place at cylinder 128 for the Shugart drives and 256 for the Quantum Data is stored on the disks in blocks or sectors o...

Page 161: ...r on before any disk access is attempted and thereafter as part of the error recovery routine A recal requires about ISms Quantum to l8ms Shugart per cylinder for a maximum time of about 8 seconds for...

Page 162: ...eady is true Normally being READY indicates that the drive is ready to be read from or written to but a special case exists with the Shugart drives upon being powered on these drives require a two min...

Page 163: ...of carrying out an operation This signal will be a B at the completion of an operation Status byte Port B23H Bit 1 Mnemonic 1 Meaning 1 1 7 1 RDY 1 Selected drive is ready 6 1 WR FLT 1 Write fault fr...

Page 164: ...e formatting and then restored afterward The formatting procedure is as follows first the heads must be positioned to the desired cylinder using the SEEK command Then a header image consisting of four...

Page 165: ...wing the formatting of a track any attempt to read a sector on that track that has not been specifically written to will result in a record not found RNF as the sync bytes will be missing for these se...

Page 166: ...n drives even if a seek is not necessary port 022H must be reloaded with the new cylinder number To read a sector prepare a buffer area in main memory to which the data from disk can be placed Next pr...

Page 167: ...oller will wait until the selected drive becomes ready before the operation is carried out Then at the completion of the operation an interrupt is generated RESET does not generate an interrupt neithe...

Page 168: ...izes only the sector number needs to be deciphered The cylinder number is the same as Shugart s track number and the head number needs no translation The number of the bad sector s is determined from...

Page 169: ...ee ALTOS Format for Hard Disk Systems 11 19 80 Another approach is to assign dummy files to the sectors that are bad so that the operating system would not try to access them DISK DRIVE SPECIFICATIONS...

Page 170: ...for 256 byte se ctors or 1 1 FE 17 times for 512 byte 1 1 cylinder byte sectors during format 1 1 head byte 1 1 sector byte 2 I CRC bytes 1 3 1 3 3 1 1 12 1 3 3 written out during 1 1 1 A1 a write ope...

Page 171: ...e invaluable in running diagnostics on the drive controller 2 Status bits TASK COMPLETE BAD SECTOR RNF and CRC ERR do not get cleared by reading status unless TASK COMPLETE is true at the beginning of...

Page 172: ...IOAL S IOR 7 SYSTBJI SPECS cylinder should be there prior to SEEKING and sector number prior to a READ or WRITE This needs to be adhered to even during error recovery 11 05 81 WS Specification Revisio...

Page 173: ...N lAX DESCRIBE FEATURES BAT ARB BQ IMPLEMENTED OB BQ AVAILABLE mI ACa ana SYSTEM WARNING un PORTS REFERENCED IB TlI IS SPECIFICATION IIAX BQ AGREE lil ll B K un PORTS DEFINED IB U SECTION L 2 D B AkS...

Page 174: ...PRELIIIIllARY 8688 USER IIAIIOAL SBCTIO 7 SYSTEII SPECS Intelligent I O Controller Specification Date 1 28 82 By Norm Kelly Specification Revision 4 2 May 27 1982 Page 118...

Page 175: ...re timely fashion FUNCTIONAL DESCRIPTION The Intelligent I O controller consists of a Z80A microprocessor four Z80A SIO dual serial controllers 4KBytes of EPROM 2 Kbytes of static ram 2 AM9513 timer I...

Page 176: ...te vectors and that the Z80A is programmed for interrupt MODE 2 Two other interrupt sources are tied to the NMI pin These two sources consist of a decoded address from the host processor expected to b...

Page 177: ...rd baud rates between 5 baud and 38 4 Kbaud The divisors to be used for these rates are listed in the table below BAUD RATE 38 4 K 19 2 K 96 72 48 36 24 2 l8 l2 6 3 15 135 ll 75 5 DIVISOR 3 6 12 16 24...

Page 178: ...E is used to generate the upper 8 address lines A16 A23 while a bit out of the control port is used for address bit 15 This allows the Intelligent I O to access all of the memory in the Mul tibus memo...

Page 179: ...al Channel 6 Data Register Command Register Serial Channel 7 Data Register Command Register Timer 9513 0 Data Register Command Register Timer 9513 1 Data Register Command Register Control Port write o...

Page 180: ...BII SPBCS SERIAL CHANNEL DESCRIPTIONS Serial Channel SIO Port AM9513 Timer Priority t iJ 1 2 3 4 5 6 7 t iJ 1 1 2 2 3 3 A B A B A B A B Specification Revision 4 2 May 27 1982 t iJ t iJ t iJ B B 1 1 1...

Page 181: ...tibus This bit is used to generate an interrupt to the host processor Since the interrupts are edge triggered this bit should be toggled to guarantee that a new interrupt is seen by the host This bit...

Page 182: ......

Page 183: ...nty will not be effective if in the opinion of Altos Computer Systems the Altos product has been damaged by aCCident misuse misapplication or as a result of service or modification by other than an au...

Page 184: ...in the following procedure 1 Contact your Author ized Reseller for assistance They will be able to fill most of your repair or service needs If your Authorized Reseller is unable to assist you and yo...

Page 185: ...r of your company and name of a responsible technical person whom Altos Customer Service may contact in the event of any question or problems 3 Ship defective Altos computer in original shipping conta...

Page 186: ......

Page 187: ...M 8688 OSER IIAIIOAL APP B TROUBLB SBOOTIBG APPDDIX B TROUBLB SBOOTIBG PROCEDURES THESE PROCEDURES WERE IN DEVELOPMENT AT THE TI ME TH IS REVISON WAS PRINTED Revision B March 22 1982 PILB APPAl 3 19 8...

Page 188: ......

Page 189: ...L APP C CORPIGORATIORS APPBRDIX C COIlllOR CRIf TBRIIIIIAL AJID PIlIll UR III tBRPACB CORPIGURATIOllS THESE PROCEDURES WERE IN DEVELOPMENT AT THE TIME THIS REVISON WAS PRINTED Revision B March 22 1982...

Page 190: ......

Page 191: ...8688 OSER MAIIOAL APP D PIIIHIBG PCB S APPBlmIX D IBSDucrIOIIS FOR PIlIIIIBG CIRCUIT BOARDS THESE PROCEDURES WERE IN DEVELOPMENT AT THE TIME THIS REVISON WAS PRINTED Revision B March 5 1982 PILB APPD2...

Page 192: ......

Page 193: ...PRBLIM 8688 OSBR IIAIIOAL APP B IlAmIX IIAPS APPBRDIX B IlAmIX IIAPS THESE MATRIX MAPS WERE IN DEVELOPMENT AT THE TIME THIS REVISON WAS PRINTED Revision B March 22 1982 FILS APPB1 3 19 82 B 1...

Page 194: ......

Page 195: ...ELl 8688 OSER RABOAL APP P SCBBIIA lICS APPBRDIX P SCBBllA2IIC DIAGRAIIS THESE SCHEMATIC DIAGRAMS WERE IN DEVELOPMENT AT THE TIME THIS REVISON WAS PRINTED Revision B March 22 1982 PILB APPP1 3 19 82 P...

Page 196: ......

Page 197: ...8688 OSER IWIUAL APP G IlAIlftBRAllCB APPBRDIX G PRBVBftIVB IlAIlftBDIICB PROCBDURBS THESE PROCEDURES WERE IN DEVELOPMENT AT THE TIME THIS REVISON WAS PRINTED Revision B March 22 1982 FILB APPG1 3 19...

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Page 200: ...Altos Computer Systems World Headquarters 2360 Bering Drive San Jose CA 95131 U S A 408 946 6700 Telex 171562 ALTOS SJN I...

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