Chapter 3: Memory Blocks in Arria II Devices
3–7
Memory Features
December 2010
Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
shows the address clock enable waveform during write cycle for M9K and
M144K blocks.
shows the address clock enable waveform during the write cycle for
MLABs.
Figure 3–5. Address Clock Enable During Write Cycle Waveform for M9K and M144K Blocks
inclock
wren
wraddress
a0
a1
a2
a3
a4
a5
a6
an
a0
a4
a5
latched address
(inside memory)
addressstall
a1
data
00
01
02
03
04
05
06
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
04
XX
00
03
01
XX
02
XX
XX
XX
05
Figure 3–6. Address Clock Enable During Write Cycle Waveform for MLABs
inclock
wren
wraddress
a0
a1
a2
a3
a4
a5
a6
an
a0
a4
a5
latched address
(inside memory)
addressstall
a1
data
00
01
02
03
04
05
06
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
04
XX
00
03
01
XX
02
XX
XX
XX
05