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5–40

Chapter 5: Clock Networks and PLLs in Arria II Devices

PLLs in Arria II Devices

Arria II Device Handbook Volume 1: Device Interfaces and Integration

December 2010

Altera Corporation

Manual Clock Switchover Mode

In manual clock switchover mode, the

clkswitch

signal controls whether

inclk0

or

inclk1

is selected as the input clock to the PLL. By default,

inclk0

is selected. A

low-to-high transition on

clkswitch

and being held high for at least three

inclk

cycles

begins a clock switchover event. You must bring the

clkswitch

signal back low again

to perform another switchover event in the future. If you do not require another
switchover event in the future, you can leave

clkswitch

in a logic high state after the

initial switch. Pulsing

clkswitch

high for at least three

inclk

cycles performs another

switchover event. If

inclk0

and

inclk1

are different frequencies and are always

running, the

clkswitch

minimum high time must be greater than or equal to three of

the slower frequency

inclk0

and

inclk1

cycles.

shows a block diagram of the manual switchover circuit.

f

For more information about PLL software support in the Quartus II software, refer to
the

Phase-Locked Loops (ALTPLL) Megafunction User Guide

Clock Switchover Guidelines

Use the following guidelines when implementing clock switchover in Arria II PLLs.

■

Automatic clock switchover requires that the

inclk0

and

inclk1

frequencies be in

100% (2×) of each other. Failing to meet this requirement causes the

clkbad[0]

and

clkbad[1]

signals to not function properly.

■

When you use manual clock switchover mode, the difference between

inclk0

and

inclk1

can be more than 100% (2×). However, differences in frequency, or phase of

the two clock sources, or both, are likely to cause the PLL to lose lock. Resetting the
PLL ensures that the correct phase relationships are maintained between the input
and output clocks.

1

Both

inclk0

and

inclk1

must be running when the

clkswitch

signal goes

high to start the manual clock switchover event. Failing to meet this
requirement causes the clock switchover to not function properly.

■

Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. The low-bandwidth PLL reacts more slowly than
the high-bandwidth PLL to reference the input clock changes. When the
switchover event occurs, a low-bandwidth PLL propagates the stopping of the
clock to the output more slowly than the high-bandwidth PLL. However, be aware
that the low-bandwidth PLL also increases lock time.

Figure 5–33. Manual Clock Switchover Circuitry in PLLs for Arria II Devices

n Counter

PFD

fbclk

clkswitch

inclk0

inclk1

muxout

r

efclk

Clock Switch

Control Logic

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Summary of Contents for EP2AGX125

Page 1: ...ection includes the following chapters Chapter 1 Overview for the Arria II Device Family Chapter 2 Logic Array Blocks and Adaptive Logic Modules in Arria II Devices Chapter 3 Memory Blocks in Arria II Devices Chapter 4 DSP Blocks in Arria II Devices Chapter 5 Clock Networks and PLLs in Arria II Devices Revision History Refer to each chapter for its own specific revision history For information on ...

Page 2: ...I 2 Section I Device Core for Arria II Devices Revision History Arria II Device Handbook Volume 1 Device Interfaces and Integration December 2010 Altera Corporation ...

Page 3: ...ice family architecture features a low power programmable logic engine and streamlined transceivers and I Os Common interfaces such as the Physical Interface for PCI Express PIPE PCIe Ethernet and DDR3 memory are easily implemented in your design with the Quartus II software the SOPC Builder design software and a broad library of hard and soft intellectual property IP solutions from Altera The Arr...

Page 4: ...gh bandwidth system interfaces Up to 726 user I O pins arranged in up to 20 modular I O banks that support a wide range of single ended and differential I O standards High speed LVDS I O support with serializer deserializer SERDES and dynamic phase alignment DPA circuitry at data rates from 150 Mbps to 1 25 Gbps Low power Architectural power reduction techniques Typical physical medium attachment ...

Page 5: ...or 12 8 or 12 User I O Banks 5 6 6 6 8 8 12 12 16 or 20 8 16 or 20 8 16 or 20 High Speed LVDS SERDES up to 1 25 Gbps 7 8 24 or 28 8 24 or 28 24 28 or 32 24 28 32 28 or 48 24 or 48 42 or 86 0 8 42 or 86 0 8 42 or 86 Notes to Table 1 1 1 The total number of transceivers is divided equally between the left and right side of each device except for the devices in the F780 package These devices have eig...

Page 6: ... 8 EP2AGX95 260 57 RD or eTX 56 RX TX or eTX 8 372 85 RD or eTX 84 RX TX or eTX 12 452 105 RD or eTX 104 RX TX or eTX 12 EP2AGX125 260 57 RD or eTX 56 RX TX or eTX 8 372 85 RD or eTX 84 RX TX or eTX 12 452 105 RD or eTX 104 RX TX or eTX 12 EP2AGX190 372 85 RD or eTX 84 RX TX or eTX 12 612 145 RD or eTX 144 RX TX or eTX 16 EP2AGX260 372 85 RD eTX 84 RX TX or eTX 12 612 145 RD eTX 144 RX TX or eTX 1...

Page 7: ...buffers without RD OCT support for row I O banks or true LVDS input buffers without RD OCT support for column I O banks 3 eTX Emulated LVDS output buffers either LVDS_E_3R or LVDS_E_1R 4 The LVDS RX and TX channels are equally divided between the left and right sides of the device 5 The LVDS channel count does not include dedicated clock input pins 6 For Arria II GZ 780 pin FBGA package the LVDS c...

Page 8: ...for 6 375 Gbps speeds Figure 1 1 and Figure 1 2show an overview of the Arria II GX and Arria II GZ device architecture respectively Figure 1 1 Architecture Overview for Arria II GX Devices Arria II GX FPGA Fabric Logic Elements DSP Embedded Memory Clock Networks All the blocks in this graphic are for the largest density in the Arria II GX family The number of blocks can vary based on the density o...

Page 9: ...or superior noise immunity Calibration circuitry for transmitter and receiver on chip termination OCT resistors Figure 1 2 Architecture Overview for Arria II GZ Device Notes to Figure 1 2 1 Not available for 780 pin FBGA package 2 Not available for 780 pin and 1152 pin FBGA packages General Purpose I O and Memory Interface 400 Mbps 6 375 Gbps CDR based Transceiver General Purpose I O and 150 Mbps ...

Page 10: ...tion compliant to PCIe Base Specification 2 0 that includes PHY MAC Data Link and Transaction layer circuitry embedded in the PCIe hard IP blocks PCIe Gen1 has 1 2 4 and 8 lane configurations PCIe Gen2 has 1 2 and 4 lane configurations PCIe Gen2 does not support 8 lane configurations Built in circuitry for electrical idle generation and detection receiver detect power state transitions lane revers...

Page 11: ...rations 512 byte payload Compliant to PCIe Gen1 at 2 5 Gbps and PCIe Gen2 at 5 0 Gbps Logic Array Block and Adaptive Logic Modules Logic array blocks LABs consists of 10 ALMs carry chains shared arithmetic chains LAB control signals local interconnect and register chain connection lines ALMs expand the traditional four input LUT architecture to eight inputs increasing performance by reducing logic...

Page 12: ...r Verilog HDL source code I O Features Contains up to 20 modular I O banks All I O banks support a wide range of single ended and differential I O standards listed in Table 1 7 Supports programmable bus hold programmable weak pull up resistors and programmable slew rate control For Arria II devices calibrates OCT or driver impedance matching for single ended I O standards with one OCT calibration ...

Page 13: ... data rate SGMII and GbE Emulated LVDS output buffers use two single ended output buffers with an external resistor network to support LVDS mini LVDS BLVDS only for Arria II GZ devices and RSDS standards Clock Management Provides dedicated global clock networks GCLKs regional clock networks RCLKs and periphery clock networks PCLKs that are organized into a hierarchical structure that provides up t...

Page 14: ...ia II Devices chapter Nios II Arria II devices support all variants of the NIOS II processor Nios II processors are supported by an array of software tools from Altera and leading embedded partners and are used by more designers than any other configurable processor Configuration Features Configuration Supports active serial AS passive serial PS fast passive parallel FPP and JTAG configuration sch...

Page 15: ...iguration process recover from an error condition by reverting back to a safe configuration image and provides error status information SEU Mitigation Offers built in error detection circuitry to detect data corruption due to soft errors in the configuration random access memory CRAM cells Allows all CRAM contents to be read and verified to match a configuration computed cyclic redundancy check CR...

Page 16: ...cific device options N Lead free devices ES Engineering sample EP2AGX EP2AGZ C Transceiver Count C 4 D 8 E 12 F 16 H 24 C Commercial temperature tJ 0 C to 85 C I Industrial temperature tJ 40 C to 100 C Table 1 10 Document Revision History Date Version Changes December 2010 4 0 Updated for the Quartus II software version 10 0 release Added information about Arria II GZ devices Updated Table 1 1 Tab...

Page 17: ...s adaptive logic modules ALMs that you can configure to implement logic functions arithmetic functions and register functions This chapter contains the following sections Logic Array Blocks on page 2 1 Adaptive Logic Modules on page 2 5 Logic Array Blocks Each LAB consists of ten ALMs various carry chains shared arithmetic chains LAB control signals local interconnect and register chain connection...

Page 18: ...B and includes all LAB features Figure 2 2 shows an overview of LAB and MLAB topology f For more information about MLABs refer to the TriMatrix Memory Blocks in Arria II Devices chapter Figure 2 2 LAB and MLAB Structure in Arria II Devices Note to Figure 2 2 1 You can use an MLAB ALM as a regular LAB ALM or configure it as a dual port SRAM MLAB LAB LUT based 64 x 1 Simple dual port SRAM LUT based ...

Page 19: ... memory blocks or DSP blocks from the left or right can also drive the LAB s local interconnect through the direct link connection Each LAB can drive 30 ALMs through fast local and direct link interconnects Ten ALMs are in any given LAB and ten ALMs are in each of the adjacent LABs Figure 2 3 shows the direct link connection which connects adjacent LABs memory blocks DSP blocks or I O element IOE ...

Page 20: ...locks using two clock sources and three clock enable signals Each clock and clock enable signals are linked For example any ALM in a particular LAB using the labclk1 signal also uses the labclkena1 signal If the LAB uses both the rising and falling edges of a clock it also uses two LAB wide clock signals De asserting the clock enable signal turns off the corresponding LAB wide clock The LAB row cl...

Page 21: ...d certain 7 input functions In addition to the ALUT based resources each ALM contains two programmable registers two dedicated full adders a carry chain a shared arithmetic chain and a register chain Through these dedicated resources an ALM can efficiently implement various arithmetic functions and shift registers Each ALM drives all types of interconnects local row column carry chain shared arith...

Page 22: ...the outputs of an ALM Each ALM has two sets of outputs that drive the local row and column routing resources The LUT adder or register output can drive the ALM outputs refer to Figure 2 6 For each set of output drivers two ALM outputs can drive column row or direct link routing connections and one of these ALM outputs can also drive local interconnect resources The LUT or adder can drive one outpu...

Page 23: ... Extended LUT Arithmetic Shared Arithmetic LUT Register The Quartus II software and other supported third party synthesis tools in conjunction with parameterized functions such as the library of parameterized modules LPM functions automatically choose the appropriate mode for common functions such as counters adders subtractors and arithmetic functions Each mode uses the ALM resources differently ...

Page 24: ...inations in normal mode Normal mode provides complete backward compatibility with 4 input LUT architectures Figure 2 7 ALM in Normal Mode Note 1 Note to Figure 2 7 1 Combinations of functions with fewer inputs than those shown are also supported For example combinations of functions with the following number of inputs are supported 4 and 3 3 and 3 3 and 2 and 5 and 2 6 Input LUT dataf0 datae0 data...

Page 25: ... be placed in one ALM to make efficient use of device resources In addition you can manually control resource usage by setting location assignments Any 6 input function can be implemented using inputs dataa datab datac datad and either datae0 anddataf0 or datae1 and dataf1 If datae0 and dataf0 are utilized the output is driven to register0 and or register0 is bypassed and the data drives out to th...

Page 26: ... In this mode if the 7 input function is unregistered the unused eighth input is available for register packing Functions that fit into the template as shown in Figure 2 9 often appear in designs as if else statements in Verilog HDL or VHDL code Figure 2 9 Template for Supported 7 Input Functions in Extended LUT Mode Note to Figure 2 9 1 If the 7 input function is unregistered the unused eighth in...

Page 27: ...ut along with combinational logic outputs The adder output is ignored in this operation Using the adder with combinational logic output provides resource savings of up to 50 for functions that can use this mode Arithmetic mode also offers clock enable counter enable synchronous up and down control add and subtract control synchronous clear and synchronous load The LAB local interconnect data input...

Page 28: ...ains longer than 20 ALMs 10 ALMs in arithmetic or shared arithmetic mode by linking LABs together automatically To enhance fitting a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks A carry chain can continue as far as a full column To avoid routing congestion in one small area of the device when a high fan in arithmetic function is implement...

Page 29: ... an adder tree by reducing the number of summation stages required to implement an adder tree Figure 2 11 shows the ALM using this feature You can find adder trees in many different applications For example the summation of the partial products in a logic based multiplier can be implemented in a tree structure Another example is a correlator function that can use a large adder tree to sum filtered...

Page 30: ... 20 ALMs 10 ALMs in arithmetic or shared arithmetic mode by linking LABs together automatically To enhance fitting a long shared arithmetic chain runs vertically allowing fast horizontal connections to the TriMatrix memory and DSP blocks A shared arithmetic chain can continue as far as a full column Similar to the carry chains the top and bottom half of shared arithmetic chains in alternate LAB co...

Page 31: ...es its clock clock enable and asynchronous clear sources with the top dedicated register Figure 2 12 shows the register constructed using two combinational blocks in the ALM Figure 2 13 shows the ALM in LUT Register mode Figure 2 12 LUT Register from Two Combinational Blocks 4 input LUT 5 input LUT clk aclr datain datac sclr sumout Master latch Slave latch combout LUT regout sumout combout Figure ...

Page 32: ...nnect resources refer to Figure 2 14 The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance 1 For more information about register chain interconnect refer to ALM Interconnects on page 2 17 Figure 2 14 Register Chain in an LAB Note 1 Note to Figure 2 14 1 You can use the combinational or adder logic to implement an unrelated un registered fun...

Page 33: ...synchronous clear function You can achieve the register preset through the Quartus II software s NOT gate push back logic option Each LAB supports up to two clears Arria II devices provide a device wide reset pin DEV_CLRn that resets all registers in the device An option set before compilation in the Quartus II software enables this pin This device wide reset overrides all other control signals LA...

Page 34: ...ftware automatically promotes register level clock enable signals to the LAB level All registers within the LAB that share a common clock and clock enable are controlled by a shared gated clock To take advantage of these clock enables use a clock enable construct in your HDL code for the registered logic f For more information about implementing static and dynamic power consumption within the LAB ...

Page 35: ...he latest version of device specifications before relying on any published information and before placing orders for products or services 3 Memory Blocks in Arria II Devices This chapter describes the Arria II device memory blocks that include 640 bit memory logic array blocks MLABs 9 Kbit M9K blocks and 144 Kbit M144K blocks MLABs are optimized to implement filter delay lines small FIFO buffers a...

Page 36: ...9 512 16 512 18 256 32 256 36 8K 1 4K 2 2K 4 1K 8 1K 9 512 16 512 18 256 32 256 36 16K 8 16K 9 8K 16 8K 18 4K 32 4K 36 2K 64 2K 72 Parity bits v v v v v Byte enable v v v v v Packed mode v v v Address clock enable v v v v v Single port memory v v v v v Simple dual port memory v v v v v True dual port memory v v v Embedded shift register v v v v v ROM v v v v v FIFO buffer v v v v v Simple dual por...

Page 37: ...Outputs set to old data Outputs set to don t care Outputs set to old data or new data Outputs set to old data or new data Mixed port read during write Outputs set to old data or don t care Outputs set to old data or don t care Outputs set to old data or don t care ECC Support Soft IP support using the Quartus II software Soft IP support using the Quartus II software Built in support in 64 wide sim...

Page 38: ...For example if you use a RAM block in 18 mode byteena 01 data 8 0 is enabled and data 17 9 is disabled Similarly if byteena 11 both data 8 0 and data 17 9 are enabled Byte enables are active high 1 You cannot use the byte enable feature when using the error correction coding ECC feature on M144K blocks Figure 3 1 shows how the write enable wren and byte enable byteena signals control the operation...

Page 39: ... and using the MSB of the address to distinguish between the two logical RAMs The size of each independent single port RAM must not exceed half of the target block size Address Clock Enable Support Arria II memory blocks support address clock enable which holds the previous address value for as long as the signal is enabled addressstall 1 When you configure the memory blocks in dual port mode each...

Page 40: ...ess clock enable Figure 3 4 shows the address clock enable waveform during the read cycle Figure 3 3 Address Clock Enable address 0 address N addressstall clock 1 0 address 0 register address N register address N address 0 1 0 Figure 3 4 Address Clock Enable During Read Cycle Waveform inclock rden rdaddress q synch a0 a1 a2 a3 a4 a5 a6 q asynch an a0 a4 a5 latched address inside memory dout0 dout1...

Page 41: ...m for M9K and M144K Blocks inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address inside memory addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 XX 04 XX 00 03 01 XX 02 XX XX XX 05 Figure 3 6 Address Clock Enable During Write Cycle Waveform for MLABs inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0...

Page 42: ...hows a functional waveform showing this functionality You can selectively enable asynchronous clears per logical memory using the RAM MegaWizard Plug In Manager f For more information about the RAM MegaWizard Plug In Manager refer to the Internal Memory RAM and ROM Megafunction User Guide Error Correction Code Support Arria II GZ M144K blocks have built in support for ECC when in 64 wide simple du...

Page 43: ...ECC is engaged Figure 3 8 shows a diagram of the ECC block of the M144K block Table 3 3 Truth Table for ECC Status Flags in Arria II Devices Status eccstatus 2 eccstatus 1 eccstatus 0 No error 0 0 0 Single error and fixed 0 1 1 Double error and no fix 1 0 1 Illegal 0 0 1 Illegal 0 1 0 Illegal 1 0 0 Illegal 1 1 X Figure 3 8 ECC Block Diagram of the M144K Block Data Input 64 64 64 8 72 SECDED Encode...

Page 44: ...ld data or don t care in the RAM MegaWizard Plug In Manager in the Quartus II software For more information about this behavior refer to Read During Write Behavior on page 3 21 1 When using the memory blocks in ROM single port simple dual port or true dual port mode you can corrupt the memory contents if you violate the setup or hold time on any of the memory block input registers This applies to ...

Page 45: ...a don t care value Table 3 4 lists the possible port width configurations for memory blocks in single port mode Figure 3 10 shows timing waveforms for read and write operations in single port mode with unregistered outputs for M9K and M144K blocks Registering the M9K and M144K block outputs delay the q output by one clock cycle Table 3 4 Port Width Configurations for MLABs M9K and M144K Blocks Sin...

Page 46: ... one read and one write operation to different locations at the same time The write operation occurs on port A the read operation occurs on port B Figure 3 12 shows a simple dual port configuration Simple dual port RAM supports input and output clock mode in addition to the read and write clock mode Figure 3 11 Timing Waveform for Read Write Operations for MLABs Single Port Mode clk_a wrena addres...

Page 47: ...nable and read enable signals Read during write operations to the same address can either output a don t care or old data value MLABs only support a write enable signal Read during write behavior for the MLABs can be either a don t care or old data value The available choices depend on the configuration of the MLAB Table 3 5 M9K Block Mixed Width Configurations Simple Dual Port Mode Read Port Writ...

Page 48: ...ows the timing waveforms for read and write operations in simple dual port mode with unregistered outputs in the MLAB The write operation is triggered by the falling clock edges Figure 3 13 Simple Dual Port Timing Waveforms for M9K and M144K Blocks wrclock wren wraddress rdclock an 1 an a0 a1 a2 a3 a4 a5 a6 q asynch rden rdaddress bn b0 b1 b2 b3 doutn 1 doutn dout0 din 1 din din4 din5 din6 data Fi...

Page 49: ...ual port RAM configuration The widest bit configuration of the M9K and M144K blocks in true dual port mode are M9K 512 16 bit or 512 18 bit with parity M144K 4K 32 bit or 4K 36 bit with parity Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block Because true dual port RAM has outputs on two ports its maximum...

Page 50: ...ny memory location at any time from either port When accessing the same memory location from both ports you must avoid possible write conflicts A write conflict happens when you attempt to write to the same address location from both ports at the same time This results in unknown data being stored to that address location Conflict resolution circuitry is not built into the Arria II memory blocks Y...

Page 51: ...andom number generators multi channel filtering and auto and cross correlation functions These and other DSP applications require local data storage traditionally implemented with standard flipflops that quickly exhaust many logic cells for large shift registers A more efficient alternative is to use embedded memory as a shift register block which saves logic cell and routing resources The size of...

Page 52: ...ed The ROM read operation is identical to the read operation in the single port RAM configuration FIFO Mode All memory blocks support FIFO mode MLABs are ideal for designs with many small shallow FIFO buffers To implement FIFO buffers in your design you can use the FIFO MegaWizard Plug In Manager in the Quartus II software Both single and dual clock asynchronous FIFOs are supported f For more info...

Page 53: ...ronous clears are supported only for output latches and output registers on both ports Input and Output Clock Mode Arria II memory blocks can implement input and output clock mode for true and simple dual port memories In this mode an input clock controls all registers related to the data input to the memory block including data address byte enables read enables and write enables An output clock c...

Page 54: ...ing into account both speed and size constraints placed on your design For example the Quartus II software may spread out memory across multiple memory blocks when resources are available to increase the performance of your design You can manually assign memory to a specific block size using the RAM MegaWizard Plug In Manager MLABs can implement single port SRAM through emulation with the Quartus ...

Page 55: ...ble new data mode or flow through old data mode or don t care mode In new data mode the new data is available on the rising edge of the same clock cycle on which it was written In old data mode the RAM outputs reflect the old data at that address before the write operation proceeds In don t care mode the RAM outputs don t care values for a read during write operation Figure 3 20 shows sample funct...

Page 56: ...ed Port Read During Write Mode This mode applies to a RAM in simple or true dual port mode which has one port reading and the other port writing to the same address location with the same clock In this mode you can choose old data or don t care value as the output In old data mode a read during write operation to different ports causes the RAM outputs to reflect the old data at that address locati...

Page 57: ... of mixed port read during write behavior for old data mode in MLABs Figure 3 24 shows a sample functional waveform of mixed port read during write behavior for don t care mode in MLABs Figure 3 23 MLABs Mixed Port Read During Write Old Data Mode clk_a wrena data_in wraddress A1 byteena_a q_b registered A0 rdaddress A1 A0 AAAA BBBB CCCC DDDD EEEE FFFF A0 old data A1 old data DDDD AABB AAAA 11 01 1...

Page 58: ... read during write is not supported when two different clocks are used in a dual port RAM The output value is unknown during a dual clock mixed port read during write operation Figure 3 25 M9K and M144K Mixed Port Read During Write Old Data Mode clk_a b wrena rdenb address_a A0 A1 byteena 11 01 10 11 data_a AAAA BBBB CCCC DDDD EEEE FFFF q_b_ asynch A0 old data A1 old data DDDD EEEE AABB AAAA addre...

Page 59: ...tialization using a mif You can create mif files in the Quartus II software and specify their use with the RAM MegaWizard Plug In Manager when instantiating a memory in your design Even if a memory is pre initialized for example using a mif it still powers up with its outputs cleared f For more information about mif files refer to the Internal Memory RAM and ROM Megafunction User Guide and the Qua...

Page 60: ...1 and Table 3 2 Updated Figure 3 10 Figure 3 12 and Figure 3 16 Added Table 3 6 and Table 3 8 Added Figure 3 10 Figure 3 15 Figure 3 21 Figure 3 23 and Figure 3 24 Added Error Correction Code Support section Minor text edit November 2009 2 0 Updated for Arria II GX v9 1 release Updated Table 3 2 Updated Figure 3 16 Minor text edit June 2009 1 1 Updated Table 3 1 Updated Byte Enable Support Simple ...

Page 61: ...plement one of several operational modes to suit your application The built in shift register chain multipliers and adders subtractors minimize the amount of external logic to implement these functions resulting in efficient resource utilization and improved performance and data throughput for DSP applications These DSP blocks are the fourth generation of hardwired fixed function silicon blocks de...

Page 62: ...lined multiplication operations Natively supported 9 bit 12 bit 18 bit and 36 bit word lengths Natively supported 18 bit complex multiplications Efficiently supported floating point arithmetic formats 24 bits for single precision and 53 bits for double precision Signed and unsigned input support Built in addition subtraction and accumulation units to efficiently combine multiplication results Casc...

Page 63: ...sion Multiplier Adder Mode Four Multiplier Adder Mode 9 9 Multipliers 12 12 Multipliers 18 18 Multipliers 18 18 Complex 36 36 Multipliers 18 36 Multipliers 18 18 Multipliers Arria II GX EP2AGX45 29 232 174 116 58 58 116 232 EP2AGX65 39 312 234 156 78 78 156 312 EP2AGX95 56 448 336 224 112 112 224 448 EP2AGX125 72 576 432 288 144 144 288 576 EP2AGX190 82 656 492 328 164 164 328 656 EP2AGX260 92 736...

Page 64: ...6 multipliers as described in later sections Each Arria II DSP block contains four two multiplier adder units 2 two multiplier adder units per half block Therefore there are eight 18 18 multiplier functionalities per DSP block For a detailed diagram of the DSP block refer to Figure 4 5 on page 4 8 Following the two multiplier adder units are the pipeline registers the second stage adders and an ou...

Page 65: ...ast one set of the registers If the register is not enabled an infinite loop occurs To support FIR like structures efficiently a major addition to the DSP block in Arria II devices is the ability to propagate the result of one half block to the next half block completely in the DSP block without additional soft logic overhead This is achieved by the inclusion of a dedicated addition unit and routi...

Page 66: ...resources and providing higher system performance Figure 4 4 shows the optional rounding and saturation unit This unit provides a set of commonly found arithmetic rounding and saturation functions in signal processing In addition to the independent multipliers and sum modes you can use DSP blocks to perform shift operations DSP blocks can dynamically switch between logical shift left right arithme...

Page 67: ...lement more multipliers in an Arria II device The Quartus II software automatically places multipliers that can share the same DSP block resources in the same block Table 4 2 DSP Block Operational Modes for Arria II Devices Mode Multiplier in Width Number of Multiplier per Block Signed or Unsigned RND SAT In Shift Register Chainout Adder 1stStage Add Sub 2ndStage Add Acc Independent Multiplier 9 b...

Page 68: ...r overflow and saturate overflow 2 Block output for saturation overflow of chainout 3 When the chainout adder is not in use the second adder register banks are known as output register banks 4 You must connect the chainin port to the chainout port of the previous DSP blocks it must not be connected to general routings chainin scanina dataa_0 datab_0 dataa_1 datab_1 dataa_2 datab_2 dataa_3 scanouta...

Page 69: ... the input register of a half DSP block Figure 4 6 Input Register of Half DSP Block Note 1 Note to Figure 4 6 1 The scanina signal originates from the previous DSP block while the scanouta signal goes to the next DSP block signa signb clock 3 0 ena 3 0 aclr 3 0 scanina 17 0 dataa_0 17 0 loopback datab_0 17 0 dataa_1 17 0 datab_1 17 0 dataa_2 17 0 datab_2 17 0 dataa_3 17 0 datab_3 17 0 scanouta Del...

Page 70: ...ease the length of the shift register chain by cascading to the lower DSP blocks The dedicated shift register chain spans a single column but you can implement longer shift register chains requiring multiple columns with the regular FPGA routing resources Shift registers are useful in DSP functions such as FIR filters When implementing an 18 18 or smaller width multiplier you do not require extern...

Page 71: ...half DSP block must have the same sign representation The multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18 18 loopback and two multiplier adder modes For more information refer to Two Multiplier Adder Sum Mode on page 4 20 1 By default when the signa and signb signals are unused the Quartus II software sets the multiplier ...

Page 72: ...e chained output adder at the same time as a second level adder in chained output summation mode The output of the second stage adder has the option to go into the rounding and saturation logic unit or the output register 1 You cannot use the second stage adder independently from the multiplier and first stage adder Rounding and Saturation Stage Rounding and saturation logic units are located at t...

Page 73: ... set by the software and has the option to either drive or bypass the output registers The exception is when the block is used in shift mode where you dynamically control the output select multiplexer directly When the DSP block is configured in chained cascaded output mode both of the second stage adders are used The first adder is for performing a four multiplier adder and the second is for the ...

Page 74: ...dividual 18 18 multipliers For operand widths up to 9 bits a 9 9 multiplier is implemented For operand widths from 10 to 12 bits a 12 12 multiplier is implemented and for operand widths from 13 to 18 bits an 18 18 multiplier is implemented This is done by the Quartus II software by zero padding the LSBs Figure 4 7 Figure 4 8 and Figure 4 9 show the DSP block in the independent multiplier operation...

Page 75: ...Device Interfaces and Integration Figure 4 8 12 Bit Independent Multiplier Mode Shown for Half DSP Block 24 12 12 12 12 12 12 24 24 Input Register Bank Pipeline Register Bank Output Register Bank clock 3 0 ena 3 0 aclr 3 0 signa signb Half DSP Block dataa_0 11 0 datab_0 11 0 dataa_1 11 0 datab_1 11 0 dataa_2 11 0 datab_2 11 0 result_0 result_1 result_2 ...

Page 76: ...ltiplier inputs and results independently You can use the pipeline registers in the DSP block to pipeline the multiplier result increasing the performance of the DSP block 1 The rounding and saturation logic unit is supported for 18 bit independent multiplier mode only Figure 4 9 9 Bit Independent Multiplier Mode Shown for Half DSP Block 18 9 9 9 9 18 9 9 18 9 9 18 Input Register Bank Pipeline Reg...

Page 77: ... independent multiplier mode but uses the entire half DSP block including the dedicated hardware logic after the pipeline registers to implement the 36 36 bit multiplication operation as shown in Figure 4 10 The 36 bit multiplier is useful for applications requiring more than 18 bit precision for example for the mantissa multiplication portion of single precision and extended single precision floa...

Page 78: ... build a 54 54 bit multiplier with basic 18 18 multipliers shifters and adders To efficiently use built in shifters and adders in the Arria II DSP block a special double mode partial 54 54 multiplier is available that is a slight modification to the basic 36 36 multiplier mode as shown in Figure 4 11 and Figure 4 12 Figure 4 11 Double Mode Shown for a Half DSP Block Pipeline Register Bank Input Re...

Page 79: ... Double Mode Two Multiplier Adder Mode 36 Final Adder implemented with ALUT logic 55 72 108 result Unsigned 54 54 Multiplier 0 0 dataa 53 36 dataa 53 36 dataa 53 36 datab 53 36 dataa 35 18 datab 53 36 dataa 17 0 datab 53 36 datab 35 18 datab 17 0 clock 3 0 ena 3 0 aclr 3 0 signa signb dataa 35 18 dataa 35 18 datab 35 18 datab 17 0 datab 17 0 dataa 17 0 datab 35 18 dataa 17 0 Shifters and Adders Sh...

Page 80: ...ultiplier adder mode Figure 4 14 shows the DSP block configured in the loopback mode This mode takes the 36 bit summation result of the two multipliers and feeds back the most significant 18 bits to the input The lower 18 bits are discarded You have the option to disable or zero out the loopback data with the dynamic zero_loopback signal A logic 1 value on the zero_loopback signal selects the zero...

Page 81: ...ombination that does not violate the 36 bit maximum result is permitted for example two 16 16 signed two multiplier adders is valid 1 Two multiplier adder mode supports the rounding and saturation logic unit You can use pipeline registers and output registers in the DSP block to pipeline the multiplier adder result increasing the performance of the DSP block Figure 4 14 Loopback Mode for Half DSP ...

Page 82: ...DSP block the real part a c b d is implemented with two multipliers feeding one subtractor block and the imaginary part a d b c is implemented with another two multipliers feeding an adder block This mode automatically assumes all inputs are using signed numbers Figure 4 15 shows an 18 bit complex multiplication This mode automatically assumes all inputs are using signed numbers Equation 4 4 Compl...

Page 83: ...s The results of these two adder blocks are then summed in the second stage adder block to produce the final four multiplier adder result as shown in Equation 4 2 on page 4 4 and Equation 4 3 on page 4 5 Four multiplier adder mode supports the rounding and saturation logic unit You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier adder result incr...

Page 84: ...r 100 dB if the largest coefficient is normalized to the maximum 18 bit representation In these situations the datapath can be up to 36 bits allowing sufficient capacity for bit growth or gain changes in the signal source without loss of precision which is useful in single precision block floating point applications Figure 4 17 shows the high precision multiplier is performed in two stages The sum...

Page 85: ...t up to two independent 44 bit accumulators Use the dynamic accum_sload control signal to clear the accumulation A logic 1 value on the accum_sload signal synchronously loads the accumulator with the multiplier result only and a logic 0 enables accumulation by adding or subtracting the output of the DSP block accumulator feedback to the output of the multiplier and first stage adder Figure 4 18 Mu...

Page 86: ...shift mode between these modes with the dynamic rotate and shift control signals You can easily use the shift mode in an Arria II device with a soft embedded processor such as the Nios II processor to perform the dynamic shift and rotate operation Shift mode makes use of the available multipliers to logically or arithmetically shift left right or rotate the desired 32 bit data The DSP block is con...

Page 87: ...gister Bank dataa_0 35 18 datab_0 35 18 dataa_0 17 0 datab_0 35 18 dataa_0 35 18 datab_0 17 0 dataa_0 17 0 datab_0 17 0 Half DSP Block result 32 Shift Rotate Table 4 5 Examples of Shift Operations Example Signa Signb Shift Rotate A input B input Result Logical Shift Left LSL N Unsigned Unsigned 0 0 0 AABBCCDD 0 0000100 0 BBCCDD00 Logical Shift Right LSR 32 N Unsigned Unsigned 1 0 0 AABBCCDD 0 0000...

Page 88: ...le 4 6 lists an example of how round to nearest even mode Examples of the difference between the two modes are shown in Table 4 7 In this example a 6 bit input is rounded to 4 bits You can observe from Table 4 7 that the main difference between the two rounding options is when the residue bits are exactly half way between its nearest two integers and the LSB is zero even Table 4 6 Example of Round...

Page 89: ...ng higher flexibility You must select the 16 configurable bit positions at compile time These 16 bit positions are located at bits 21 6 for rounding and 43 28 for saturation as shown in Figure 4 20 1 For symmetric saturation the RND bit position is to determine where the LSP for the saturated data is located You can use the rounding and saturation function as described in regular supported multipl...

Page 90: ...on signa 0 signb 0 for unsigned unsigned multiplication 2 output_round Round control for first stage round saturation block output_round 1 for rounding on multiply output output_round 0 for normal multiply output 1 chainout_round Round control for second stage round saturation block chainout_round 1 for rounding on multiply output chainout_round 0 for normal multiply output 1 output_saturate Satur...

Page 91: ...is that infers the appropriate megafunction by recognizing multipliers multiplier adders multiplier accumulators and shift functions With either method the Quartus II software maps the functionality to the DSP blocks during compilation f For instructions about using the megafunctions and the MegaWizard Plug In Manager refer to the Quartus II Software Help f For more information refer to Section II...

Page 92: ...e version 10 1 release Added Arria II GZ devices information Updated DSP Block Overview Operational Modes Overview DSP Block Resource Descriptions Updated Table 4 1 Added Figure 4 3 Figure 4 7 Figure 4 11 Figure 4 15 Minor text edits July 2010 3 0 Updated for the Arria II GX v10 0 release Updated DSP Block Resource Descriptions and Second Stage Adder sections Minor text edits November 2009 2 0 Upd...

Page 93: ...latest version of device specifications before relying on any published information and before placing orders for products or services 5 Clock Networks and PLLs in Arria II Devices This chapter describes the hierarchical clock networks and phase locked loops PLLs which have advanced features in Arria II devices that provide dedicated global clock networks GCLKs regional clock networks RCLKs and pe...

Page 94: ...uts programmable logic device PLD transceiverinterface clocks and logic array CLK 0 15 p and CLK 0 15 n pins PLL clock outputs and logic array RCLK networks 48 64 88 1 CLK 4 15 pins PLL clock outputs PLD transceiver interface clocks and logic array CLK 0 15 p and CLK 0 15 n pins PLL clock outputs and logic array PCLK networks 84 24 per device quadrant 2 88 22 per device quadrant Dynamic phase alig...

Page 95: ...GCLKs to create internally generated GCLKs and other high fan out control signals for example synchronous or asynchronous clears and clock enables Figure 5 1 and Figure 5 2 show CLK pins and PLLs that can drive GCLK networks in Arria II devices Figure 5 1 GCLK Networks in Arria II GX Devices Notes to Figure 5 1 1 PLL_5 and PLL_6 are only available in EP2AGX95 EP2AGX125 EP2AGX190 and EP2AGX260 devi...

Page 96: ...west clock delay and skew for logic contained in a single device quadrant Arria II IOEs and internal logic in a given quadrant can also drive RCLKs to create internally generated RCLKs and other high fan out control signals for example synchronous or asynchronous clears and clock enables Figure 5 3 and Figure 5 4 show CLK pins and PLLs that can drive RCLK networks in Arria II devices Figure 5 2 GC...

Page 97: ...es Figure 5 4 RCLK Networks in Arria II GZ Devices Note 1 Note to Figure 5 4 1 A maximum of four signals from the core can drive into each group of RCLKs For example only four core signals can drive into RCLK 0 5 and another four core signals can drive into RCLK 54 63 at any one time RCLK 0 5 RCLK 30 35 RCLK 6 11 RCLK 24 29 RCLK 42 47 CLK 12 15 Top Left PLL Bottom Left PLL Bottom Right PLL Top Rig...

Page 98: ...can drive six row clocks in each logic array block LAB row nine column I O clocks and three core reference clocks The SCLKs are the clock resources to the core functional blocks PLLs and I O interfaces of the device Figure 5 5 shows that the GCLK RCLK PCLK or the PLL feedback clock networks in each spine clock can drive the SCLKs Figure 5 5 Hierarchical Clock Networks per Spine Clock in Arria II D...

Page 99: ... clock region has a higher skew when compared with other clock regions but allows the signal to reach every destination in the device This is a good option for routing global reset and clear signals or routing clocks throughout the device To form a regional clock region a source drives a single quadrant of the device This clock region provides the lowest skew in a quadrant and is a good option if ...

Page 100: ...LL outputs and internal logic can drive the GCLK and RCLK networks Table 5 2 through Table 5 5 on page 5 10 list the connectivity between dedicated clock pins and the GCLK and RCLK networks Figure 5 6 Device Dual Regional Clock Region for Arria II GX Devices Figure 5 7 Device Dual Regional Clock Region for Arria II GZ Devices Clock pins or PLL outputs can drive half of the device to create side wi...

Page 101: ...e up to four signals into each GCLK and RCLK network with logic array block LAB routing to allow internal logic to drive a high fan out low skew signal 1 You cannot drive Arria II PLLs by internally generated GCLKs or RCLKs The input clock to the PLL has to come from dedicated clock input pins or PLL fed GCLKs RCLKs only PLL Clock Outputs Table 5 2 and Table 5 3 list the connection between the ded...

Page 102: ...ks for Arria II GX Devices Clock Resource CLK p n Pins 4 5 6 7 8 9 10 11 12 13 14 15 RCLK 12 14 16 18 20 22 v v RCLK 13 15 17 19 21 23 v v RCLK 24 35 v v v v RCLK 36 38 40 42 44 46 v v RCLK 37 39 41 43 45 47 v v Table 5 5 Clock Input Pin Connectivity to the RCLK Networks for Arria II GZ Devices Clock Resource CLK p n Pins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RCLK 0 4 6 10 v RCLK 1 5 7 11 v RCLK 2...

Page 103: ...L Clock Pin Drivers for Arria II GX Devices Note 1 Dedicated Clock Input Pin CLK p n Pins PLL Number 1 2 3 4 5 6 CLK 4 7 v v CLK 8 11 v v v v CLK 12 15 v v Note to Table 5 6 1 PLL_5 and PLL_6 are connected directly to CLK 8 11 PLL_1 PLL_2 PLL_3 and PLL_4 are driven by the clock input pins through a 4 1 multiplexer Table 5 7 PLLs and PLL Clock Pin Drivers for Arria II GZ Devices Note 1 2 Dedicated ...

Page 104: ...0 3 v v GCLK 4 7 v v GCLK 8 11 v v v v GCLK 12 15 v v Table 5 9 PLL Connectivity to the GCLK Networks for Arria II GZ Devices Note 1 Clock Network PLL Number L2 L3 B1 B2 R2 R3 T1 T2 GCLK 0 3 v v GCLK 4 7 v v GCLK 8 11 v v GCLK 12 15 v v Note to Table 5 9 1 Only PLL counter outputs C0 C3 can drive the GCLK networks Table 5 10 RCLK Outputs from PLLs for Arria II GX Devices Clock Resource PLL Number ...

Page 105: ...ting the clock source dynamically you can either select two PLL outputs such as C0 or C1 or a combination of clock pins or PLL outputs Figure 5 8 GCLK Control Block for Arria II Devices Notes to Figure 5 8 1 You can only dynamically control these clock select signals through internal logic when the device is operating in user mode 2 These clock select signals can only be set through a configuratio...

Page 106: ... set the input clock sources and the clkena signals for the GCLK and RCLK clock network multiplexers through the Quartus II software with the ALTCLKCTRL megafunction You can also enable or disable the dedicated external clock output pins with the ALTCLKCTRL megafunction 1 When you use the ALTCLKCTRL megafunction to implement dynamic clock source selection in Arria II devices the inputs from the cl...

Page 107: ...cally controlled through a configuration file sof or pof and cannot be dynamically controlled during user mode operation Figure 5 10 RCLK Control Block for Arria II GZ Devices Notes to Figure 5 10 1 When the device is in user mode you can only set the clock select signals through a configuration file sof or pof You cannot dynamically control the clock 2 The CLKn pin is not a dedicated clock input ...

Page 108: ...clock select signals through a configuration file sof or pof You cannot dynamically control the clock 3 The clock control block feeds a multiplexer in the PLL _CLKOUT pin s IOE The PLL _CLKOUT pin is a dual purpose pin Therefore this multiplexer selects either an internal signal or the output of the clock control block PLL Counter Outputs and m Counter Enable Disable PLL _CLKOUT pin Internal Logic...

Page 109: ...ant of frequency over shoot during resynchronization Clock Source Control for PLLs The clock input to Arria II PLLs comes from clock input multiplexers The clock multiplexer inputs come from dedicated clock input pins PLLs through the GCLK and RCLK networks or from dedicated connections between adjacent corner and center PLLs Arria II GX devices or from dedicated connections between adjacent top b...

Page 110: ...vided the clock control block is fed by an output from another PLL or a pin driven dedicated GCLK or RCLK An internally generated global signal or general purpose I O pin cannot drive the PLL 4 4 1 1 inclk0 inclk1 To the clock switchover block CLK n 3 n 2 GCLK RCLK input 3 Adjacent PLL output Figure 5 15 Clock Input Multiplexer Logic for Arria II GZ devices Notes to Figure 5 15 1 When the device i...

Page 111: ... information refer to the FPGA Fabric PLLs Transceiver PLLs Cascading section in the Transceiver Clocking in Arria II Devices chapter 1 For more information about PLL cascading in external memory interfaces designs refer to the External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide PLLs in Arria II Devices Arria II GX devices offer up to six PLLs per device and seven outputs per PL...

Page 112: ... dedicated path between adjacent PLLs Through GCLK and RCLK and dedicated path between adjacent PLLs 4 Compensation modes All except external feedback mode when you use differential I Os All except LVDS clock network compensation All except external feedback mode when you use differential I Os PLL drives DIFFCLK and LOADEN Yes No Yes VCO output drives DPA clock Yes No Yes Phase shift resolution Do...

Page 113: ...is is only supported in PLL_1 and PLL_3 of EP2AGX95 EP2AGX125 EP2AGX190 and EP2AGX260 devices You can only access one differential I O pair or one single ended pin at a time Figure 5 16 PLL Block Diagram for Arria II Devices Notes to Figure 5 16 1 The number of post scale counters is seven for left and right PLLs and ten for top and bottom PLLs 2 This is the VCO post scale counter K 3 The FBOUT po...

Page 114: ...s of pins 1st pair two single ended I O or one differential I O 2nd pair two single ended I O or one differential external feedback input FBp FBn 3rd pair two single ended I O or one differential input Figure 5 17 External Clock Outputs for Arria II GX PLLs Notes to Figure 5 17 1 You can feed these clock output pins with any one of the C 6 0 or m counters 2 The PLL _CLKOUT p and PLL _CLKOUT npins ...

Page 115: ...e the other pin is the external feedback input FB pin Therefore for single ended I O standards the left and right PLLs only support external feedback mode Figure 5 18 External Clock Outputs for Top and Bottom PLLs in Arria II GZ Devices Notes to Figure 5 18 1 You can feed these clock output pins using any one of the C 9 0 or m counters 2 The CLKOUT0p and CLKOUT0n pins can be either single ended or...

Page 116: ...o drive out to any regular I O pin through the GCLK or RCLK network You can also use the external clock output pins as user I O pins if you do not require external PLL clocking However external clock output pins can support a differential I O standard that is only driven by a PLL 1 Regular I O pins cannot drive the PLL clock input pins Figure 5 19 External Clock Outputs for Left and Right PLLs in ...

Page 117: ...eset is driven high the PLL counters reset clearing the PLL output and placing the PLL out of lock The VCO is then set back to its nominal setting When areset is driven low again the PLL resynchronizes to its input as it relocks You must include the areset signal in designs if any of the following conditions are true PLL reconfiguration or clock switchover is enabled in your design Phase relations...

Page 118: ...us II software Another example is when PLL_1 Arria II GX devices or PLL_T2 Arria II GZ devices is configured in zero delay buffer mode and the PLL input is driven by a dedicated clock input pin a fully compensated clock path results in zero delay between the clock input and one of the output clocks from the PLL If the PLL input is instead fed by a non dedicated input using the GCLK network the out...

Page 119: ...wo paths Data pin to IOE register input Clock input pin to the PLL PFD input You can use the PLL Compensation assignment in the Quartus II software Assignment Editor to select which input pins are used as the PLL compensation targets You can include your entire data bus provided the input registers are clocked by the same output of a source synchronous compensated PLL All input pins must be on the...

Page 120: ...twork plus any difference in the delay between these two paths Data pin to SERDES capture register Clock input pin to SERDES capture register In addition the output counter must provide the 180 phase shift No Compensation Mode In no compensation mode the PLL does not compensate for the clock networks This mode provides better jitter performance because the clock feedback into the PFD passes throug...

Page 121: ...rk is fully compensated Figure 5 23 shows an example waveform of the phase relationship of the PLL clocks in normal mode Figure 5 22 Phase Relationship Between PLL Clocks in No Compensation Mode for Arria II Devices Note to Figure 5 22 1 The PLL clock outputs can lag the PLL input clocks depending on routine delays PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port 1 Externa...

Page 122: ... ports of the PLL when using Arria II GZ PLLs in ZDB mode along with single ended I O standards to ensure phase alignment between the CLK pin and the external clock output CLKOUT pin The PLL uses this bidirectional I O pin to mimic and compensate for the output delay from the clock output port of the PLL to the external clock output pin 1 The bidirectional I O pin that you instantiate in your desi...

Page 123: ...a II GZ PLLs In external feedback mode the output of the M counter FBOUT feeds back to the PLL fbin input using a trace on the board becoming part of the feedback loop Also use one of the dual purpose external clock outputs as the fbin input pin in this mode You must use the same I O standard on the input clock feedback input and output clocks Left and right PLLs support this mode when using singl...

Page 124: ...vides down the high frequency VCO For multiple PLL outputs with different frequencies the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications For example if output frequencies required from one PLL are 33 and 66 MHz the Quartus II software sets the VCO to 660 MHz the least common multiple of 33 and 66 MHz in the VCO range Then the post scale co...

Page 125: ...oftware automatically chooses the appropriate scaling factors according to the input frequency multiplication and division values entered into the ALTPLL megafunction Post Scale Counter Cascading Arria II PLLs support post scale counter cascading to create counters larger than 512 This is automatically implemented in the Quartus II software by feeding the output of one C counter into the input of ...

Page 126: ...mmable Phase Shift Use phase shift to implement a robust solution for clock delays in Arria II devices Implement phase shift with a combination of the VCO phase output and the counter starting time A combination of the VCO phase output and counter starting time is the most accurate method of inserting delays because it is purely based on counter settings which are independent of process voltage an...

Page 127: ...cks for low time CLK1 is based off the 135 phase tap from the VCO and also has the C value for the counter set to one The CLK1 signal is also divided by four In this case the two clocks are offset by 3 Φfine CLK2 is based off the 0phase from the VCO but has the C value for the counter set to three This arrangement creates a delay of 2 ΦCOARSE two complete VCO periods Use the coarse and fine phase ...

Page 128: ...specification Arria II devices cannot internally generate spread spectrum clocks Clock Switchover The clock switchover feature allows the PLL to switch between two reference input clocks Use this feature for clock redundancy or for a dual clock domain application such as in a system that turns on the redundant clock if the previous clock stops running Your design can perform clock switchover autom...

Page 129: ...the multiplexer select input as shown in Figure 5 30 In this case inclk1 becomes the reference clock for the PLL When you use the automatic switchover mode you can switch back and forth between the inclk0 and inclk1 clocks any number of times when one of the two clocks fails and the other clock is available When you use the automatic clock switchover mode the following requirements must be satisfi...

Page 130: ...cycles the clock sense circuitry drives the clkbad 0 signal high Also because the reference clock signal is not toggling the switchover state machine controls the multiplexer through the clksw signal to switch to the backup clock inclk1 Manual Override Mode In automatic switchover with manual override mode you can use the clkswitch input for user or system controlled switch conditions You can use ...

Page 131: ...nt clock glitching On the falling edge of inclk1 the reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference and the activeclock signal changes to indicate which clock is currently feeding the PLL In automatic switchover with manual overide mode the activeclock signal mirrors the clkswitch signal As both clocks are still functional during the manual switch neither clkbad si...

Page 132: ...over Guidelines Use the following guidelines when implementing clock switchover in Arria II PLLs Automatic clock switchover requires that the inclk0 and inclk1 frequencies be in 100 2 of each other Failing to meet this requirement causes the clkbad 0 and clkbad 1 signals to not function properly When you use manual clock switchover mode the difference between inclk0 and inclk1 can be more than 100...

Page 133: ...to turn off the PFD PFDENA 0 so the VCO maintains its most recent frequency You can also use the state machine to switch over to the secondary clock When the PFD is re enabled output clock enable signals clkena can disable the clock outputs during the switchover and resynchronization period After the lock indication is stable the system can re enable the output clocks PLL Reconfiguration PLLs use ...

Page 134: ...you can dynamically adjust the PLL counter settings by shifting their new settings into a serial shift register chain or scan chain Serial data is the input to the scan chain with the SCANDATAPORT and shift registers are clocked by SCANCLK The maximum SCANCLK frequency is 100 MHz Serial data is shifted through the scan chain as long as the SCANCLKENA signal stays asserted After the last bit of dat...

Page 135: ...d into the scan chain the SCANCLKENA signal is deasserted to prevent inadvertent shifting of bits in the scan chain For Arria II GZ devices after all 234 bits top and bottom PLLs or 180 bits left and right PLLs have been scanned into the scan chain the SCANCLKENA signal is deasserted to prevent inadvertent shifting of bits in the scan chain 4 The CONFIGUPDATE signal is asserted for one SCANCLK cyc...

Page 136: ...e by 1 When this bit is set to 0 the high and low time counters are added to compute the effective division of the VCO output frequency For example if the post scale divide factor is 10 the high and low count values could be set to 5 and 5 respectively to achieve a 50 50 duty cycle The PLL implements this duty cycle by transitioning the output clock from high to low on the rising edge of the VCO o...

Page 137: ...ven post scale counters and a 180 bit scan chain Table 5 15 PLL Reprogramming Bits for Arria II GX Devices Block Name Number of Bits Total Counter Other 1 C6 2 16 2 18 C5 16 2 18 C4 16 2 18 C3 16 2 18 C2 16 2 18 C1 16 2 18 C0 16 2 18 M 16 2 18 N 16 2 18 Charge Pump Current 0 3 3 VCO Post Scale divider K 1 0 1 Loop Filter Capacitor 3 0 2 2 Loop Filter Resistor 0 5 5 Unused CP LF 0 7 7 Total number ...

Page 138: ... Devices Block Name Number of Bits Total Counter Other 1 C9 2 16 2 18 C8 16 2 18 C7 16 2 18 C6 3 16 2 18 C5 16 2 18 C4 16 2 18 C3 16 2 18 C2 16 2 18 C1 16 2 18 C0 16 2 18 M 16 2 18 N 16 2 18 Charge Pump Current 0 3 3 VCO Post Scale divider K 1 0 1 Loop Filter Capacitor 4 0 2 2 Loop Filter Resistor 0 5 5 Unused CP LF 0 7 7 Total number of bits 234 Notes to Table 5 16 1 Includes two control bits rby...

Page 139: ...ows the scan chain bit order sequence for post scale counters in all Arria II PLLs Figure 5 37 Scan Chain Order of PLL Components for Arria II GX PLLs DATAIN MSB LF K CP LSB N M C0 C1 C2 C3 C4 C5 C6 DATAOUT Figure 5 38 Scan Chain Order of PLL Components for Top and Bottom of Arria II GZ PLLs Note 1 Note to Figure 5 39 1 Left and right PLLs have the same scan chain order The post scale counters end...

Page 140: ...ump current Icp loop filter resistor R and capacitor C values for Arria II PLLs Table 5 17 charge_pump_current Bit Settings for Arria II Devices CP 2 CP 1 CP 0 Decimal Value for Setting 0 0 0 0 0 0 1 1 0 1 1 3 1 1 1 7 Table 5 18 loop_filter_r Bit Settings for Arria II Devices LFR 4 LFR 3 LFR 2 LFR 1 LFR 0 Decimal Value for Setting 0 0 0 0 0 0 0 0 0 1 1 3 0 0 1 0 0 4 0 1 0 0 0 8 1 0 0 0 0 16 1 0 0 ...

Page 141: ... adjustment is achieved by incrementing or decrementing the VCO phase tap selection to a given C counter or to the M counter The phase is shifted by 1 8 of the VCO frequency at a time The output clocks are active during this phase reconfiguration process Table 5 21 lists the control signals that are used for dynamic phase shifting Table 5 20 PLL Counter Settings for Arria II Devices PLL Scan Chain...

Page 142: ...ifting Shared with scanclk for dynamic reconfiguration GCLK RCLK or I O pin PLL reconfiguration circuit PHASEDONE When asserted this indicates to the core logic that the phase adjustment is complete and the PLL is ready to act on a possible second adjustment pulse Asserts based on internal PLL timing Deasserts on the rising edge of scanclk PLL reconfiguration circuit Logic array or I O pins Table ...

Page 143: ... falling edge PHASESTEP must stay high for at least two SCANCLK cycles On the second SCANCLK rising edge after PHASESTEP is latched the fourth SCANCLK rising edge in Figure 5 40 the values of PHASEUPDOWN and PHASECOUNTERSELECT are latched and the PLL starts dynamic phase shifting for the specified counters and in the indicated direction On the fourth SCANCLK rising edge PHASEDONE goes high to low ...

Page 144: ...5 4 Figure 5 5 Figure 5 7 Figure 5 15 Figure 5 11 Figure 5 16 Figure 5 18 Figure 5 19 Figure 5 24 Figure 5 26 Figure 5 27 Figure 5 38 and Figure 5 39 Added Table 5 5 Table 5 7 Table 5 9 Table 5 11 andTable 5 16 Added Clock Sources Per Quadrant and External Feedback Mode sections Minor text edit July 2010 3 0 Updated for Arria II GX v10 0 release Updated Clock Regions and Arria II PLL Hardware Over...

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