DE1-S
O
C C
OMPUTER
S
YSTEM WITH
N
IOS
II
For Quartus II 15.0
Gnd Ch
7
Ch
6
Ch
5
Ch
4
Ch
3
Ch
2
Ch
1
Ch
0
V
JP15
cc5
Figure 37. ADC connector.
4.8
Floating-point Hardware
The Nios II processor in the DE1-SoC Computer includes hardware support for floating-point addition, subtraction,
multiplication, and division. To use this support in a C program, variables must be declared with the type
float
. A
simple example of such code is given in Figure
38
. When this code is compiled, it is necessary to pass the special
argument
-mcustom-fpu-cfg=60-2
to the C compiler, to instruct it to use the floating-point hardware support.
5
Modifying the DE1-SoC Computer
It is possible to modify the DE1-SoC Computer by using Altera’s Quartus II software and Qsys tool. Tutorials that
introduce this software are provided in the University Program section of Altera’s web site. To modify the system it
is first necessary to make an editable copy of the DE1-SoC Computer. The files for this system are installed as part
of the Monitor Program installation. Locate these files, copy them to a working directory, and then use the Quartus II
and Qsys software to make any desired changes.
6
Making the System the Default Configuration
The DE1-SoC Computer can be loaded into the nonvolatile FPGA configuration memory on the DE1-SoC board,
so that it becomes the default system whenever the board is powered on. Instructions for configuring the DE1-SoC
board in this manner can be found in the tutorial
Introduction to the Quartus II Software
, which is available from
Altera’s University Program.
40
Altera Corporation - University Program
2015