DE1-S
O
C C
OMPUTER
S
YSTEM WITH
N
IOS
II
For Quartus II 15.0
Address
0
15
31
. . .
0
x
FF202000
0
x
FF202004
. . .
Unused
RUN
TO
1
START CONT ITO
STOP
16
2
17
Unused
Counter start value (low)
0
x
FF202008
Counter start value (high)
0
x
FF20200C
Counter snapshot (low)
0
x
FF202010
Counter snapshot (high)
0
x
FF202014
3
Not present
(interval timer has
16-bit registers)
Status register
Control register
Figure 14. Interval timer registers.
2.7
G-Sensor
The DE1-SoC Computer includes a 3D accelerometer (G-sensor) that is connected to the HPS. The Nios II processor
can access this device via an I2C serial interface at the base address
0xFFC04000
. More details can be found in the
tutorial
Using the DE1-SoC Accelerometer with Nios II
, available from Altera’s University Program website.
3
Exceptions and Interrupts
The reset address of the Nios II processor in the DE1-SoC Computer is set to
0x00000000
. The address used for
all other general exceptions, such as divide by zero, and hardware IRQ interrupts is
0x00000020
. Since the Nios II
processor uses the same address for general exceptions and hardware IRQ interrupts, the Exception Handler software
must determine the source of the exception by examining the appropriate processor status register. Table
1
gives the
assignment of IRQ numbers to each of the I/O peripherals in the DE1-SoC Computer. The rest of this section
describes the interrupt behavior associated with the interval timer, parallel ports, and serial ports in the DE1-SoC
Computer. Interrupts for other devices listed in Table
1
are discussed in section
4
.
I/O Peripheral
IRQ #
Interval timer
0
Pushbutton switch parallel port
1
Second Interval timer
2
Audio port
6
PS/2 port
7
JTAG port
8
Serial port
10
JP1 Expansion parallel port
11
JP2 Expansion parallel port
12
Table 1. Hardware IRQ interrupt assignment for the DE1-SoC Computer.
14
Altera Corporation - University Program
2015