ADM-VPX3-9V2 User Manual
3.10.1.1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233):
•
set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
•
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
•
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
•
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
•
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
•
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
•
set_property CFGBVS GND [ current_design ]
•
set_property CONFIG_VOLTAGE 1.8 [ current_design ]
•
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem):
•
-format MCS
•
-size 256
•
-interface SPIx4
•
-loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)
Program with vivado hardware manager with these settings (see xapp1233):
•
SPI part: mt25qu02g-spi-x1_x2_x4_x8
•
State of non-config mem I/O pins: Pull-none
3.10.2 Configuration via JTAG
A Xilinx programming cable (HW-USB-II-G) can connect directly to the header on the debug board. This permits
the FPGA to be reconfigured using the Xilinx Vivado Hardware Manager. The device will be automatically
recognized in Vivado Hardware Manager.
When the HW-USB-II-G is not plugged into the debug board, the JTAG channel is routed to the P0 standard
JTAG connection.
For more detailed instructions, please see “Using a Vivado Hardware Manager to Program an FPGA Device”
section of Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/
ug908-vivado-programming-debugging.pdf
Page 21
Functional Description
ad-ug-1377_v1_2.pdf
