ADM-VPX3-9V2 User Manual
3.4.1 PCIe Reference Clock
Quad 224 can serve as an input for the PCIe reference clock. This quad has direct access to VPX REFCLK at
MGTREFCLK0. Any other suitable quad can provide a PCIE reference clock with PROGCLK0* or PROGCLK1*
as well.
3.4.2 Fabric Clock
The design offers a fabric clock (net name FABRIC_CLK_*) which defaults to 300 MHz. This clock is intended to
be used for IDELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC) pin.
DIFF_TERM_ADV = TERM_100 is required for LVDS termination
3.4.3 Programming Clock (EMCCLK)
A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI flash device during
configuration of the FPGA. Note that this is not a global clock capable IO pin.
3.4.4 PROGCLK0 Clock
The PROGCLK_0 clocks have a default 100MHz reference clock. Note that this clock frequency can be changed
to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator.
See details on avr2util in the section:
The PROGCLK_0 connects at each usable MGT quad at the MGTREFCLK0 location. Quad 224 is the only
exception, which is connected to VPX REFCLK instead. PROGCLK0_9* is connected to global clock pins at
Bank 68 as well.
See net names PROGCLK_0* for pin locations.
3.4.5 PROGCLK1 Clock
The PROGCLK_1 clocks have a default 156.25MHz reference clock. Note that this clock frequency can be
changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock
oscillator. See details on avr2util in the section:
The PROGCLK_1 connects at each usable MGT quad at the MGTREFCLK1 location.
See net names PROGCLK_1* for pin locations.
3.4.6 DDR4 SDRAM Reference Clocks
The four banks of DDR4 SDRAM memory each receive a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are nets beginning with REFCLK300M*.
The default frequency is 300MHz. Note that this clock frequency can be changed to any arbitrary clock frequency
up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator. See details on avr2util in the
section:
.
Page 14
Functional Description
ad-ug-1377_v1_2.pdf
