ADM-VPX3-9V2 User Manual
3.7 DDR4 SDRAM
four banks of DDR4 SDRAM memory are soldered down to the board. The available density of the memory is
4GB/per bank, 16GB total. The memory interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate
is 2666 MT/s.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) tool. An example memory
exerciser project is included in the ADM-VPX3-9V2 SDK. All constraint information is included in
The 8Gb components used are Micron MT40A512M16RLY-062E IT
The DDR4 ICs are placed and routed with the clamshell topology. Ensure the "clamshell" check box in the MIG
IP tools is selected to enable proper address control.
Figure 12 : DDR4 bank locations by index
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Functional Description
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