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5/02 Processor Only

Chapter 29

Understanding the User Fault Routine

29–7

Subroutine File 4 - Executed for error 0020

MINOR ERROR AT END OF SCAN

If the overflow trap bit S:5/0 is set, counter C5:0 will increment.
If the count of C5:0 is 5 or less, the overflow trap S:5/0 will be cleared, the

major error halted bit S:1/13 will be cleared, and the processor will remain in

the Run mode. Fault code 0020 will be indicated in the status file display. If

the count is greater than 5, the processor will set S:5/0 and S:1/13 and enter

the fault mode.
This subroutine file is also executed if the control register error bit S:5/2 is set.

In this case, the processor is placed in the fault mode.

Fault code and description are indicated.

S:1/13 Cleared

S:5/0 Cleared

Status File Display - At 1st through 5th overflow (S:5/0) occurrences

END

SBR

SUBROUTINE

RET

RETURN

GRT

GREATER THAN
Source A

C5:0.ACC

0

Source B

5

(CU)

(DN)

CTU

COUNT UP
Counter

C5:0

Preset

120

Accum

0

(U)

S:5

0

] [

S:5

0

(U)

C5:0

CU

(U)

S:1

13

RET

RETURN

] [

S:5

0

F1

F2

F3

F4

F5

Status File
S2:5 Minor Fault 0000 0000 0000 0000
S2:6 Fault Code 0020H
Desc: Minor Error At End Of Scan
S2:29 Err File: 0 Indx Cross File: No
S2:24 Index Reg: 0 Single Step: No
S2:5/0 = 0 PRG
ADDRESS NEXT FL PREV FL NEXT PG PREV PG

F1

F2

F3

F4

F5

Status File
Arithmetic Flags S:0 Z:0 V:0 C:0
S2:0 Proc Status 0000 0000 0000 0000
S2:1 Proc Status 0000 0000 1000 0001
S2:2 Proc Status 1000 0000 0000 0010

S2:0/0 = 0 PRG
ADDRESS NEXT FL PREV FL NEXT PG PREV PG

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Summary of Contents for 1747-PT1

Page 1: ...ALLEN BRADLEY Hand Held Terminal Catalog Number 1747 PT1 User Manual Allen Bradley Parts ...

Page 2: ...Bradley Company cannot assume responsibility or liability for actual use based on the examples and diagrams No patent liability is assumed by Allen Bradley Company with respect to use of information circuits equipment or software described in this manual Reproduction of the contents of this manual in whole or in part without written permission of the Allen Bradley Company is prohibited Throughout ...

Page 3: ...n general 14 Using EEPROMs and UVPROMs g 15 Instruction Set Overview 27 The Status File 32 Bit Addition and Subtraction 20 Math Instructions 22 File Copy and File Fill Instructions Index Register 23 Bit Shift FIFO and LIFO Instructions Index Register 24 Sequencer Instructions DH 485 devices 9 Configuring Online Communication 28 Troubleshooting Faults User Fault Routine 29 Understanding the User Fa...

Page 4: ...nstalling the Memory Pak Battery and Communication Cable 1 3 HHT Powerup 1 7 HHT Display Format 1 8 The Keyboard 1 9 Menu Function Keys F1 F2 F3 F4 F5 1 9 Data Entry Keys 1 9 Auto Shift 1 9 Cursor Keys 1 10 ZOOM and RUNG Keys 1 12 The Menu Tree 2 1 Using the HHT Menu 2 1 Progressing through Menu Displays 2 1 The ENTER Key 2 2 The ESCAPE Key 2 2 The Main Menu 2 3 Main Menu Functions 2 3 SELFTEST F1...

Page 5: ...Value S 24 Index Register 4 13 Example 4 13 Creating Data for Indexed Addresses 4 14 Crossing File Boundaries 4 14 Example 4 14 Monitoring Indexed Addresses 4 15 Example 4 15 Effects of File Instructions on Indexed Addressing 4 15 Effects of Program Interrupts on Index Register S 24 4 15 File Instructions Using the File Indicator 4 16 Bit Shift Instructions 4 16 Sequencer Instructions 4 17 File Co...

Page 6: ...hing 5 5 Example Parallel Output Branching with Conditions SLC 5 02 Only 5 6 Nested Branching 5 6 Example Nested Input and Output Branches 5 6 Example 5 7 A 4 Rung Ladder Program 5 8 Application Example 5 9 Operating Cycle Simplified 5 11 When the Input Goes True 5 12 When the Input Goes False 5 13 Creating a Program 6 1 Creating a Program Offline with the HHT 6 1 Clearing the Memory of the HHT 6 ...

Page 7: ...gs 7 14 Adding an Instruction to a Rung 7 14 Modifying Instructions 7 16 Changing the Address of an Instruction 7 16 Changing an Instruction Type 7 18 Modifying Branches 7 19 Extending a Branch Up 7 19 Extending a Branch Down 7 22 Appending a Branch 7 24 Delete and Undelete Commands 7 26 Deleting a Branch 7 26 Deleting an Instruction 7 29 Copying an Instruction from One Location to Another 7 30 De...

Page 8: ...9 6 Attach 9 7 Exception 9 8 Node Configuration 9 8 Consequences of Changing a Processor Node Address 9 9 Entering a Maximum Node Address 9 10 Changing the Baud Rate 9 10 Set and Clear Ownership 9 10 Recommendations When Using DH 485 Devices 9 12 Downloading Uploading a Program 10 1 Downloading a Program 10 1 Uploading a Program 10 3 Processor Modes 11 1 Processor Modes 11 1 Program Mode 11 1 Test...

Page 9: ...n EEPROM Memory Module 14 1 Transferring a Program to an EEPROM Memory Module 14 1 Transferring a Program from an EEPROM Memory Module 14 3 EEPROM Burning Options 14 5 Burning EEPROMs for a SLC 5 01 Processor or Fixed Controller 14 5 Burning EEPROMs for a SLC 5 02 Processor 14 5 Burning EEPROMS for SLC Configurations 14 6 UVPROM Memory Modules 14 6 Instruction Set Overview 15 1 Instruction Classif...

Page 10: ...ndexed Word Addresses 17 2 Timer Data File Elements Timebase and Accuracy 17 2 Timebase 17 2 Accuracy 17 2 Timer On Delay TON 17 3 Status Bits 17 3 Timer Off Delay TOF 17 4 Status Bits 17 4 Retentive Timer RTO 17 5 Status Bits 17 6 Count Up CTU and Count Down CTD 17 7 Status Bits 17 8 High Speed Counter HSC 17 9 Instruction Parameters 17 11 Application Example 17 11 Reset RES 17 13 I O Message and...

Page 11: ...tructions 19 1 Comparison Instructions Overview 19 1 Indexed Word Addresses 19 1 Equal EQU 19 2 Entering Parameters 19 2 Not Equal NEQ 19 3 Entering Parameters 19 3 Less Than LES 19 4 Entering Parameters 19 4 Less Than or Equal LEQ 19 5 Entering Parameters 19 5 Greater Than GRT 19 6 Entering Parameters 19 6 Greater Than or Equal GEQ 19 7 Entering Parameters 19 7 Masked Comparison for Equal MEQ 19 ...

Page 12: ...rithmetic Status Bits 20 10 Math Register 20 10 Clear CLR 20 11 Using Arithmetic Status Bits 20 11 Math Register 20 11 Convert to BCD TOD 20 12 Entering Parameters 20 12 Using Arithmetic Status Bits 20 13 Math Register When Used 20 13 Convert from BCD FRD 20 15 Entering Parameters 20 15 Using Arithmetic Status Bits 20 16 Math Register When Used 20 16 Ladder Logic Filtering of BCD Input Devices 20 ...

Page 13: ...s 21 7 Not NOT 21 8 Using Arithmetic Status Bits 21 8 File Copy and File Fill Instructions 22 1 File Copy and Fill Instructions Overview 22 1 Effect on Index Register in SLC 5 02 Processors 22 1 File Copy COP 22 2 Entering Parameters 22 2 File Fill FLL 22 3 Entering Parameters 22 4 Bit Shift FIFO and LIFO Instructions 23 1 Bit Shift FIFO and LIFO Instructions Overview 23 1 Effect on Index Register...

Page 14: ...mpare 24 6 Effect on Index Register in SLC 5 02 Processors 24 6 Sequencer Load SQL 24 7 Entering Parameters 24 7 Status Bits 24 8 Operation 24 9 Effect on Index Registers in SLC 5 02 Processors 24 9 Control Instructions 25 1 Control Instructions Overview 25 1 Jump to Label JMP 25 2 Entering Parameters 25 2 Label LBL 25 3 Entering Parameters 25 3 Jump to Subroutine JSR 25 4 Nesting Subroutine Files...

Page 15: ...6 18 Output Limiting with Anti reset Windup 26 18 The Manual Mode 26 19 Feed Forward 26 21 Time Proportioning Outputs 26 21 PID Tuning 26 23 Procedure 26 23 The Status File 27 1 Status File Functions 27 1 Status File Display SLC 5 02 Processors 27 32 Status File Display SLC 5 01 and Fixed Processors 27 33 Troubleshooting Faults 28 1 Troubleshooting Overview 28 1 User Fault Routine Not in Effect 28...

Page 16: ...0 1 Operation 30 1 STI Subroutine Content 30 2 Interrupt Occurrences 30 2 Interrupt Latency 30 2 Interrupt Priorities 30 3 Status File Data Saved 30 3 STI Parameters 30 4 STD and STE Instructions 30 6 STD STE Zone Example 30 7 STS Instruction 30 8 INT Instruction 30 9 Understanding I O Interrupts SLC 5 02 Processor Only 31 1 I O Overview 31 1 Basic Programming Procedure for the I O Interrupt Funct...

Page 17: ...ecution Times for the SLC 5 02 Processor Series A or B C 8 Instructions Having Indexed Addresses C 9 Instructions Having M0 or M1 Data File Addresses C 9 Example C 9 Instruction Execution Times for the SLC 5 02 Processor Series C and Later C 10 Instructions Having Indexed Addresses C 12 Instructions Having M0 and M1 Data File Addresses C 12 Example C 12 Estimating Scan Time D 1 Events in the Opera...

Page 18: ...representative for information on available training courses before using this product We recommend that you review The Getting Started Guide for HHT catalog number 1747 NM009 before using the Hand Held Terminal HHT This manual is a reference guide for technical personnel who use the Hand Held Terminal HHT to develop control applications It describes those procedures in which you may use an HHT to...

Page 19: ...Program Covers the procedures used to compile and save a program 9 Configuring Online Communication Describes online communication between the HHT and SLC 500 10 Downloading Uploading a Program Provides the procedures for downloading and uploading 11 Processor Modes Describes the different operating modes a processor can be placed in while using the HHT 12 Monitoring Controller Operation Briefly c...

Page 20: ...status file functions of the fixed SLC 5 01 and SLC 5 02 processors 28 Troubleshooting Faults Explains the major error fault codes by indicating the probable causes and recommending corrective action 29 Understanding the User Fault Routine SLC 5 02 Processor Only Covers recoverable and non recoverable user faults 30 Understanding Selectable Timed Interrupts SLC 5 02 Processor Only Explains the ope...

Page 21: ...ses and allowing the reader to begin programming in the shortest time possible Getting Started Guide for APS 1747 NM001 A procedural and reference manual for technical personnel who use the APS import export utility to convert APS files to ASCII and conversely ASCII to APS files APS Import Export User Manual 1747 NM006 An introduction to HHT for first time users containing basic concepts but focus...

Page 22: ...technical training warranty support support service agreements Technical Product Assistance If you need to contact Allen Bradley for technical assistance please review the information in the Troubleshooting Faults chapter 28 first Then call your local Allen Bradley representative Your Questions or Comments on this Manual If you have any suggestions for how this manual could be made more useful to ...

Page 23: ...tion one HHT to one controller or on a DH 485 network communicate with up to 31 nodes over a maximum of 4 000 feet or 1219 meters When equipped with a battery 1747 BA the HHT retains a user program in memory for storage and later use Specifications Environmental conditions Operating temperature 0 to 40 C 32 to 104 F Storage temperature 20 to 65 C 4 to 149 F Humidity rating 5 to 95 non condensing D...

Page 24: ...cate true status A zoom feature is included to give immediate access to instruction parameters SLC 500 PROGRAMMING SOFTWARE Rel 2 03 1747 PTA1E Allen Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 N O SPACE PRE LEN S ACC POS I U ESC A 7 D 4 T 1 B 8 E 5 R 2 0 C 9 F 6 M 3 SHIFT ENTER ZOOM RUNG Calculator style Color coded Keyboard Keys operate with motion and tactile response Disp...

Page 25: ...atalog number 1747 PTA1E ATTENTION The memory pak contains CMOS devices Wear a grounding strap and use proper grounding procedures to guard against damage to the memory pak from electrostatic discharge a To install the memory pak remove the cover from the back of the HHT Backside of HHT Slide cover to the left Lift off cover Installing the Memory Pak Battery and Communication Cable Allen Bradley P...

Page 26: ...es Installation Powerup 1 4 b Insert the memory pak in its compartment as indicated in the following figure Backside of HHT After the memory pak is in the compartment press down on handle to secure connector in socket ...

Page 27: ...BATTERY TEST FAILED appears To prevent this from happening leave the battery low defeat jumper inserted in the battery socket The HHT is functional but your user program is cleared from memory when you de energize the HHT If you do not download the user program to the processor before you de energize the HHT your program will be lost a Remove the jumper from the battery socket then connect the bat...

Page 28: ... Communication Port Peripheral Port Isolated Link Coupler Cover Open The connectors are keyed Connect one end of the 1747 C10 communication cable to the top of the HHT The other connector plugs into the communication port on the SLC 500 controllers or the peripheral port on the 1747 AIC SLC Controller Modular 1747 C10 Cable HHT If you are using a 1747 NP1 wall mount power supply or a 1747 NP2 desk...

Page 29: ...len Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 PRESS A FUNCTION KEY SELFTEST TERM PROGMAINT OFL UTILITY If any of the tests fail the failure is indicated by the appropriate message on the display For a detailed list of HHT messages and error definitions refer to appendix A in this manual After powerup you may perform any of five diagnostic tests using the selftest function P...

Page 30: ...INT Prompt Data Entry Error Area Menu tree functions are directly accessible Select menu function keys with F1 to F5 keys When the symbol is present pressing ENTER toggles additional menu functions File Name 101 Prog Name 1492 File Name Type Size Instr 0 System 1 Reserved 2 101 Ladder CHG_NAM CRT_FIL EDT_FIL DEL_FIL MEM_MAP F1 F2 F3 F4 F5 OFL Display Area Indicates that the HHT is offline When onl...

Page 31: ...tain the upper function of a key press and release the SHIFT key then press the desired key If you make an error while entering data press ESC and re enter the data or use the cursor arrow keys and or the SPACE key to locate and correct the error To complete a data entry press ENTER You can also use the ESC key to exit the data entry and return to the previous menu level Auto Shift When you enter ...

Page 32: ...in the program scroll through controller and I O configuration selections scroll through program file directories scroll through active node addresses scroll through the elements and bits of individual data files F1 F2 F3 F4 F5 ZOOM on OTE 2 1 1 0 2 NAME OUTPUT ENERGIZE BIT ADDR O0 2 0 7 ENTER BIT ADDR O0 2 0 7 EDT_DAT ACCEPT The keys move the cursor left and right between the items of the address...

Page 33: ...ame Prog Name 2A File Name Type Size Instr 0 System 217 1 Reserved 0 2 Ladder 30 OFL The keys scroll through user program files DIAGNSTC ATTACH NODE CFG OWNER F1 F2 F3 F4 F5 Node Addr Device Max Addr Owner 0 APS 31 1 TERMINAL 31 2 5 02 31 3 500 20 31 Node Addr 0 Baud Rate 19200 OFL The keys scroll through active node addresses ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Address 15 data ...

Page 34: ...sor moves to the selected rung and the rung appears at the top of the display OFL INS RNG MOD RNG SEARCH DEL RNG UND RNG F1 F2 F3 F4 F5 TON T4 2 2 2 0 0 2 TON F1 F2 F3 F4 F5 ZOOM on TON TON 2 2 0 0 2 NAME TIMER ON DELAY TIMER T4 2 TIME BASE 01 SEC PRESET 20 ACCUM 0 EDT_DAT Press the ZOOM key with the cursor on an instruction The Zoom display shows the instruction parameters Exit the Zoom display b...

Page 35: ... with the following Progressing through Menu Displays To progress through the HHT menu displays press the desired function key When that display appears press the next appropriate function key and so on 1 For example to clear the HHT memory start from the Main menu SLC 500 PROGRAMMING SOFTWARE Rel 2 03 1747 PTA1E Allen Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 PRESS A FUNCT...

Page 36: ...Size Instr 0 System 217 1 Reserved 0 2 101 Ladder 465 ARE YOU SURE YES NO F1 F2 F3 F4 F5 OFL 3 Press F2 YES This deletes the current program in the HHT After you confirm the display returns to the previous menu File Name Prog Name Default File Name Type Size Instr 0 System 1 Reserved 2 Ladder EDT_DAT SEL_PRO EDT_I O CLR_MEM F1 F2 F3 F4 F5 OFL The ESCAPE Key Use ESC to exit a menu and move to the p...

Page 37: ...FL UTILITY Some of the procedures you may perform from the Main menu are SELFTEST F1 Allows you to test the following components of the HHT display keypad random access memory read only memory internal watchdog timer TERMINAL F2 Allows you to configure the HHT for IMC 110 mode when attached to a 1746 HS module monitor and debug MML programs PROGRAM MAINTENANCE F3 Allows you to name programs and pr...

Page 38: ...memory monitor the ladder diagram while the processor is in Run mode The figures that follow graphically guide you through the HHT menus and sub menus DISPLAY F1 KEYPAD F2 RAM F3 ROM F4 WTCHDOG F5 DSTRUCT F2 NONDEST F4 Main Menu Refer to page 2 6 Refer to page 2 7 to 2 10 F1 SELFTEST F2 TERM F3 PROGMAINT F5 UTILITY Main Menu Function Key Use For SELFTEST HHT unit diagnostics TERM terminal mode for...

Page 39: ...M F4 ADDRESS F1 NEXT_FL F2 PREV_FL F3 NEXT_PG F4 PREV_PG F5 TYPE F1 SERIES F3 MOD_RCK F1 MOD_SLT F2 DEL_SLT F3 UND_SLT F4 RACK 1 F1 RACK 2 F2 RACK 3 F3 OTHER F3 ADV_SET F5 INT_SBR F1 MOD_SET F2 BIN F1 DEC F2 HEX BCD F3 NEXT_PG F4 PREV_PG F5 CFG_SIZ F3 ADV_SIZ F4 INS_INST F1 BRANCH F2 MOD_INST F3 ACP_RNG F5 DEL_INST F2 UND_INST F4 EXT_UP F1 EXT_DWN F2 APP_BR F3 INS_BR F4 DEL_BR F5 ENTER ENTER ENTER...

Page 40: ...5 ENTER ENTER ENTER MOV LOG F1 MOV F1 MVM F2 AND F3 OR F4 XOR F5 NOT F1 OTHERS F5 ENTER page ENTER CPT MTH F5 ADD F1 SUB F2 MUL F3 DIV F4 DDV F5 NEG F1 CLR F2 SQR F3 TOD F4 FRD F5 DCD F2 SCL F3 PID F4 OTHERS F5 ENTER ENTER COMPARE F4 LIM F1 MEQ F3 EQU F4 NEQ F5 LES F1 GRT F2 LEQ F3 GEQ F4 OTHERS F5 ENTER I O_MSG F3 IIM F1 IOM F2 MSG F3 IIE F4 IID F5 RPI F1 REF F3 SVC F4 OTHERS F5 ENTER TMR CNT F2 ...

Page 41: ...0 F3 1200 F4 UTILITY F5 Main Menu Utility F5 Default Program in Processor If Previously Attached to that Processor ONLINE F1 WHO F2 OFFLINE F1 OWNER F2 DWNLOAD F2 CLR_PRC F3 MEM_PRC F4 DIAGNSTC F1 ATTACH F3 NODE_CFG F4 NODE F1 NETWORK F5 RESET F5 OFFLINE F1 CHG_ADR F1 MAX_ADR F2 BAUD F3 SET_OWNR F1 CLR_OWNR F5 DWNLOAD F2 CLR_PRC F3 MEM_PRC F4 PASSWRD F3 CLR_MEM F5 ENT F1 REM F2 ENT_MAS F3 REM_MAS ...

Page 42: ...REM_MAS F4 OWNER F5 F2 F3 F4 F1 19200 9600 2400 1200 Main Menu Utility F5 Processor Program Does Not Equal HHT Program If Previously Attached to that Processor UTILITY F5 ONLINE F1 OFFLINE F1 UPLOAD F2 DWNLOAD F3 MODE F4 CLR_PRC F5 RUN F1 TEST F3 CONT F2 SINGLE F4 PROGRAM F5 DIAGNSTC F1 ATTACH F3 NODE_CFG F4 NODE F1 NETWORK F5 RESET F5 CHG_ADR F1 MAX_ADR F2 BAUD F3 SET_OWNR F1 CLR_OWNR F5 WHO F2 P...

Page 43: ...M F3 EDT_DAT F4 MONITOR F5 RUN F1 TEST F3 CONT F2 SINGLE F4 PROGRAM F5 ENT F1 REM F2 ENT_MAS F3 REM_MAS F4 MEM_PRC F2 PRC_MEM F4 ADDRESS F1 NEXT_FL F2 PREV_FL F3 NEXT_PG F4 PREV_PG F5 MODE F1 FORCE F2 EDT_DAT F3 RUN F1 TEST F3 CONT F2 SINGLE F4 PROGRAM F5 ON F1 OFF F2 REM F3 REM_ALL F4 ENABLE F5 ADDRESS F1 NEXT_FL F2 PREV_FL F3 NEXT_PG F4 PREV_PG F5 CUR INS F1 CUR OPD F2 NEW INS F3 UP F4 FORCE F5 ...

Page 44: ...LINE F1 UPLOAD F2 DWNLOAD F3 MODE F4 CLR_PROC F5 PASSWRD F1 XFERMEM F3 EDT_DAT F4 MONITOR F5 RUN F1 TEST F3 CONT F2 SINGLE F4 PROGRAM F5 ENT F1 REM F2 ENT_MAS F3 REM_MAS F4 MEM_PRC F2 PRC_MEM F4 ADDRESS F1 NEXT_FL F2 PREV_FL F3 NEXT_PG F4 PREV_PG F5 MODE F1 FORCE F2 EDT_DAT F3 RUN F1 TEST F3 PROGRAM F5 ON F1 OFF F2 REM F3 REM_ALL F4 ENABLE F5 ADDRESS F1 NEXT_FL F2 PREV_FL F3 NEXT_PG F4 PREV_PG F5 ...

Page 45: ... cancel edit CAN_RNG cancel rung CFG_SIZ configure size CHG_ADR change node address CHG_NAM change name CLR_MEM clear memory CLR_OWNR clear ownership CLR_PRC clear processor CONT continuous CPT MTH compute math CRT_DT create data CRT_FIL create file CSN continuous scan CUR INS current instruction CUR OPD current operand DEC decimal number DEL_BR delete branch DEL_DT delete data DEL_FIL delete file...

Page 46: ...s files INS_BR insert branch INS_INST insert instruction INS_RNG insert rung INT_SBR interrupt subroutine I O_MSG I O message MAX_ADR maximum node address MEM_MAP memory map MEM_PRC memory module to processor MEM_SIZ memory size MOD_INST modify instruction MOD_RCK modify rack MOD_RNG modify rung MOD_SET modify setup MOD_SLT modify slot MOR_CPT more compute MOV LOG move logic NEW INS new instructio...

Page 47: ...remove REM_ALL remove all REM_MAS remove master SAVE_CT save and continue SAVE_EX save and exit SEL_PRO select processor SET_OWNR set ownership SFT SEQ shift sequencer SNK sink SRC source SSN single scan TERM terminal TMR CNT timer counter TRANS transistor TRI triac TSTRUNG test single rung UND_INST undelete instruction UND_RNG undelete rung UND_SLT undelete slot WTCHDOG watchdog XFERMEM transfer ...

Page 48: ...ile fill FRD convert from BCD GEQ greater than or equal to GRT greater than HSC high speed counter IID I O interrupt disable IIE I O interrupt enable IIM immediate input with mask INT interrupt subroutine IOM immediate output with mask JMP jump to label JSR jump to subroutine LBL label LEQ less than or equal to LES less than LFL LIFO load LFU LIFO unload LIM limit test MCR master control reset MEQ...

Page 49: ... subroutine RPI reset pending I O interrupt RTO retentive on delay timer SBR subroutine SCL scale data SQC sequencer compare SQL sequencer load SQO sequencer output SQR square root STD STI disable STE STI enable STS STI start immediately SUB subtract SUS suspend SVC service communications TND temporary end TOD convert to BCD TOF timer off delay TON timer on delay XIC examine if closed XIO examine ...

Page 50: ...processor a memory module the APS terminal Notes on terminology The term program used in Hand Held Terminal HHT displays is equivalent to the term processor file used in APS software displays These terms mean the collective program files and data files created under a particular program or processor file Most of the operations you perform with the HHT involve the program and the two components cre...

Page 51: ...program When you have completed and saved your program you download it to the processor RAM memory for online operation See page 3 3 for more information on downloading You may also keep a back up of your program in the EEPROM memory module located in the processor Program Files Program files contain controller information the main control program and any subroutine programs The first three progra...

Page 52: ...n This file is useful for troubleshooting controller and program operation Bit file 3 This file is used for internal relay logic storage Timer file 4 This file stores the timer accumulated and preset values and status bits Counter file 5 This file stores the counter accumulated and preset values and the status bits Control file 6 This file stores the length pointer position and status bits for spe...

Page 53: ...1000 1000 PROCESSOR Upload Using EEPROM and UVPROM Memory Modules for Program Backup An EEPROM or UVPROM memory module can be inserted in SLC 500 controllers You can use the HHT to transfer a copy of the program in processor RAM to an EEPROM memory module UVPROM memory modules cannot be programmed by a processor You need an external PROM burner You can also transfer a program from an EEPROM or UVP...

Page 54: ... transfer on the DH 485 network Non SLC 500 devices are able to read and write to this file Data file 9 can be used as an ordinary data file if the processor is not on a network Designate this file as Integer or Bit when using the network transfer function This file is also called Common Interface File 485CIF or PLC 2 compatibility file M0 and M1 files These data files reside in the memory of the ...

Page 55: ...rol Integer B T C R N 9 255 File Type File Number Identifier User Defined Files Data file types identifiers and numbers Data files contain elements As shown below some data files have 1 word elements some have 3 word elements You will be addressing elements words and bits Output and Input files have 1 word elements with each element specified by slot and word number Elements in Timer Counter and C...

Page 56: ... 2 the status file and following with files 0 1 3 4 5 6 and 7 Data File 2 Status The status file is explained in chapter 27 You can address various bits and words as follows Format Explanation S Status file Element delimiter S e b e Element number Ranges from 0 to 15 in a SLC 5 01 or fixed controller 0 32 in a SLC 5 02 These are 1 word elements 16 bits per element Bit delimiter b Bit number Bit lo...

Page 57: ...tputs The figure shows how these outputs and inputs are arranged in data files 0 and 1 For these files the element size is always 1 word The table on the following page explains the addressing format for outputs and inputs Note that the format specifies e as the slot number and s as the word number When you are dealing with file instructions refer to the element as e s slot and word taken together...

Page 58: ...ge 0 255 range accommodates multi word specialty cards Bit delimiter b Terminal number Inputs 0 to 15 Outputs 0 to 15 Examples applicable to the controller shown on page 4 4 O 0 4 Controller output 4 slot 0 O 2 7 Output 7 slot 2 of the expansion rack I 1 4 Input 4 slot 1 of the expansion rack I 0 15 Controller input 15 slot 0 I 0 1 7 Controller input 23 bit 07 word 1 of slot 0 Word addresses O 1 O...

Page 59: ...2 Power Supply I O I O 3 4 I O I O 5 6 I O I O 7 8 Power Supply I O I O 9 10 Future Expansion Modular controller using a 7 slot rack interconnected with a 10 slot rack 2 3 6 32 None 6 None 16 Slot Inputs Outputs 4 5 6 7 8 9 10 8 None 16 16 8 None None 8 32 None None None 16 16 1 Data File 0 Output Image 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X INVALID Slot 1 outputs 0 5 Slot 3 outputs 0 15 Slot 4 o...

Page 60: ...ed from 1 to a maximum of 30 I e s b Word delimiter Required only if a word number is necessary as noted below s Word number Required if the number of inputs or outputs exceeds 16 for the slot Range 0 31 Bit delimiter b Terminal number Inputs 0 to 15 Outputs 0 to 15 Examples applicable to the controller shown on page 4 6 O 3 15 Output 15 slot 3 O 5 0 Output 0 slot 5 O 10 11 Output 11 slot 10 I 2 1...

Page 61: ...B3 252 0 Can also be expressed as bit 4032 Address B3 4032 Element Format Explanation Examples B Bit type file Bf e b f File number Number 3 is the default file A file number between 10 255 can be used if additional storage is required B3 3 14 Bit 14 element 3 Element delimiter e Element number Ranges from 0 to 255 These are 1 word elements 16 bits per element B3 252 0 Bit 0 element 252 Bit delimi...

Page 62: ...e Assign timer addresses as follows Format Explanation T Timer Tf e f File number Number 4 is the default file A file number between 10 255 can be used if additional storage is required Element delimiter e Element number Ranges from 0 to 255 These are 3 word elements See figure above Example T4 0 Element 0 timer file 4 Address bits and words by using the format Tf e s b where Tf e is explained abo...

Page 63: ...ollows Format Explanation C Counter Cf e f File number Number 5 is the default file A file number between 10 255 can be used if additional storage is required Element delimiter e Element number Ranges from 0 to 255 These are 3 word elements See figure above Example C5 0 Element 0 counter file 5 Address bits and words by using the format Cf e s b where Cf e is explained above and is the word delimi...

Page 64: ...ed Internal Use are not addressable Assign control addresses as follows Format Explanation R Control file Rf e f File number Number 6 is the default file A file number between 10 255 can be used if additional storage is required Element delimiter e Element number Ranges from 0 to 255 These are 3 word elements See figure above Example R6 2 Element 2 control file 6 Address bits and words by using th...

Page 65: ...at Explanation N Integer file Nf e b f File number Number 7 is the default file A file number between 10 255 can be used if additional storage is required Element delimiter e Element number Ranges from 0 to 255 These are 1 word elements 16 bits per element Bit delimiter b Bit number Bit location within the element 0 to 15 Examples N7 2 Element 2 integer file 7 N7 2 8 Bit 8 in element 2 integer fil...

Page 66: ...fset value in S 24 is the offset in elements For example an offset value of 2 will offset T4 0 ACC to T4 2 ACC which is 2 elements 6 words The number in S 24 can be a positive or negative integer resulting in a positive or negative offset You can use more than one indexed address in your ladder program All indexed addresses will have the same offset stored in word S 24 You can manipulate the offse...

Page 67: ...e boundaries only if no indexed addresses exist in the O output I input or S status files This selection is made at the time you save your program The file order from start to finish is B3 T4 C5 R6 N7 x9 x10 x9 and x10 are application specific files where x can be of types B T C R N Example The figure below indicates the maximum offset for word address T4 3 ACC when allowing and disallowing crossi...

Page 68: ...t value upon file instruction completion Refer to the next page for a list of file instructions that use the symbol for addressing ATTENTION File instructions manipulate the offset value stored in word S 24 Make sure that you load the correct offset value in S 24 prior to using an indexed address that follows a file instruction Otherwise unpredictable operation could occur resulting in possible pe...

Page 69: ...sible personal injury and or damage to equipment The following paragraphs explain user created files as they apply to Bit Shift instructions Sequencer instructions and File Copy and File Fill instructions Bit Shift Instructions The figure below shows a user defined file within bit data file 3 For this particular user defined file enter the following parameters when programming the instruction B3 2...

Page 70: ...e 3 6 This is the specified length of the file 6 elements beyond the starting address totals 7 elements You can use user defined integer files or bit files with sequencer instructions depending on the application You can program as many files as you like within another file However be careful that the files do not overlap Address of the user defined file is B3 4 Length of the file is 6 elements be...

Page 71: ...teger The file is N7 14 specified as 6 elements long The second example is a user defined file within Data File 0 Output Image We used this particular data file configuration in regard to I O addressing on page 4 6 Here we are defining a file 5 elements long Note that for the output file and the input file as well an element is always one word referenced as the slot and word taken together For exa...

Page 72: ...allocate timers T4 0 through T4 99 As described on page 4 9 timers are 3 word elements By assigning timer T4 100 you allocate 100 elements using 300 words of memory So whether you use timers T4 0 through T4 98 later in the program they are allocated in memory Obviously you can keep the size of your data files to a minimum by assigning addresses beginning at element 0 of each data file and trying t...

Page 73: ...ement in the file is used in your program For example if you are using element B3 5 you cannot delete B3 0 through B3 4 even if you aren t using them in your program Important Make certain that you do not inadvertently delete data originally reserved for indexed addressing Unexpected operation will result You can enter integer constants directly into many of the instructions you program The range ...

Page 74: ...llowing in mind in creating and applying your ladder logic Important During the processor scan M0 and M1 data can be changed by the processor according to ladder diagram instructions addressing the M0 and M1 files During the same scan the specialty I O module can change M0 and M1 data independent of the rung logic applied during the scan Addressing M0 M1 Files The addressing format for M0 and M1 f...

Page 75: ... e s b Mf e s b Mf e s b L Mf e s b U Mf e s b f file 0 or 1 If you need to show the state of the M0 or M1 addressed bit you can transfer the state to an internal processor bit This is illustrated below where an internal processor bit is used to indicate the true false state of a rung This rung will not show its true rungstate because the EQU instruction is always shown as true and the M0 instruct...

Page 76: ... ladder program The COP instructions below copy data from a processor bit file and integer file to an M0 file Suppose the data is configuration information affecting the operation of the specialty I O module COP COPY FILE Source B3 0 Dest M0 1 0 Length 16 COP COPY FILE Source N7 0 Dest M0 1 16 Length 27 S 1 15 First scan bit It makes this rung true only for the first scan after entering the Run mo...

Page 77: ...eries B 1 93 ms 1 58 ms plus 0 67 ms per word SLC 5 02 Series C 1 16 ms 0 95 ms plus 0 40 ms per word If you are using a Series B processor add 1 93 ms to the program scan time for each bit instruction addressed to an M0 or M1 data file If you are using a Series C processor add 1 16 ms If you are using a Series B processor add 1 58 ms plus 0 67 ms per word of data addressed to the M0 or M1 file Th...

Page 78: ...s provide equivalent operation to those of figure A by substituting XIC instruction B3 10 for XIC instruction M0 2 1 1 in rung 2 Scan time is reduced by approximately 1 ms Series B processor 1 B3 12 M0 2 1 1 B3 14 M0 2 1 1 B3 10 2 B3 12 B3 10 B3 14 M0 2 1 1 B3 10 1 2 The following figure illustrates another economizing technique The COP instruction addresses an M1 file adding approximately 4 29 ms...

Page 79: ...N10 0 Specialty I O Modules with Retentive Memory Certain specialty I O modules retain the status of M0 M1 data after power is removed See your specialty I O module user s manual This means that an OTE instruction having an M0 or M1 address remains on if it is on when power is removed A hold in rung as shown below will not function as it would if the OTE instruction were non retentive on power los...

Page 80: ... formats that you can select on the HHT Word addresses begin with the file identifier G and the slot number you have assigned to the specialty I O module In this case the slot number is 1 Four words have been created addresses G1 0 through G1 3 Important Word 0 of the G file is configured automatically by the processor according to the particular specialty I O module Word 0 is read only address DE...

Page 81: ...ta offline under the I O configuration function only With the decimal and hex bcd formats you edit data at the word level G1 1 234 decimal format G1 1 00EA hex bcd format With the binary format you edit data at the bit level G1 19 1 Important Word 0 of the G file is configured automatically by the processor according to the particular specialty I O module Word 0 cannot be edited Allen Bradley Part...

Page 82: ...r programming works we chose to use bit relay logic instructions since they are the easiest to understand The three instructions discussed in this section are Examine if Closed XIC Analogous to the normally open relay contact For this instruction we ask the processor to Examine if the contact is Closed Examine if Open XIO Analogous to the normally closed relay contact For this instruction we ask t...

Page 83: ... a location in the processor s data files where the on off state of the bit is stored Addresses of the above instructions indicate they are located in the Bit data file B3 bits 10 11 and 12 OTE XIC XIO Bit Data File 3 Element 0 Bit Status 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 In the preceding diagram we indicated that bit 10 is logic 1 on bit 11 is logic 0 off and b...

Page 84: ...ng the OTE output instruction will become or remain true We then say that rung conditions are true When the processor does not find a continuous path of true input instructions in a rung the OTE output instruction will become or remain false We then say that rung conditions are false The figure below shows the on off state of output B3 12 as determined by the changing states of the inputs in the r...

Page 85: ...l continuity is Parallel OR logic This means that when one or another path of logic is true energize the output Example Parallel Inputs A C B In the above example if A or B is true energize C Use branching to form parallel logic in your user program Branches can be established at both input and output portions of a rung The upper limit on the number of levels which can be programmed in a branch st...

Page 86: ...ogic path rung logic is not enabled and the output instruction logic will not be true Output is not energized Example Parallel Input Branching A B D C In the above example either A and B or C provides a true logical path Output Branching You can program parallel outputs on a rung to allow a true logic path to control multiple outputs When there is a true logic path all parallel outputs become true...

Page 87: ...ue logic path to E Nested Branching With the SLC 5 02 processor input and output branches can be nested to avoid redundant instructions to speed up processor scan time and provide more efficient programming A nested branch is a branch that starts or ends within another branch You can nest branches up to four levels deep Example Nested Input and Output Branches Important APS allows all branching co...

Page 88: ... Program Basics 5 7 Nested branches can be converted into non nested branches by repeating instructions to make parallel equivalents Example A B C F D E A B C F D E C Nested Branch Non nested Equivalent Parallel Branch ...

Page 89: ...ta file bits then executes the program instructions individually rung by rung from the beginning to the end of the program as it does it updates the data file bits and the appropriate output data file bits accordingly When XIC instruction I 0 1 goes true because an external momentary push button closes Rung 1 is evaluated as false because XIC instruction B3 11 is false at this time Rung 2 is evalu...

Page 90: ...ruction B3 11 de energizing output O 0 2 Instruction B3 10 prevents interaction between instructions B3 12 and B3 11 Status Bit I 0 1 Rung B3 10 B3 12 O 0 2 B3 11 1 2 3 4 B3 10 1 I 0 0 1 B3 11 B3 12 2 B3 11 B3 12 B3 10 2 B3 10 I 0 0 1 B3 11 3 4 B3 11 I 0 0 1 O 0 0 As previously indicated the processor executes instructions individually rung by rung from the beginning to the end of the program This...

Page 91: ... indicates how the instructions are executed when XIC instruction I 0 1 changes state I 0 1 represents an external momentary contact push button T T F F T T T T F T T T T T F T F T F T T T T T T T F T F F F T T F F F F F F Instruction Execution T true at time of execution F false at time of execution XIC I 0 1 Goes True Goes False Scan 1000 Scan 1001 F F T F F F T T T F F T T F T T F F T T T T F F...

Page 92: ... to the user program The processor executes the entire list of instructions in ascending rung order Status bits are updated according to logical continuity rules as the program scan moves from instruction to instruction through successive ladder rungs The I O scan and program scan are separate independent functions Thus any status changes occurring in external input devices during the program scan...

Page 93: ...an Program Scan 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 O 0 0 1 First scan after input goes true scan 1000 Input Data File Ladder Program Output Data File O 0 I 0 Instructions Intensified Output Bit De energized Input bit energized I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 ...

Page 94: ... 0 0 0 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 O 0 0 1 Input Data File Ladder Program Output Data File O 0 I 0 Output Bit Energized Input Bit De energized Instructions are normal intensity First scan after input goes false scan 2000 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 O 0 0...

Page 95: ...3 Configure the I O 4 Name the ladder program and main program file Clearing the Memory of the HHT To create a new program clear the HHT memory DEFAULT program 1 Energize your HHT After it goes through the self diagnostic tests the main menu display appears SLC 500 PROGRAMMING SOFTWARE Rel 2 03 1747 PTA1E Allen Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 PRESS A FUNCTION KEY ...

Page 96: ...stem 76 1 Reserved 0 2 Ladder 5 ARE YOU SURE F1 F2 F3 F4 F5 YES OFL NO 4 Press F2 YES This clears the HHT memory and the following display appears File Name Prog Name DEFAULT File Name Type Size Instr 0 System 1 Reserved 2 Ladder F1 F2 F3 F4 F5 EDT_DAT SEL_PRO EDT_I O OFL CLR_MEM Configuring the Controller After clearing the HHT memory you must configure the processor and I O structure for your ap...

Page 97: ...47 L511 CPU 1K USER MEMORY Slot 1 NONE F1 F2 F3 F4 F5 MOD_RCK MOD_SLT DEL_SLT UND_SLT The display shows that the processor module we just entered is assigned to slot 0 It also shows the default rack selection 1746 A4 For this example you do not have to change the rack selection If you are using a different rack press F1 MOD_RCK then F1 RACK 1 Select the appropriate rack using the and keys then pre...

Page 98: ...t 1 1746 IA4 4 INPUT 100 120 VAC F1 F2 F3 F4 F5 MOD_RCK MOD_SLT DEL_SLT UND_SLT 5 Call up another slot number using the and keys Press the key once for slot 2 Assign the other slots by following the procedure for slot 1 Your controller is now fully configured The configuration can be changed at any time by using the functions shown here UND_SLT can be used to undelete a slot if it is accidently re...

Page 99: ...igure a specialty I O module not listed 1 Configure your SLC 5 02 processor racks and standard I O as described earlier 2 Assign the specialty I O module to an open slot in your rack We are using slot 6 in a 1747 A7 7 slot rack for the following example We are also using the Remote I O Scanner Module catalog number 1747 SN for this example Refer to RIO Scanner User Manual catalog number 1747 NM005...

Page 100: ...Press F4 ADV_SIZ to view or modify the I O and M0 M1 file sizes Advanced I O Size Setup Note All sizes are in words Slot 6 Output Size 32 M0 File Size 0 Input Size 32 M1 File Size 0 Scanned Output Size 32 Scanned Input Size 32 ENTER SCANNED OUTPUT 32 F1 F2 F3 F4 F5 OFL The default for the scanned output size is 32 words In this example to reduce the processor scan time enter 16 words 7 Type 16 the...

Page 101: ...previous display Press F2 MOD_SET to view or modify the G file contents The following display appears with the cursor positioned on G6 0 Address HEX BCD Data G6 0 2020 G6 1 0000 G6 2 0000 ELEMENT CANNOT BE EDITED F1 F2 F3 F4 F5 OFL BIN DEC HEX BCD NEXT_PG PREV_PG Indicates Slot 6 Word 0 of the G file is configured automatically by the processor according to the particular specialty I O module Word...

Page 102: ...2 processor only This function allows a specialty I O module to interrupt the normal processor operating cycle in order to scan a specified subroutine file This is described in detail starting on page 31 1 Interrupt operation for a specific module is described in the user s manual for the module Naming the Ladder Program In addition to configuring your controller you must give the program a name o...

Page 103: ... Program Name 1000 F1 F2 F3 F4 F5 OFL PROGRAM FILE Important If you forget to press the SPACE key the program name is now 1000ULT Whenever you create a new program name or change the name if the previous name consists of more characters than the new one the SPACE key must be used to clear the additional characters To correct the name repeat the above procedure Naming Your Main Program File Unlike ...

Page 104: ...1000 File Name Type Size Instr 0 System 1 Reserved 2 222 Ladder F1 F2 F3 F4 F5 CHG_NAM CRT_FIL EDT_FIL OFL DEL_FIL MEM_MAP Program Name Main Program File Name File Size The program directory now shows the name of the program which is 1000 and the name of the main program file which is 222 The display also shows the file sizes At this point asterisks are displayed because no ladder programs are ent...

Page 105: ...ny password Important There is no password override to defeat the protection Contact your Allen Bradley representative if you are not able to locate your password Entering Passwords Ordinarily you do not enter a password until your ladder program is completed tested and ready to be applied This avoids having to type in the password each time you edit the program download edit again and so on Passw...

Page 106: ...2 F3 F4 F5 ENTER NEW PASSWORD XXX OFL 5 Press ENTER You are prompted to verify the password by re typing it File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 1 Reserved 2 222 Ladder F1 F2 F3 F4 F5 RE ENTER NEW PASSWORD OFL 6 Type 123 again The password is now accepted 7 Cycle power to the HHT for the password to take effect After the HHT powers up you are requested to enter the passw...

Page 107: ...ss ENTER To change a password or master password do one of the following Changing Passwords Changing Master Passwords 1 Press F3 PASSWRD 1 Press F3 PASSWRD 2 Press F1 ENT 2 Press F4 ENT_MAS 3 Type existing password and press ENTER 3 Type the existing master password and press ENTER 4 Type the new password and press ENTER 4 Type the new master password and press ENTER 5 Re type the new password and...

Page 108: ...r error handler STI interrupts and interrupt programs require subroutine program files These are described later in this manual Valid file numbers range from 3 to 255 Creating a Subroutine Program File using the Next Consecutive File Number Create subroutine program file 3 1 Begin at the program maintenance display File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 1 Reserved 2 222 La...

Page 109: ...the HHT Creating a Subroutine Program File using a Non Consecutive File Number In this example create subroutine program file 6 1 From the above display press F2 CRT_FIL 2 Press 6 then ENTER File 6 is created but the display does not change 3 Press the key 3 times to view file 6 File Name 222 Prog Name 1000 File Name Type Size Instr 3 Ladder 4 Undefined 5 Undefined 6 Ladder F1 F2 F3 F4 F5 CHG_NAM ...

Page 110: ...222 Prog Name 1000 File Name Type Size Instr 3 Ladder 4 Undefined 5 Undefined 6 Ladder ENTER FILE NUMBER F1 F2 F3 F4 F5 OFL 2 You are prompted for the file number to delete Press 6 then ENTER The following display appears File Name 222 Prog Name 1000 File Name Type Size Instr 3 Ladder 4 Undefined 5 Undefined 6 Ladder DATA FORCES IN LAST STATE DELETE F1 F2 F3 F4 F5 OFL YES NO 3 Press F2 YES to dele...

Page 111: ...5 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL OTE O0 3 0 0 END These numbers in the upper right corner of the display provide you with the following ladder program information When you locate the cursor on an instruction as shown below the HHT displays the instruction mnenomic and address in the upper left corner of the display The HHT displays the full address For example when you assign the addre...

Page 112: ...e editing program file 2 and the cursor is located on rung 0 nest level 0 branch level 0 and not presently on an editable instruction the cursor is located on the END of program statement F1 F2 F3 F4 F5 2 0 0 0 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL END 3 Press F1 INS_RNG The following display appears F1 F2 F3 F4 F5 2 0 0 0 INS_INST BRANCH MOD_INST ACP_RNG OFL END I I The I symbol in the power...

Page 113: ...s symbol indicates that the HHT has automatically shifted for you You can then enter the file type I O S B T C R and N 4 At the ENTER BIT ADDR prompt type the address I 1 0 which is an abbreviated form of the address The display appears as follows ENTER BIT ADDR I 1 0 ZOOM on XIC NAME EXAMINE IF CLOSED BIT ADDR F1 F2 F3 F4 F5 2 0 0 0 5 Before continuing make certain that the information entered is...

Page 114: ...g display appears F1 F2 F3 F4 F5 OFL 2 0 0 0 END I I L U Notice that the cursor is now located on the right power rail of rung 0 In the next section the Output Energize instruction is inserted to the left of the cursor Further instructions may be entered in the same way Entering an Output Energize Instruction 1 Press F3 for the output energize instruction The following display appears ENTER BIT AD...

Page 115: ...inue with the additional editing examples save the work you have done so far Whenever you are adding or editing rungs of a program it is recommended to periodically save your program In the event of a power loss to the HHT any edits that you have made up to this point are not recoverable 4 At this point the rung is entered and accepted Now save this rung and continue editing Press ENTER to display...

Page 116: ...on always places the new rung above the rung on which the cursor is positioned This places the new rung between the first rung and the END of program statement If you did not move the cursor the new rung is inserted above the original rung The display appears as follows END F1 F2 F3 F4 F5 2 1 0 0 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL I I Position of the new rung indicated by the I symbol in t...

Page 117: ...NERGIZE BIT ADDR F1 F2 F3 F4 F5 2 0 0 0 7 Type the address O 3 1 then press ENTER then F5 ACCEPT The cursor is now positioned on the output energize instruction and the following display appears Notice that with the cursor placed on the output instruction the instruction mnemonic and address are displayed in the upper left corner The cursor location is also displayed in the upper right corner This...

Page 118: ... the starting point of the branch to the left of the cursored instruction or at the cursor F5 Delete Branch Removes a branch and the instructions within the branch from a rung In this example use the insert branch command The other branching commands are described starting on page 7 19 1 Starting from the previous display press ESC twice to bring up the following menu display END F1 F2 F3 F4 F5 2 ...

Page 119: ...r is now positioned on the branch start and you are prompted to move the cursor to the branch target Press the key once The cursor is now positioned to the left of the examine if closed instruction END F1 F2 F3 F4 F5 2 1 0 0 OFL I I SELECT BRANCH TARGET PRESS ENTER 5 Press ENTER The branch is inserted around the examine if closed instruction END F1 F2 F3 F4 F5 2 1 1 1 OFL I I EXT_UP EXT_DWN APP_BR...

Page 120: ... press ENTER then F5 ACCEPT The display appears as follows L U END F1 F2 F3 F4 F5 2 1 1 1 OFL I I I I 4 To accept the new rung into your program press ESC twice then F5 ACP_RNG The rung is now a part of your program as indicated by the absence of I s in the power rails END F1 F2 F3 F4 F5 2 2 0 0 OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG 5 Press ENTER for additional menu options then press F4 SAVE...

Page 121: ... menu functions F1 F2 F3 F4 F5 2 0 0 0 OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG The cursor is located on the left power rail of rung 0 END 2 To place the new instruction between the existing input and output instructions press the key twice to place the cursor on the output instruction The display changes as follows F1 F2 F3 F4 F5 2 0 0 0 2 OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OTE O0 3 0 0...

Page 122: ...Press F5 ACCEPT This inserts the instruction and address into the rung The following display appears I F1 F2 F3 F4 F5 OFL I L U 2 0 0 0 3 OTE O0 3 0 0 NO FORCE END 7 Press ESC twice Then press F5 ACP_RNG The new examine if closed instruction is now part of your rung as indicated by the absence of I s in the power rails F1 F2 F3 F4 F5 2 1 0 0 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL END Once agai...

Page 123: ...f closed instruction in the first rung rung 0 of the program from I 1 0 2 to I 1 0 1 The new rung should appear as follows I 1 0 0 O 3 0 0 I 1 0 1 Change this address 1 From the previous save and continue display press ENTER The following display appears F1 F2 F3 F4 F5 2 0 0 0 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL END 2 To change the address of the second examine if closed instruction press t...

Page 124: ... the second method you must press the SHIFT key for the file type I O B Also if the previous address contains more characters than the new one you must use the SPACE and the keys to clear each remaining character before pressing ENTER When the new address is displayed on the prompt line ZOOM on XIC NAME EXAMINE IF CLOSED BIT ADDR I1 1 0 1 ENTER BIT ADDR I1 1 0 1 F1 F2 F3 F4 F5 2 0 0 0 2 ACCEPT EDT...

Page 125: ...following display appears F1 F2 F3 F4 F5 2 0 0 0 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL END 2 To change the examine if closed instruction press the key twice With the cursor positioned on the examine if closed instruction with address I1 1 0 1 press F2 MOD_RNG The following display appears F1 F2 F3 F4 F5 2 0 0 0 2 OFL END INS_INST BRANCH MOD_INST ACP_RNG XIC I1 1 0 1 NO FORCE I I 3 Press F3 MO...

Page 126: ...nch function The branch menu contains several different branching functions This example deals with those functions Extending a Branch Up Use the extend branch up command to create a new branch level on an existing branch above your cursor location The new branch shares the same start and target locations as the branch on which the cursor is located In this example modify rung 1 of your program to...

Page 127: ... F4 F5 2 1 1 1 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL END Cursor Location 3 Press F2 MOD_RNG then F2 BRANCH The following menu display appears F1 F2 F3 F4 F5 2 1 1 1 OFL END EXT_UP EXT_DWN APP_BR DEL_BR INS_BR I I I I 4 Press F1 EXT_UP The display changes as follows I I I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL END EXT_UP EXT_DWN APP_BR DEL_BR INS_BR 5 Press ESC The proper menu is displayed I I I I I...

Page 128: ...I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL END L U 8 Now insert the examine if closed instruction with address B3 2 Since the cursor is located on the right rail of the branch press F1 9 In the zoom display type the address B3 2 then press ENTER then F5 ACCEPT The display appears as follows I I I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL END L U Notice that the length of both branches has increased 10 Press ESC tw...

Page 129: ...0 0 O 3 0 1 B3 1 I 1 0 1 Add this branch level to the rung B3 2 B3 3 1 From the previous save and continue display press ENTER The following display appears F1 F2 F3 F4 F5 2 0 0 0 OFL END INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG 2 Because the cursor is positioned on the left power rail of rung 0 move the cursor to a position within nest level 1 branch level 2 of rung 1 by pressing the key then the k...

Page 130: ...ress ESC The proper menu is displayed I I I I I I I F1 F2 F3 F4 F5 2 1 1 3 I OFL INS_INST BRANCH MOD_INST ACP_RNG 6 Now insert the examine if closed instruction with address B3 3 by pressing F1 INS_INST then F1 BIT then F1 7 In the zoom display type the address B3 3 then press ENTER then F5 ACCEPT The display appears as follows I I I I I I I F1 F2 F3 F4 F5 2 1 1 3 I OFL L U Notice that the length ...

Page 131: ...3 1 I 1 0 1 Add this branch to the rung B3 2 B3 3 O 3 0 2 1 From the previous save and continue display press ENTER for the main editing display menu F1 F2 F3 F4 F5 2 0 0 0 OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG 2 Press the key once then the key three times to position the cursor on the right power rail of branch level 0 F1 F2 F3 F4 F5 2 1 1 0 OFL L U 3 Press F2 MOD_RNG then F2 BRANCH The bran...

Page 132: ...ey once to place the cursor to the right of the output I I I I I I I I F1 F2 F3 F4 F5 2 1 1 0 6 OFL SELECT BRANCH TARGET PRESS ENTER 6 Press ENTER The branch is placed around the output I I I I I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL EXT_UP EXT_DWN APP_BR DEL_BR INS_BR 7 Press ESC to return to the editing menu display I I I I I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL INS_INST BRANCH MOD_INST ACP_RNG ...

Page 133: ... and Undelete Commands Delete commands are used to delete branches instructions and rungs In addition undelete commands are used to copy an instruction or a rung and create new instructions or rungs Deleting a Branch Use the delete branch command to remove a parallel branch and the instructions located within the branch Modify rung 1 of your program to appear as follows I 1 0 0 O 3 0 1 I 1 0 1 O 3...

Page 134: ...lowing display appears with the cursor positioned on the left power rail of rung 1 I I I I I I I I F1 F2 F3 F4 F5 2 1 0 0 OFL INS_INST BRANCH MOD_INST ACP_RNG 3 To remove branch level 1 position the cursor on the branch by pressing the key then the key The display appears as follows I I I I I I I I F1 F2 F3 F4 F5 2 1 1 1 OFL INS_INST BRANCH MOD_INST ACP_RNG 4 Press F2 BRANCH the branch menu displa...

Page 135: ...he Run mode the status bits associated with the instructions that are energized true or forced on remain in that state even after they are deleted This can cause incorrect program operation if these addresses are associated with other instructions 6 Press F2 YES to delete the branch The display changes as follows I I I I I I F1 F2 F3 F4 F5 2 1 1 1 END OFL EXT_UP EXT_DWN APP_BR DEL_BR INS_BR 7 To r...

Page 136: ...place the cursor on the instruction to be deleted Then press F2 MOD_RNG The following display appears I I F1 F2 F3 F4 F5 2 0 0 0 2 END OFL INS_RNG BRANCH MOD_INST ACP_RNG XIO I1 1 0 1 NO FORCE 3 Press ENTER to display additional menu functions I I F1 F2 F3 F4 F5 2 0 0 0 2 END OFL DEL_INST UND_INST XIO I1 1 0 1 NO FORCE 4 Press F2 DEL_INST then F2 YES to confirm the deletion 5 Press ENTER then F5 A...

Page 137: ...ied The display appears as follows F1 F2 F3 F4 F5 2 1 1 1 2 END OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG XIC I1 1 0 2 NO FORCE 3 Press F2 MOD_RNG then ENTER for additional menu functions Then press F2 DEL_INST then F2 YES to confirm the deletion and place the instruction in the delete buffer 4 Press F4 UND_INST to re insert the instruction into rung 1 then ENTER then press F5 ACP_RNG The display...

Page 138: ...F4 F5 2 0 0 0 2 END OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG XIC I1 1 0 1 NO FORCE Deleting and Copying Rungs Use the delete and undelete rung commands to copy rung 0 and create rungs 2 and 3 After copying the rungs change the instruction addresses so that your program appears as follows I 1 0 0 O 3 0 0 I 1 0 0 O 3 0 1 I 1 0 1 O 3 0 2 I 1 0 1 I 1 0 3 O 3 0 3 I 2 0 0 I 2 0 1 O 3 0 4 I 2 0 2 1 Sta...

Page 139: ...tement F1 F2 F3 F4 F5 2 2 0 0 END OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG 6 Since the two new rungs are identical at this point you are not concerned with the position of the next rung With the cursor positioned on the left power rail of the first new rung press F5 UND_RNG The second new rung is inserted above the previous one 2 2 0 0 F1 F2 F3 F4 F5 OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG 7 ...

Page 140: ...EDT_DAT 9 To change the address to I 1 0 3 press the key seven times to position the cursor on the bit element 10 Press 3 then ENTER then F5 ACCEPT The new address is assigned to the instruction I I 2 2 0 0 1 F1 F2 F3 F4 F5 XIC I1 1 0 3 NO FORCE 11 To change the next address press then ZOOM The zoom display for this instruction appears ZOOM on XIC NAME EXAMINE IF CLOSED BIT ADDR I1 1 0 3 F1 F2 F3 ...

Page 141: ...struction appears ZOOM on OTE NAME OUTPUT ENERGIZE BIT ADDR O0 3 0 0 F1 F2 F3 F4 F5 2 2 0 0 3 EDT_DAT ACCEPT ENTER BIT ADDR O0 3 0 0 14 Press the key seven times to position the cursor on the bit element 15 Press 3 then ENTER then F5 ACCEPT 16 To complete editing this rung press ESC then F5 ACP_RNG 17 Repeat the above procedure for the instructions in rung 3 18 Save and compile your changes Abando...

Page 142: ... as OTE O 3 4 forced I O instructions a specific rung The HHT search function is done only within the existing program file Subroutine files require that you go to those files to initiate another search The search function is accessible offline from the edit file menu display F3 SEARCH or 2 0 0 0 F1 F2 F3 F4 F5 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL online from the monitor file menu display F4...

Page 143: ...u of the available instruction symbols and or mnemonics F4 UP DOWN Toggles the search direction within the program When UP is displayed the search starts at the cursor location and continues down to the end of the program then wraps around to the start of the program When DOWN is displayed the search starts at the cursor location and continues up to the start of the program then wraps around to th...

Page 144: ...F4 F5 CUR INS CUR OPD NEW INS FORCE UP OFL The instruction mnemonic is displayed here 3 There are two ways to select the examine if closed instruction either use the key to position the cursor on an examine if closed instruction then press F1 CUR INS or press F3 NEW INS then F1 BIT then F1 then ENTER The display changes as follows with the cursor on the first examine if closed instruction Notice t...

Page 145: ...irst instruction in rung 1 nest level 1 branch level 0 F1 F2 F3 F4 F5 CUR INS CUR OPD NEW INS FORCE UP OFL XIC NO FORCE XIC I1 1 0 0 2 1 1 0 1 END You may continue to search for each XIC instruction in the program by pressing ENTER When you reach the last occurrence of this instruction in the program the cursor wraps around to the start of the program 6 To conclude this search procedure and clear ...

Page 146: ...s is displayed in the search buffer 2 0 0 0 F1 F2 F3 F4 F5 CUR INS CUR OPD NEW INS FORCE UP OFL I 1 1 4 Press ENTER again to find the first occurrence of the address which is the second instruction in rung 0 F1 F2 F3 F4 F5 CUR INS CUR OPD NEW INS FORCE UP OFL I 1 2 NO FORCE XIC I1 1 0 1 2 0 0 0 2 5 Press ENTER again to find the next occurrence of the address which is located in rung 1 nest level 1...

Page 147: ...ss ESC Searching for a Particular Instruction with a Specific Address In most applications you search for the location of an instruction and its associated address In the procedure below the search is for the location of output energize OTE O 3 4 1 Use the cursor keys to position the cursor on the left power rail of rung 0 2 0 0 0 F1 F2 F3 F4 F5 INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG OFL 2 Press F...

Page 148: ...the instruction Since this is an output energize instruction there should be only one occurrence of this instruction and address For other types of instructions such as the examine if closed XIC instructions that you saw earlier pressing ENTER finds each additional occurrence of the instruction with that address Reversing the Search Direction The default setting for the search direction is to sear...

Page 149: ...nd uploaded to the HHT Refer to chapter 10 for details regarding uploading a ladder program and chapter 13 for a detailed description of the force function In the Online Monitor mode use the search forced I O function to locate all forced inputs and outputs that are inserted in your program In the Offline monitor mode use the search forced I O function to locate all forced inputs and outputs that ...

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Page 154: ...ilable memory is updated Since programs are created or edited offline it is important to save your work before downloading it to the processor As mentioned in the previous chapter whenever you are creating a new program or editing an existing one you should periodically save your work In the event of a power loss to the HHT any edits that you have made up to that point are not recoverable Save and...

Page 155: ... processors Toggles between Yes and No This option allows you to protect proprietary program data and algorithms The protection takes affect only after the processor file is downloaded to a controller F2 Test Single Rung SLC 5 02 processor Toggles between Enable and Disable This option allows you to execute your program one rung at a time or a section at a time Use this function for debugging purp...

Page 156: ...py of the online processor program is resident on the terminal hard disk or in the HHT Otherwise you are not able to upload the program Yes Online access to the processor program and data table using a programming terminal is unrestricted This is the default No Online access to the processor program and data table is not permitted unless a matching copy of the online processor program is in the HH...

Page 157: ... verify if the indexed address the sum of the base address and the offset value is in the same data file as the base address The processor does check to ensure that the indexed address is contained within the data table address space Disallow The processor performs runtime checks on indexed addresses to ensure that the indexed address is contained within the same data file as the base address This...

Page 158: ... 3 B bit B3 15 1 1 4 T timer F1 F2 F3 F4 F5 CRT_DT DEL_DT NEXT_PG OFL PRG_SIZE PREV_PG This display shows one output file word and two input file words created by the I O configuration There are 16 words in the status file file 2 The number of words in the status file is determined by the particular processor fixed and SLC 5 01 processor 16 words SLC 5 02 processor 33 words There is one word in bi...

Page 159: ...s 1 output 2 input 16 status 1 bit If you had not saved your program after adding or deleting program files or modifying data files the following display appears with asterisks indicating that the program has not been compiled MEMORY LAYOUT F1 F2 F3 F4 F5 OFL data words used in data files instr used in program files instructions of available memory 3 Press ESC three times to return to the main men...

Page 160: ... is not compatible with the SLC 5 03 processor For the examples in this section the DH 485 network is configured as follows Node Address Network Device 0 APS Terminal 1 Hand Held Terminal 2 SLC 5 02 Processor 3 SLC 500 Processor 4 SLC 5 01 Processor Allen Bradley 1784 T45 T47 or Compatible Laptop SLC 500 20 I O Fixed Controller SLC 500 5 02 Modular I O Controller 1747 AIC Isolated 1747 PIC Interfa...

Page 161: ...ot previously attached to a processor the Who function is entered F2 WHO Allows you to view the nodes on the network run network diagnostics attach to and communicate with a specific node change a node configuration and set and clear ownership F3 PASSWRD Allows you to change a password in the HHT offline program F4 CLR_MEM Allows you to clear the HHT offline memory In the following example go onli...

Page 162: ...Description F1 PASSWORD Allows you to change the processor password master password F3 TRANSFER MEMORY Transfers processor RAM to EEPROM or EEPROM UVPROM to processor RAM F4 EDT_DAT Allows you to monitor or edit processor data files F5 MONITOR Allows you to observe the program operation of the processor program file that you specify Exceptions The function keys and menus vary depending on how the ...

Page 163: ...F2 WHO The following display appears Node Addr Device Max Addr Owner 2 5 02 31 3 500 20 31 4 5 01 31 0 APS 31 Node Addr 2 Baud Rate 19200 F1 F2 F3 F4 F5 DIAGNSTC ATTACH OFL OWNER NODE_CFG Current Node Asterisks indicate the node previously attached to Important The HHT uses top line editing This means that the information shown nearest the top of the display is the current node address For example...

Page 164: ...g downloading a program changing the processor operating mode clearing processor memory changing processor password master password monitoring a program viewing or modifying data files or clearing the processor memory F4 NODE_CFG Allows you to change the node address the maximum node address and the baud rate of each node F5 OWNER Allows you to clear or set ownership of the selected processor Sett...

Page 165: ...E The following display appears Node 2 Device Type 5 02 Firmware Rel 5 Series C Mode PRG Fault Code 0000H Program Name 1000 Forces Not Installed F1 F2 F3 F4 F5 OFL 3 To monitor the diagnostic display of the network press ESC then F5 NETWORK The following display appears Total Nodes 5 Max Addr 31 Msgs Sent 29736 Msgs Rcvd 202 Retries 0 Limit Exceeded 0 Bad Msgs Rcvd 0 NAK Sent 0 NAK Rcvd 0 Node Add...

Page 166: ...the HHT to node 4 Assume that the HHT and processor programs are identical 1 Start at the Who display Node Addr Device Max Addr Owner 2 5 02 31 3 500 20 31 4 5 01 31 0 APS 31 Node Addr 2 Baud Rate 19200 F1 F2 F3 F4 F5 DIAGNSTC ATTACH OFL OWNER NODE_CFG Current Node 2 Press the twice to select node 4 The display appears as follows Node Addr Device Max Addr Owner 4 5 01 31 0 APS 31 1 TERMINAL 31 2 5...

Page 167: ...he Who display Node Addr Device Max Addr Owner 2 5 02 31 3 500 20 31 4 5 01 31 0 APS 31 Node Addr 2 Baud Rate 19200 F1 F2 F3 F4 F5 DIAGNSTC ATTACH OFL OWNER NODE_CFG Current Node 2 Use the and keys to change the order of the nodes listed if necessary Press F3 ATTACH since the current node is already 2 The following menu is displayed Program Directory Programmer Processor F1 F2 F3 F4 F5 PRG CLR_PRC...

Page 168: ...rogramming device and processor on a DH 485 network must have a unique address from 0 through 31 The default node address of a processor is 1 and a programmer is 0 Consequences of Changing a Processor Node Address Remember that the processor node address resides in the status data file word S 15 of a program This means that when you overwrite the contents of processor memory by using the download ...

Page 169: ...dress you must change the maximum node addresses to include that address Failure to do so causes the devices on the network to ignore the new device When you cycle power to a Series A SLC 500 or SLC 5 01 processor the maximum node address returns to the default selection of 31 Changing the Baud Rate The baud rate of a processor or programming device is the speed at which it communicates with other...

Page 170: ...NAL 5 Node Addr 3 Baud Rate 19200 F1 F2 F3 F4 F5 DIAGNSTC ATTACH OFL OWNER NODE_CFG Indicates that node 5 is owned by node 0 2 To claim ownership of node 5 press the key twice then press F5 OWNER The display changes as follows Node Addr Device Max Addr Owner 5 5 02 5 0 1 TERMINAL 5 3 500 20 5 4 5 01 5 Node Addr 5 Baud Rate 19200 F1 F2 F3 F4 F5 SET_OWNR OFL CLR_OWNR 3 Press F1 SET_OWNR Since the pr...

Page 171: ...de address as low as possible The highest numbered node should have its maximum node address set to its own address Set the maximum node address the same for all nodes on the network Make certain that the baud rate settings of all nodes are the same A terminal only communicates with processors set at the same baud rate The baud rate change for a processor does not take effect until you cycle power...

Page 172: ...Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 PRESS A FUNCTION KEY SELFTEST TERM PROGMAINT OFL UTILITY 2 Press F5 UTILITY The following display appears if a password is required SLC 500 PROGRAMMING SOFTWARE Rel 2 03 1747 PTA1E Allen Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 ENTER PASSWORD OFL or this display appears after the password is entered or if a password is not ...

Page 173: ...3 DEFAULT FILE IN PROCESSOR PRG DEFAULT indicates that a program is not in the pro cessor or this display appears if a program is in processor memory Program Directory Programmer Processor F1 F2 F3 F4 F5 CLR_PRC DWNLOAD OFFLINE MODE UPLOAD Prog 1000 Prog 1952 File 222 File Exec Files 4 Exec Files 3 Data Files 9 Data Files 9 PROGRAM FILES DIFFER PRG 1952 or anything other than DEFAULT indicates tha...

Page 174: ...rs These functions are change processor operating mode transfer memory monitor or edit data files monitor online program operation ATTENTION If forces are installed in an offline program they are downloaded to the processor in their last state Be absolutely certain that the installed forces will not cause unexpected machine operation before continuing Any changes made to a program running in a pro...

Page 175: ...TA1E Allen Bradley Company Copyright 1990 All Rights Reserved F1 F2 F3 F4 F5 ENTER PASSWORD OFL or this display appears after the password is entered for the current offline program which is 1000 or if a password is not required File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 77 1 Reserved 0 2 222 Ladder 13 3 Ladder 1 F1 F2 F3 F4 F5 ONLINE WHO PASSWRD OFL CLR_MEM 3 Press F2 WHO the...

Page 176: ...00 Prog 03CLOCK File 222 File 03M Exec Files 4 Exec Files 3 Data Files 9 Data Files 9 PROGRAM FILES DIFFER PRG 5 Press F2 UPLOAD The display changes as follows Program Directory Programmer Processor F1 F2 F3 F4 F5 NO YES Prog 1000 Prog 03CLOCK File 222 File 03M Exec Files 4 Exec Files 3 Data Files 9 Data Files 9 OVERWRITE EXISTING PROGRAM PRG 6 Press F2 YES to replace program 1000 with 03CLOCK in ...

Page 177: ...d data as it is being executed Use the search function Force I O Upload a processor program to HHT RAM Monitor and edit data Program Mode The Program mode facilitates the transfer of programs through the download and upload function In this mode the processor does not scan or execute the ladder program and all outputs are de energized regardless of their current states Once a program is downloaded...

Page 178: ...cutes a single operating cycle which includes reading the inputs executing the ladder program and updating all data without energizing output circuits The remaining portion of this chapter takes you step by step through changing processor modes The previous chapters described going online to a processor and downloading uploading programs Changing the Mode To change any mode Program Test or Run the...

Page 179: ...equests you to confirm your selection File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 77 1 Reserved 0 2 222 Ladder 13 3 Ladder 1 ARE YOU SURE F1 F2 F3 F4 F5 YES NO PRG 4 Press F2 YES The display changes as follows File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 77 1 Reserved 0 2 222 Ladder 13 3 Ladder 1 F1 F2 F3 F4 F5 RUN TEST RUN PROGRAM Display toggles between the...

Page 180: ...questing the file number you want to monitor File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 76 1 Reserved 0 2 222 Ladder 56 3 Ladder 0 ENTER FILE NUMBER F1 F2 F3 F4 F5 RUN 3 To view the main program file 2 press 2 then ENTER The ladder program display appears The cursor location is displayed in the upper right corner This indicates that the cursor is located in program file 2 rung...

Page 181: ...e video block This section describes the types of data files where to access them in the HHT and how to monitor them Data Files These files contain information used in your ladder program Data table files include Data File 0 Output Data File 1 Input Data File 2 Status Data File 3 Binary or Bit Data File 4 Timer Data File 5 Counter Data File 6 Control Data File 7 Integer Data File 8 Reserved file D...

Page 182: ...LC 500 processors However the form of protection can only be changed during offline programming Fixed and SLC 5 01 processors output files are always protected and all other files are unprotected from online changes while the processor is in the Run mode SLC 5 02 processors at the time you save your program you can protect output files all files or no files from online changes while the processor ...

Page 183: ...or branch intersection when you press F3 EDT_DAT the cursor moves to the beginning of the first data file the Output data file You can then use the ADDRESS function key followed by ENTER to specify any address in the data table Monitor the counter data file by pressing F3 EDT_DAT The following display appears ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 COUNTER C5 0 CU CD DN OV UN UA STA...

Page 184: ...s of an output circuit or terminal All bits are presently reset 0 Important If the processor is in the Run mode you can only save changed data in the output file if you have a SLC 5 02 processor and your file was saved allowing this option Refer to chapter 8 ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Address 15 data 0 O0 3 0 0000 0000 O0 3 0 0 0 RUN To display the next consecutive data...

Page 185: ...00 0000 S2 6 Fault Code 0000H Desc No Error S2 3L Program Scan x10mS last 0 S2 3H Watchdog x10mS 10 S2 5 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 7 Suspend Code 0 S2 8 Suspend File 0 S2 4 Running Clock 0000 0000 0000 0000 S2 13 14 Math Register 00000000H S2 7 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 15H Communication KBaud Rat...

Page 186: ...RESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 9 S2 10 Active Node List 1 2 3 0 0 0 0 0111 1000 0000 0000 0000 0000 0000 0000 Node 0 S2 9 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 11 S2 12 I O Slot Enables 1 2 3 0 0 0 0 1111 1111 1111 1111 1111 1111 1111 1111 Slot 0 S2 11 0 1 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status F...

Page 187: ...reset The preset is currently 1000 and the accumulator is 0 F1 F2 F3 F4 F5 NEXT_PG PREV_PG ADDRESS NEXT_FL PREV_FL Timer T4 0 EN TT DN STATUS 0 0 0 PRESET 1000 ACCUM 0 STATUS 000 RUN To display the next consecutive data file the counter data file press F2 NEXT_FL Counter Data File C5 The display below shows the counter data file The cursor is on the count up enable bit CU bit 15 of counter C5 0 Th...

Page 188: ...ich currently has a decimal value of 1098 F1 F2 F3 F4 F5 NEXT_PG PREV_PG ADDRESS NEXT_FL PREV_FL Address Data N7 0 1098 N7 1 0 N7 2 2000 N7 3 5 N7 0 1098 RUN To display the next consecutive data file press F2 NEXT_FL If a data file numbered 8 or higher has been used the displays will change accordingly Otherwise the HHT wraps around to the start of the data table and displays the output data file ...

Page 189: ...value To change the counter preset or accumulator values or the status bits 1 Press EDT_DAT from either the zoom display or the online monitor display A screen similar to the one below appears Counter C5 0 CU CD DN OV UN UA STATUS 0 0 1 0 0 0 PRESET 3 ACCUM 16 STATUS 001000 RUN F1 F2 F3 F4 F5 NEXT_PG PREV_PG ADDRESS NEXT_FL PREV_FL In this display the accumulator ACCUM is 16 and the done bit DN bi...

Page 190: ...an overflow condition setting the overflow bit OV bit 12 Rung 3 in the ladder program is true The display changes as follows Counter C5 0 CU CD DN OV UN UA STATUS 0 0 1 1 0 0 PRESET 32767 ACCUM 32768 STATUS 32768 RUN F1 F2 F3 F4 F5 NEXT_PG PREV_PG ADDRESS NEXT_FL PREV_FL The accumulator is on the 32768th count shown as 32678 As the count continues to increment the accumulator shows negative number...

Page 191: ...used throughout this chapter Operation This program is used to achieve the maintained contact action of an On Off toggle switch using a momentary contact push button Press for on press again for off The first time you press the push button represented by address I 0 1 instruction B3 11 is latched energizing output O 0 0 The second time you press the push button instruction B3 12 unlatches instruct...

Page 192: ...HT is online monitoring the program in the Run mode The cursor is located on external input I 0 1 The display indicates NO FORCE RUN MODE FORCE EDT DAT SEARCH F1 F2 F3 F4 F5 XIC I1 0 0 1 NO FORCE 2 0 0 0 1 To Close an External Input Circuit To simulate the closing of the external input circuit you must force the input as follows 1 Select the force function by pressing F2 FORCE The force functions ...

Page 193: ...data file Other forces are unaffected F4 REM_ALL Affects all forced external input bit addresses and external output circuits Removes installed forces from all external input bit addresses and output circuits You must confirm your choice F5 ENABLE Toggles between enable and disable all forces both inputs and outputs You must confirm your choice The disable function is in effect when no forces are ...

Page 194: ...display Note that the output 0 LED of the controller is on To Close and Open an External Circuit To simulate closing opening closing and opening of an external circuit as by pressing and releasing a push button twice you must force the input off then on then off 1 Press F2 OFF Rungs 1 and 3 remain true ON OFF REM REM_ALL DISABLE F RUN F1 F2 F3 F4 F5 XIC I1 0 0 1 FORCE OFF 2 0 0 0 1 2 Press F1 ON R...

Page 195: ...To disable and or remove forces you can select DISABLE REM or REM ALL 4 Remove the force by pressing F3 REM NO FORCE indicates the force is removed and disabled The F no longer appears to the left of RUN The FORCED I O LED of the processor is off RUN ON OFF REM REM_ALL ENABLE F1 F2 F3 F4 F5 XIC I1 0 0 1 NO FORCE 2 0 0 0 1 5 Press ESC to exit the force function RUN MODE FORCE EDT DAT SEARCH F1 F2 F...

Page 196: ...enabled 1 Set up these initial conditions a repeat of what was done on page 13 2 F RUN MODE FORCE EDT DAT SEARCH F1 F2 F3 F4 F5 XIC I1 0 0 1 FORCE ON 2 0 0 0 1 2 Select the search function by pressing F4 SEARCH The search functions appear F RUN CUR INS CUR OPD NEW INS UP FORCE F1 F2 F3 F4 F5 XIC I1 0 0 1 FORCE ON 2 0 0 0 1 3 Press F5 FORCE XIC I1 0 0 1 FORCE ON 2 0 0 0 1 ENTER TO FIND FORCE F RUN ...

Page 197: ...ruction in rung 2 END ENTER TO FIND FORCE F RUN UP F1 F2 F3 F4 F5 XIC I1 0 0 1 FORCE ON 2 0 0 0 1 6 Press ENTER The cursor has wrapped around to rung 0 the first occurrence of a forced instruction ENTER TO FIND FORCE F RUN UP F1 F2 F3 F4 F5 XIC I1 0 0 1 FORCE ON 2 0 0 0 1 Notes The search locates all forced instructions regardless of instruction type or address The search for forced instructions c...

Page 198: ...s installs a force If the Enable function is in effect and the processor is in the Run or Test mode the force is applied The data file bit remains forced until 1 the disable function is in effect or 2 the force is removed F2 OFF Enters a 0 in the input force table for the cursored external input bit address This installs a force If the Enable function is in effect and the processor is in the Run o...

Page 199: ...E F1 F2 F3 F4 F5 OTE O0 0 0 1 FORCE ON 2 3 0 0 2 When your program has forced I O and you go offline the FORCE ON and FORCE OFF indications appear in the offline ladder diagram displays although the I O data files do not change If you subsequently remove the forces online then go offline the FORCE ON and FORCE OFF indications no longer appear in the offline ladder diagram displays Forces Carried O...

Page 200: ...EPROM and undesired CPU faults follow the installation procedure described in the controller installation manual 1747 NI001 fixed controller or 1747 NI002 modular controller Establish online communications with the processor Make sure the processor is in the Program mode Transfer the file to from the EEPROM memory module Transferring a Program to an EEPROM Memory Module 1 Establish online communic...

Page 201: ...RC and processor to memory PRC_MEM 7 To transfer the processor program to the EEPROM press F4 PRC_MEM File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 77 1 Reserved 0 2 222 Ladder 13 3 Ladder 1 F1 F2 F3 F4 F5 YES NO PRG XFER PROC TO MEMORY MODULE The prompt line asks you to verify your choice 8 Press F2 The prompt line indicates XFERRING PROC TO MEMORY MODULE momentarily then return...

Page 202: ...File Exec Files 4 Exec Files 3 Data Files 9 Data Files 3 DEFAULT FILE IN PROCESSOR F1 F2 F3 F4 F5 OFFLINE DWNLOAD CLR_PRC PRG MEM_PRC 5 Press F4 MEM_PRC Program Directory Programmer Processor Prog 1000 Prog DEFAULT File 222 File Exec Files 4 Exec Files 3 Data Files 9 Data Files 3 XFER MEMORY MODULE TO PROC F1 F2 F3 F4 F5 YES PRG NO The prompt line asks you to verify your choice 6 Press F2 YES The ...

Page 203: ... 0 2 222 Ladder 13 3 Ladder 1 F1 F2 F3 F4 F5 PASSWRD XFERMEM EDT_DAT PRG MONITOR 8 Press F3 XFERMEM File Name 222 Prog Name 1000 File Name Type Size Instr 0 System 77 1 Reserved 0 2 222 Ladder 13 3 Ladder 1 F1 F2 F3 F4 F5 MEM_PRC PRC_MEM PRG Your choices are memory module to processor RAM MEM_PRC and processor RAM to memory module PRC_MEM 9 To transfer the program from the memory module to the pro...

Page 204: ...d controller to actually run it The I O and rack configurations of the processors do not have to match however the processor and I O configuration must match the EEPROM program in order to enter the Run mode If you do a major fault will occur You cannot use a SLC 5 02 processor to burn a program configured for a SLC 5 01 processor or fixed controller A program configured for a SLC 5 01 processor o...

Page 205: ...the processor RAM follow the Transferring A Program from an EEPROM procedures earlier in this chapter Program loading is done with a commercially available PROM programmer and a 1747 M5 adapter 1747 M3 or 1747 M4 UVPROM either a 1747 M1 or 1747 M2 complementary EEPROM containing the program to be transferred to the 1747 M3 or 1747 M4 UVPROM or a copy of the program in an INT INTELLEC 8 MDS Hex fil...

Page 206: ...ic 5 02 Only Function Conditional Input or Output Instructions as Noted Examine if Closed XIC Conditional instruction True when bit is on 1 Examine if Open XIO Conditional instruction True when bit is off 0 One Shot Rising OSR Conditional instruction Makes rung true for one scan upon each false to true transition of conditions preceding it in the rung Output Energize OTE Output instruction True 1 ...

Page 207: ...tions go false the mode changes to program from run or test the processor loses power a fault occurs Count Up CTU Counts up for each false to true transition of conditions preceding it in the rung Produces an output when accumulated value count reaches preset value Count Down CTD Counts down for each false to true transition of conditions preceding it in the rung Produces an output when accumulate...

Page 208: ...rs data from one node to another on the DH 485 network When the instruction is enabled message transfer is pending Actual data transfer takes place at the end of the scan during the communications portion of the operating cycle Service Communications SVC When conditions preceding it in the rung are true the SVC instruction interrupts the program scan to execute the communications portion of the op...

Page 209: ... source B Less Than or Equal LEQ Instruction is true when source A source B Greater Than GRT Instruction is true when source A source B Greater Than or Equal GEQ Instruction is true when source A source B Masked Comparison for Equal MEQ Compares 16 bit data of a source address to 16 bit data at a reference address through a mask If the values match the instruction is true Limit Test LIM True false...

Page 210: ...ister Negate NEG When rung conditions are true the NEG instruction subtracts the source from zero and stores the result in the destination Clear CLR When rung conditions are true the CLR instruction clears the destination to zero Convert to BCD TOD When rung conditions are true the TOD instruction converts the source value to BCD and stores it in the math register or the destination file of the SL...

Page 211: ...es A and B of the OR instruction are ORed bit by bit and stored in the destination Exclusive Or XOR When rung conditions are true sources A and B of the XOR instruction are Exclusive ORed bit by bit and stored in the destination Not NOT When rung conditions are true the source of the NOT instruction is inverted 0 1 1 0 bit by bit and stored in the destination File Copy and File Fill Instructions C...

Page 212: ...he first to be unloaded Last In First Out LIFO Load LFL Unload LFU LFL LFU The LFL instruction loads a word into an LIFO stack on successive false to true transitions The LFU unloads a word from the stack on successive false to true transitions The last word loaded is the first to be unloaded Sequencer Instructions Chapter 24 Instruction Name and Mnemonic 5 02 Only Function Output Instructions Seq...

Page 213: ...he main program file or the previous subroutine file Master Control Reset MCR Output instruction Used in pairs to inhibit enable a zone within a ladder program Temporary End TND Output instruction When rung conditions are true the TND instruction stops the program scan updates I O and communications then resumes scanning at rung 0 of the main program file Suspend SUS Output instruction used for tr...

Page 214: ...are Root 20 20 STD STI Disable 25 10 STE STI Enable 25 10 STS STI Start Immediately 25 10 SUB Subtract 20 4 SUS Suspend 25 9 SVC Service Communications 18 14 TND Temporary End 25 8 TOD Convert to BCD 20 12 TOF Timer Off Delay 17 4 TON Timer On Delay 17 3 XIC Examine if Closed 16 2 XIO Examine if Open 16 3 XOR Exclusive Or 21 7 Instruction Mnemonic and Name ADD Add 20 3 AND And 21 5 BSL Bit Shift L...

Page 215: ...d on logical continuity of ladder rungs You can address a bit as many times as your program requires The following data files use bit instructions output and input data files The instructions represent external outputs and inputs the status data file the bit data file Use these instructions for the internal relay logic of your program timer counter and control data files The instructions use vario...

Page 216: ...having an input data file address When an external input device completes its circuit an on state is indicated at the input terminal wired to the device This status of the terminal is reflected in the input data file at a particular addressed bit With the terminal on the processor finds this bit set 1 during an I O scan causing the XIC instruction to be true When the input device no longer complet...

Page 217: ...file address When an external input device does not complete its circuit an Off state is indicated at the input terminal wired to the device This status of the terminal is reflected in the input data file at a particular addressed bit With the terminal off the processor finds this bit in the reset condition 0 during an I O scan causing the XIO instruction to be true When the input device completes...

Page 218: ...ve OTE instructions are reset when You enter or return to the Run or Test mode or power is restored A CPU fault occurs The OTE is programmed within an inactive or false MCR zone Important A bit that is set within a subroutine using an OTE instruction remains set until the subroutine is scanned again Avoid duplicate OTE addresses within the same program file When you want two or more different cond...

Page 219: ...0 1 0 State Condition Previous State Instruction OTL OTU These are retentive output instructions that can be used in a pair for the data table bit they control Possible logic states are indicated in the table above OTL and OTU instructions can also be used to initialize data values at the bit level When you assign an address to the OTL instruction that corresponds to the address of an external out...

Page 220: ...es to control the bit in memory The latched output device is energized even though the rung conditions controlling the output latch instruction may have gone false ATTENTION Physical outputs are turned off under processor fault conditions However when error conditions are fixed the controller will resume operation using the data table value stored at the instruction address Your program can examin...

Page 221: ...tput instructions on the rung are executed for only one program scan even if the rung goes true and remains true Instruction Parameters Use a bit address from either the bit or integer data file The addressed bit is set 1 as long as rung conditions preceding the OSR instruction are true the bit is reset 0 when rung conditions preceding the OSR instruction are false The address assigned to the OSR ...

Page 222: ...ansition of the input condition of the rung Using the OSR instruction in output branching such as in this example is permitted when using the SLC 5 02 processor In this case when I 1 0 is on output O 3 0 will be on for one scan only if B3 1 in not on and output O 3 1 will be on for one scan only if B3 2 is on Fixed SLC 5 01 SLC 5 02 Processors TOD TO BCD Source T4 0 ACC Dest S 13 I 1 0 0 OSR B3 0 ...

Page 223: ...n the rung goes false See page 17 5 Count Up CTU The count increments at each false true transition of the rung See page 17 7 Count Down CTD The count decrements at each false true transition of the rung See page 17 7 High Speed Counter HSC A special CTU counter for use with fixed controllers having 24 VDC inputs See page 17 9 Counter or Timer Reset RES This instruction resets the accumulated valu...

Page 224: ...ord EN TT DN Internal Use 15 14 13 Preset Value Accumulated Value EN Timer Enable Bit TT Timer Timing Bit DN Timer Done Bit Timebase The timebase is a measure of the interval counted by a timer Selectable as 0 01 sec or 1 0 sec for SLC 5 02 processors Fixed at 0 01 sec for fixed controllers and SLC 5 01 processors Accuracy Timing accuracy is minus 0 01 to plus 0 seconds with a program scan of up t...

Page 225: ...he accumulated value is equal to the preset value It is reset when rung conditions become false The timer timing bit TT is set when rung conditions are true and the accumulated value is less than the preset value It is reset when the rung conditions go false or when the done bit is set The enable bit EN is set when rung conditions are true it is reset when rung conditions become false Effects of p...

Page 226: ...when rung conditions go true regardless of whether the timer has timed out Status Bits The done bit DN is reset when the accumulated value is equal to the preset value It is set when rung conditions become true The timing bit TT is set when rung conditions are false and the accumulated value is less than the preset value It is reset when the rung conditions go true or when the done bit is reset Th...

Page 227: ... EN TT DN 0 0 0 EDT_DAT online monitor mode Operation The RTO instruction begins to count timebase intervals when rung conditions become true As long as rung conditions remain true the timer increments its accumulated value ACC each scan until it reaches the preset value PRE The accumulated value is retained when any of the following occurs Rung conditions become false You change processor operati...

Page 228: ...ction When the RES instruction having the same address as the RTO is enabled the accumulated value and the control bits are reset Effects of processor mode changes When the processor changes from the Run or Test mode to the Program or Fault mode or user power is lost while the timer is timing but not yet at the preset value the following occurs The timer enable and timing bits remain set The accum...

Page 229: ...ntive Count up and count down instructions count false to true rung transitions These rung transitions could be caused by events occurring in the program such as parts traveling past a detector or actuating a limit switch Each count is retained when the rung conditions again become false The count is retained until an RES instruction having the same address as the counter instruction is enabled Ea...

Page 230: ...he accumulated value becomes equal to the preset value the counter done DN bit is set and remains set if the accumulator exceeds the preset Bit 15 of the counter control word is the count up enable CU bit It is set when rung conditions of the CTU instruction are true The bit is reset when either rung conditions go false or an RES instruction having the same address as the CTU instruction is enable...

Page 231: ...t UN is set You can reset it by energizing the appropriate RES instruction You can also reset the underflow bit by incrementing the count greater than or equal to 32 768 with a CTU instruction having the same address as the CTD instruction When the UN bit is set the accumulated value wraps around to 32 767 and continues counting down from there Fixed Controllers Only High Speed Counter HSC Output ...

Page 232: ...ne bit C5 0 DN will be set the accumulator will be cleared and the preset value C5 0 PRE will be loaded into the HSC in preparation for the next high speed transition at input I 0 0 The ladder program polls the done bit C5 0 DN to determine the state of the HSC Once the done bit has been detected as set the ladder program should clear bit C5 0 DN use the unlatch OTU instruction before the HSC accu...

Page 233: ...able disable state of the HSC Word 1 contains the preset value that is loaded into the HSC when the RES instruction is executed when the done bit is set or when powerup takes place The valid range is 1 32767 Word 2 contains the HSC accumulated value This word is updated each time the HSC instruction is evaluated and when the update accumulator bit is set using an OTE instruction This accumulator i...

Page 234: ...SBR SUBROUTINE RET RETURN C5 0 DN JSR JUMP TO SUBROUTINE SBR file number 3 JSR JUMP TO SUBROUTINE SBR file number 3 C5 0 DN C5 0 DN U C5 0 DN 0 1 20 21 6 16 31 Program File 3 Execute HSC Logic Program File 2 Poll for DN Bit in Main Program File Rung Rung Unlatch DN Bit HSC Application Logic ...

Page 235: ...ount down instruction having the same address as the RES instruction With timers the RES instruction resets the accumulated value done bit timing bit and enable bit With counters the RES instruction resets the accumulated value overflow or underflow bit done bit and enable bits If the counter rung is enabled the CU or CD bit will be reset as long as the RES instruction is enabled If the counter pr...

Page 236: ...ns apply to I O event driven interrupts discussed in chapter 31 Understanding I O Interrupts SLC 5 02 processor only All application examples shown are in the HHT zoom display SLC 5 02 Processors Only Message Read Write MSG Output Instruction MSG EN DN ER MSG READ WRITE MESSAGE Read write WRITE Target Device 500CPU Control Block N7 0 Control Block Length 7 F1 F2 F3 F4 F5 ZOOM on MSG MSG 2 0 0 0 1 ...

Page 237: ...es enabled and waiting Waiting messages are serviced one at a time in sequential order first in first out Related Status File Bits Two status bit files are related to the MSG instruction Bit S 2 6 DH 485 Message Reply Pending Read only This bit becomes set when another node on the DH 485 network has supplied the information or performed the action that you have requested in the MSG instruction of ...

Page 238: ...RITE MSG TYPE READ LD LS ADDR TARGET 500 CPU TARG NODE 0 CTRL BLK TARG OS AD CTRL BLK 7 WORDS MSG LEN 0 SELECT MESSAGE TYPE READ WRITE Choices are READ WRITE Read indicates that the local processor processor in which the instruction is located is receiving data write indicates that it is sending data After you make a selection F2 or F4 the display changes to the following 2 Select Target Device F1...

Page 239: ...an address the display changes to the following 4 Local Destination Source File Address F1 F2 F3 F4 F5 ZOOM on MSG MSG 2 0 0 0 NAME MESSAGE READ WRITE MSG TYPE WRITE LD LS ADDR TARGET 500 CPU TARG NODE 0 CTRL BLK N7 0 TARG OS AD CTRL BLK 7 WORDS MSG LEN 0 LOCAL SOURCE FILE ADDR LD Local Destination LS Local Source If this is a read message instruction this parameter is the local destination file a...

Page 240: ... local processor is reading or writing to After you enter a node number the display changes to the following 6 Target File Address Offset F1 F2 F3 F4 F5 ZOOM on MSG MSG 2 0 0 0 NAME MESSAGE READ WRITE MSG TYPE WRITE LD LS ADDR N7 40 TARGET 500 CPU TARG NODE 5 CTRL BLK N7 0 TARG OS AD CTRL BLK 7 WORDS MSG LEN 0 TARGET FILE ADDR OS Offset AD Address If the target device is a 500 CPU this is the sour...

Page 241: ...Examples A MSG read instruction specifying a target file type C counter a destination file type N integer and a length value of 1 will transfer 1 word of information A MSG read instruction specifying a target file type N a destination file type C and a length value of 1 will transfer 3 words The message length is the final parameter After you enter it the display changes to the following F1 F2 F3 ...

Page 242: ...nditions go true and the instruction is being executed It remains set until message transmission is completed and the rung goes false Bit 14 ST Start bit This bit is set when the processor receives acknowledgement from the target device The ST bit is reset when the DN bit or ER bit is set Bit 13 DN Done bit This bit is set when the message is transmitted successfully and is replied to by the targe...

Page 243: ...5 ZOOM on MSG MSG 2 0 0 0 2 NAME MESSAGE READ WRITE MSG TYPE WRITE LD LS ADDR N7 40 TARGET 500 CPU TARG NODE 5 CTRL BLK N7 0 TARG OS AD N7 6 EN ST DN ER NR TO MSG LEN 2 0 0 0 0 0 0 EDT_DAT Successful MSG Instruction Timing Diagram Rung goes True Target node receives packet Target node processes packet successfully and returns data read or writes data success EN EW ST 1 0 1 0 1 0 DN ER 1 0 1 0 Alle...

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Page 255: ...reater Than GRT Greater Than or Equal GEQ Masked Comparison for Equal MEQ Instruction for use with SLC 5 02 processors only Limit LIM The following general information applies to comparison instructions Indexed Word Addresses With SLC 5 02 processors you have the option of using indexed word addresses for instruction parameters specifying word addresses Indexed addressing is discussed in chapter 4...

Page 256: ...isplay HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode When the values at source A and source B are equal the instruction is logically true If these values are not equal the instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed integers are stored in two s complement...

Page 257: ...HT Zoom Display Ladder Diagrams and APS Displays online monitor mode When the values at source A and source B are not equal the instruction is logically true If the two values are equal this instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed integers are stored in two s complementary f...

Page 258: ...adder Diagrams and APS Displays online monitor mode When the value at source A is less than the value at source B this instruction is logically true If the value at source A is greater than or equal to the value at source B this instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed intege...

Page 259: ...dder Diagrams and APS Displays online monitor mode When the value at source A is less than or equal to the value at source B this instruction is logically true If the value at source A is greater than the value at source B this instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed integer...

Page 260: ...y Ladder Diagrams and APS Displays online monitor mode When the value at source A is greater than the value at source B this instruction is logically true If the value at source A is less than or equal to the value at source B this instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed int...

Page 261: ...adder Diagrams and APS Displays online monitor mode When the value at source A is greater than or equal to the value at source B this instruction is logically true If the value at source A is less than the value at source B this instruction is logically false Entering Parameters You must enter a word address for source A You can enter a program constant or a word address for source B Signed intege...

Page 262: ...a at a reference address and allows portions of the data to be masked by a separate word Entering Parameters Source the address of the value you want to compare Mask a hex value or the address of the mask through which the instruction moves data Refer to appendix B for more information regarding masks and hexadecimal numbering Compare an integer value or the address of the reference If the 16 bits...

Page 263: ...or mode This input instruction tests for values within or outside a specified range depending on how you set the limits Entering Parameters Low Limit Test and High Limit values you program can be word addresses or decimal values restricted to the following combinations If the Test parameter is a program constant both the Low Limit and High Limit parameters must be word addresses If the Test parame...

Page 264: ...alue is Instruction is false when Test value is 5 8 5 thru 8 32 768 thru 4 and 9 thru 32 767 False True False 32 768 Low Limit High Limit 32 767 If the Low Limit has a value greater than the High Limit the instruction is false when the Test value is between the limits If the Test value is equal to either limit or outside the limits the instruction is true This is illustrated in the figure below 8 ...

Page 265: ... later SLC 5 02 processors 32 bit addition and subtraction All application examples shown are in the HHT zoom display The following general information applies to math instructions Entering Parameters Source address es of the value s on which the mathematical logical or move operation is to be performed can be word addresses or program constants An instruction that has two source operands will not...

Page 266: ...ow or a division by 0 will occur you can avoid a major error from occurring by resetting S 5 0 with an unlatch OTU instruction in your program The rung containing the OTU instruction must be between the overflow point and the END statement or TND instruction or REF instruction Math Register S 14 and S 13 Status word S 13 contains the least significant word of the 32 bit values of MUL and DDV instr...

Page 267: ...d in the destination Using Arithmetic Status Bits C set if carry is generated otherwise reset V set if overflow is detected at destination otherwise reset On overflow the minor error flag S 5 0 is also set The value 32 768 or 32 767 is placed in the destination Exception If you are using a Series C or later SLC 5 02 processor and have the Math Overflow Selection Bit S 2 14 set then the unsigned tr...

Page 268: ...at source A and then stored in the destination Using Arithmetic Status Bits C set if borrow is generated otherwise reset V set if underflow otherwise reset On underflow the minor error flag S 5 0 is also set and the value 32 768 or 32 767 will be placed in the destination Exception If you are using a Series C or later SLC 5 02 processor and have the Math Overflow Selection Bit S 2 14 set then the ...

Page 269: ... This provides the same operation as that of the Series B SLC 5 02 processor When S 2 14 is reset and the result of an ADD SUB MUL or DIV instruction cannot be represented in the destination address underflow or overflow The overflow bit S 0 1 is set The overflow trap bit S 5 0 is set The destination address contains 32767 if the result is positive or 32768 if the result is negative Note that the ...

Page 270: ...B3 3 B3 2 0000 0000 0000 0011 0001 1001 0100 0000 0101 0101 1010 1000 0000 0000 0000 0011 0110 1110 1110 1000 0003 1940 55A8 0003 6EE8 203 072 21 928 225 000 Addend Addend Sum If a carry is generated S 0 0 set 1 is added to B3 3 If B3 1 is negative B3 31 set 1 is subtracted from B3 3 Overflow trap bit S 5 0 is unlatched to prevent a major error from occurring at the end of the scan Application Not...

Page 271: ...n Using Arithmetic Status Bits C always reset V set if overflow is detected at the destination otherwise reset On overflow the minor error flag is also set The value 32 767 or 32 768 is placed in the destination Exception If you are using a Series C or later SLC 5 02 processor and have the Math Overflow Selection Bit S 2 14 set then the unsigned truncated overflow remains in the destination Z set ...

Page 272: ...icant word of the math register The remainder is placed in the least significant word of the math register Using Arithmetic Status Bits C always reset V set if division by zero or overflow otherwise reset On overflow the minor error flag is also set The value 32 767 is placed in the destination Exception If you are using a Series C or later SLC 5 02 processor and have the Math Overflow Selection B...

Page 273: ...t word of the math register The remainder is placed in the least significant word of the math register Using Arithmetic Status Bits C always reset V set if division by zero or if the result is greater than 32 767 or less than 32 768 otherwise reset On overflow the minor error flag is also set The value 32 767 is placed in the destination Z set if the result is zero otherwise reset S set if the res...

Page 274: ...The destination contains the 2 s complement of the source Using Arithmetic Status Bits C cleared if 0 or overflow otherwise set V set if overflow otherwise reset On overflow the minor error flag is also set The value 32 767 is placed in the destination Exception If you are using a Series C or later SLC 5 02 processor and have the Math Overflow Selection Bit S 2 14 set then the unsigned truncated o...

Page 275: ...R CLR 2 3 0 0 2 NAME CLEAR DEST N7 1 0 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The destination value is cleared to zero Using Arithmetic Status Bits C always reset V always reset Z always set S always reset Math Register Unchanged Clear CLR Allen Bradley Parts ...

Page 276: ...ion instruction when you want to display or transfer BCD values external to the processor Entering Parameters Source the address of the value to be converted to BCD If the integer value you enter is negative the sign is ignored and the conversion occurs as if the number were positive The absolute value of the number is used for conversion Destination the address of the location to hold the result ...

Page 277: ...ult of the conversion This result is valid at overflow Example 1 SLC 5 02 Processors Only The integer value 9760 stored at N7 3 is converted to BCD and the BCD equivalent is stored in N10 0 The maximum BCD value possible is 9999 Destination is displayed as 26784 decimal equivalent to 9760 BCD 9 7 6 0 9 7 6 0 N7 3 Decimal 0010 0110 0010 0000 N10 0 4 digit BCD 1001 0111 0110 0000 F1 F2 F3 F4 F5 ZOOM...

Page 278: ...S 5 0 also being set Your ladder program can unlatch S 5 0 before the end of the scan to avoid major error 0020 as done in this example TOD TO BCD Source N7 3 32760 Dest S 13 00032760 U S 5 0 S 0 1 APS displays S 13 and S 14 in BCD MOV MOVE Source S 13 10080 Dest O 2 0 10080 MVM MASKED MOVE Source S 14 3 Mask 000F Dest O 3 0 3 0 0 0 3 2 7 6 0 3 2 7 6 0 0 0 15 15 N7 3 Decimal S 13 S 14 5 digit BCD ...

Page 279: ...r mode BCD BCD Fixed SLC 5 01 Processors SLC 5 02 Processors SLC 5 02 Processors Use this instruction when you want to convert BCD values to integer or decimal values Entering Parameters Source word address of the value in BCD to be converted to integer decimal With SLC 5 02 processors the source parameter can be a word address in any data file or it can be the math register S 13 With fixed and SL...

Page 280: ... you always provide ladder logic filtering of all BCD input devices prior to executing the FRD instruction The slightest difference in point to point input filter delay can cause the FRD instruction to fault due to conversion of a non BCD digit An example of filtering is shown below The above rungs cause the processor to verify that the value at slot 2 I 2 remains the same for two consecutive scan...

Page 281: ...CD S 14 S 13 0000 0000 0000 0011 0010 0111 0110 0000 N10 0 Decimal 0111 1111 1111 1000 F1 F2 F3 F4 F5 ZOOM on FRD FRD 2 3 0 0 2 NAME FROM BCD DEST N10 0 32760 SOURCE S 13 10080 EDT_DAT Source is displayed as 10080 decimal equivalent to 32760 BCD You should convert BCD values to integer before you manipulate them in your ladder program If you do not convert the values the processor manipulates them...

Page 282: ...heel switch for example is moved from word N7 2 into the math register Status word S 14 is then cleared to make certain that unwanted data is not present when the FRD instruction is executed CLR CLEAR Dest S 14 0 FRD FROM BCD Source S 13 00001234 Dest N7 0 1234 APS displays S 13 and S 14 in BCD MOV MOVE Source N7 2 4660 Dest S 13 4660 I 1 0 0 0001 0010 0011 0100 0000 0100 1101 0010 ...

Page 283: ...ns such as rotary switches keypads bank switching etc Source Destination Bit 15 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x 0 1...

Page 284: ...LC 5 02 Processors Only Square Root SQR Output Instruction SQR SQR SQUARE ROOT Source N7 0 21583 Dest N7 1 147 F1 F2 F3 F4 F5 ZOOM on SQR SQR 2 3 0 0 2 NAME SQUARE ROOT SOURCE N7 0 21583 DEST N7 1 147 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode When this instruction is evaluated as true the square root of the absolute value of the source is calc...

Page 285: ... 5 02 Processors Only SCL SCALE Source N7 0 9760 Rate 10000 25000 Offset 127 Dest N7 1 24527 Scale Data SCL Output Instruction SCL F1 F2 F3 F4 F5 ZOOM on SCL SCL 2 3 0 0 2 NAME SCALE SOURCE N7 0 9760 RATE 25000 25000 OFFSET 127 127 DEST N7 1 24527 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode Scale Data SCL Allen Bradley Parts ...

Page 286: ... major error will be declared Entering Parameters The range of values for the following parameters is 32 768 to 32 767 Source This can be a program constant decimal or a word address Rate This is the positive or negative value you enter divided by 10 000 It can be a program constant decimal or a word address The rate parameter is limited to a range of 3 2768 to 3 2767 Offset This can be a program ...

Page 287: ...25 32 77 in the SCL instruction 1 Place the degrees C value 25 in this case in the source parameter 2 The multiplier is 1 8 so place a program constant value of 18000 in the rate parameter 3 32 must be added Place this program constant in the offset parameter When the SCL instruction goes true the result will appear in the word address entered in the destination parameter SCL SCALE Source N7 0 25 ...

Page 288: ... will not accept program constants in both operands Destination This is the address of the result of the move or logical operation It must be a word address Indexed Word Addresses With SLC 5 02 processors you have the option of using indexed word addresses for instruction parameters specifying word addresses Indexed addressing is discussed in chapter 4 Using Arithmetic Status Bits After an instruc...

Page 289: ...t the math register Move MOV Output Instruction MOV MOV MOVE Source N7 0 9760 Dest N7 1 9760 F1 F2 F3 F4 F5 ZOOM on MOV MOV 2 3 0 0 2 NAME MOVE SOURCE N7 0 9760 DEST N7 1 9760 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The processor moves a copy of the source value to the destination location Entering Parameters Source a program constant or the...

Page 290: ...P instruction is discussed in chapter 22 Masked Move MVM Output Instruction MVM MVM MASKED MOVE Source B3 6 1111010011110101 Mask 00E0 Dest B3 7 0000000011100000 F1 F2 F3 F4 F5 ZOOM on MVM MVM 2 3 0 0 2 NAME MASKED MOVE SOURCE B3 6 1111 0100 1111 0101 MASK 00E0 00E0 DEST B3 7 0000 0000 1110 0000 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The ma...

Page 291: ...nstruction is true data at the source address passes through the mask to the destination address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 2 before move 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 source B3 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Mask F0F0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 B3 2 after move MVM MASKED MOVE Source B3 0 0101010101010101 Mask F0F0 Dest B3 2 1111111111111111 unaltered unaltered Mask do not pass d...

Page 292: ... 0100 DEST B3 8 0000 0001 0000 0100 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The value at source A is ANDed bit by bit with the value at source B and then stored in the destination Truth Table R A AND B A B R 0 0 0 1 0 0 0 1 0 1 1 1 A Source A bit B Source B bit R Destination bit Using Arithmetic Status Bits C always reset V always reset Z se...

Page 293: ... 2 0011 0101 1010 0101 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The value at source A is ORed bit by bit with the value at source B and then stored in the destination Truth Table R A OR B A B R 0 0 0 1 0 1 0 1 1 1 1 1 A Source A bit B Source B bit R Destination bit Using Arithmetic Status Bits C always reset V always reset Z set if the result...

Page 294: ...EST B3 2 0011 0101 1000 0100 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The value at source A is Exclusive ORed bit by bit with the value at source B and then stored in the destination Truth Table R A XOR B A B R 0 0 0 1 0 1 0 1 1 1 1 0 A Source A bit B Source B bit R Destination bit Using Arithmetic Status Bits C always reset V always reset Z ...

Page 295: ...and APS Displays NOT NOT Source B3 0 1010011011101100 Dest B3 1 0101100100010011 online monitor mode The source value is NOTed inverted bit by bit and then stored in the destination Truth Table R NOT A A R 0 1 1 0 A Source bit R Destination bit Using Arithmetic Status Bits C always reset V always reset Z set if the result is zero otherwise reset S set if the result is negative most significant bit...

Page 296: ...r to a Move MOV instruction but they enable you to move more than one word at a time This is facilitated by the use of the file indicator in the parameter addresses The symbol indicates a file or group of words not just one word The following general information applies to file copy and file fill instructions Effect on Index Register in SLC 5 02 Processors After a COP or FLL instruction is execute...

Page 297: ...ss The COP instruction moves data from one file to another as illustrated below Source File Destination File Entering Parameters Source The address of the first word of the file you want to copy You must use the file indicator in the address Destination The address of the first word of the file where the copy of the source file will be stored You must use the file indicator in the address Length T...

Page 298: ...ords corresponding to the status words of your destination file contains zeros Be sure that you accurately specify the starting address and length of the data block you are copying The instruction will not read or write over a file boundary such as between files N16 and N17 at the destination Note that an error is declared if a write is attempted over a file boundary You can perform file shifts by...

Page 299: ...must use the file indicator in the address Length The number of elements in the file you want filled If the destination file type is 3 words per element you can specify a maximum length of 42 If the destination file type is 1 word per element you can specify a maximum length of 128 All elements are filled from the source value typically a program constant into the specified destination file each s...

Page 300: ...e a method of loading words into a file and unloading them in the same order as they were loaded First word in is the first word out LIFO instructions provide a method of loading words into a file and unloading them in the opposite order as they were loaded Last word in is the first word out FIFO and LIFO instruction applications include assembly transfer lines inventory control and system diagnos...

Page 301: ...T LEFT FILE B3 1 LENGTH 50 CONTROL R6 0 BIT ADDR I1 1 0 0 EN DN ER UL 0 0 0 0 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode F1 F2 F3 F4 F5 ZOOM on BSR BSR 2 3 0 0 1 NAME BIT SHIFT RIGHT FILE B3 1 LENGTH 50 CONTROL R6 0 BIT ADDR I1 1 0 0 EN DN ER UL 0 0 0 0 EDT_DAT EN DN BSR BIT SHIFT RIGHT File B3 1 Control R6 0 Bit Address I 1 0 0 Length 50 Bit S...

Page 302: ...t when set indicates the instruction detected an error such as entering a negative number for the length or position Avoid using the unload bit when this bit is set UL bit 10 The unload bit stores the status of the bit exited from the array each time the instruction is enabled When the register shifts and input conditions go false the enable done and error bits are reset Bit Address This is the ad...

Page 303: ...1 60 44 DO NOT USE 58 bit array B3 1 Bit Address source I 22 12 Unload Bit R6 53 10 Data block is shifted one bit at a time from bit 16 to bit 73 Operation Bit Shift Right When the rung goes from false to true the enable bit EN bit 15 is set and the data block is shifted to the right to a lower bit number one bit position The specified bit at the Bit Address source is shifted into the last bit pos...

Page 304: ...OURCE N7 10 LENGTH 34 FIFO N7 12 POSITION 0 CONTROL R6 0 EN EU DN EM 0 0 0 0 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode F1 F2 F3 F4 F5 ZOOM on FFU FFU 2 4 0 0 2 NAME FIFO UNLOAD FIFO N7 12 LENGTH 34 DEST N7 11 POSITION 0 CONTROL R6 0 EN EU DN EM 0 0 0 0 EDT_DAT FFL and FFU instructions are used in pairs The FFL instruction loads words into a us...

Page 305: ...stack length and the position value are stored in this element The same address is programmed for the FFL and FFU instructions Do not use the control file address for any other instruction The 3 word control element EN EU DN EM 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Length Position Status Bits EN bit 15 FFL instruction enable bit The bit is set on a false to true transition of the FFL run...

Page 306: ...se to true transition of the rung until the stack is filled 34 elements The done bit DN is then set which inhibits further loading FFU instruction operation When rung conditions change from false to true the FFU enable bit EU is set This unloads the contents of the element at stack position 0 into the Destination N7 11 All data in the stack is shifted one element toward position zero and the highe...

Page 307: ...Display Ladder Diagrams and APS Displays online monitor mode F1 F2 F3 F4 F5 ZOOM on LFU LFU 2 4 0 0 2 NAME LIFO UNLOAD LIFO N7 12 LENGTH 34 DEST N7 11 POSITION 0 CONTROL R6 0 EN EU DN EM 0 0 0 0 EDT_DAT monitor mode These instructions are the same as the FIFO load and unload instructions except that the last data loaded is the first data to be unloaded FIFO and LIFO instruction applications includ...

Page 308: ...e position value then increments The LFL instruction loads an element at each false to true transition of the rung until the stack is filled 34 elements The done bit DN is then set which inhibits further loading LFU instruction operation When rung conditions change from false to true the LFU enable bit EU is set This unloads data from the last element loaded into the stack at the position value mi...

Page 309: ...operating conditions or for diagnostic purposes Instruction for use with the SLC 5 02 processor only Sequencer Load SQL It loads 16 bit data into a file at each step of sequencer operation All application examples shown are in the HHT zoom display The following general information applies to sequencer instructions Applications Requiring More than 16 Bits When your application requires more than 16...

Page 310: ...Length 4 Position 0 FD EN DN F1 F2 F3 F4 F5 ZOOM on SQO SQO 2 3 0 0 2 NAME SEQUENCER OUTPUT FILE B10 1 CONTROL R6 20 MASK 0F0F LENGTH 4 DEST O0 2 0 POSITION 0 EN DN ER 0 0 0 EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode F1 F2 F3 F4 F5 ZOOM on SQC SQC 2 3 0 0 2 NAME SEQUENCER COMPARE FILE B10 11 CONTROL R6 21 MASK FFF0 LENGTH 4 SOURCE I1 1 0 POSITI...

Page 311: ... its sequencer file For input data file addresses the HHT requires that you enter the slot and word number For example I 3 0 Destination SQO This is the address of the output word or file to which the instruction moves data from its sequencer file For output data file addresses the HHT requires that you enter the slot and word number For example O 4 0 Important You can address the mask source or d...

Page 312: ...er file starting at position 1 Position 0 is the startup position The instruction resets wraps to position 1 at each cycle completion The address assigned for a sequencer file is step zero Sequencer instructions use length 1 words of data table for each file referenced in the instruction This applies to the source mask and or destination if addressed as files A length value that points past the en...

Page 313: ...ata by resetting bits in the mask word The bits mask data when reset pass data when set Unless you set mask bits the instruction will not change the value in the destination word The mask can be fixed by entering a hex code The mask can be a variable by entering an element address or a file address for changing the mask with each step The following figure indicates how the SQO instruction function...

Page 314: ...next step word in the sequencer file Data stored there is transferred through a mask and compared against the source data for equality If the source data equals the reference data the FD bit is set in the SQC s control file or word R6 x FD Current data is compared against the source every scan that the rung evaluates as true Applications of the SQC instruction include machine diagnostics The follo...

Page 315: ... file where the source data is loaded into You must use the file indicator for this address Source This can be a word address file address or a program constant 32768 to 32767 indicating the value or location whose contents are loaded into the sequencer file For input addresses the HHT requires that you enter the slot and word number For example I 3 0 If the source is a file address its file lengt...

Page 316: ...d file and also of the source if the source is a file address starting at position 1 Position 0 is the startup position The instruction automatically resets wraps to position 1 at each cycle completion The position address assigned for a sequencer file is step zero Sequencer instructions use length plus 1 word of data for each file referenced in the instruction This applies to the source if addres...

Page 317: ...to the next position in the sequencer file and loads the contents of source I 1 0 into this location The SQL instruction continues to load the current data into this location each scan that the rung remains true When the rung goes false the enable bit EN is reset The instruction loads data into a new file element at each false to true transition of the rung When step 4 is completed the done bit DN...

Page 318: ...med interrupts and I O Event Driven interrupts discussed in chapters 30 and 31 Interrupt Subroutine INT The following general information applies to control instructions Control instructions allow you to change the order that the processor scans solves your ladder diagram rungs Normally the processor solves from left to right on each rung and from top to bottom of the ladder diagram rung 0 to the ...

Page 319: ...in the same program file When rungs of logic are jumped over or skipped the processor does not scan evaluate them meaning that outputs timers etc are left in their last state The outputs are not de energized turned off Important Be careful when using the JMP instruction to move backward or loop through your program If you loop too many times you may cause the watchdog timer to time out and fault t...

Page 320: ...tion has no control bits It is always evaluated as true or logic 1 You can program multiple jumps to the same label by assigning the same label number to multiple JMP instructions but assigning the same label number to two or more labels causes a compiler error Important Do not jump JMP into an MCR zone Instructions that are programmed within the MCR zone starting at the LBL instruction and ending...

Page 321: ...o the subroutine JSR rung false the SBR rungs are not scanned or evaluated meaning outputs timers etc are left in their last state if an OTE is on it stays on They are not de energized Your main program should account for this and turn off reset de energize output instructions as required You must program each subroutine in its own program file by assigning a unique file number 3 255 Nesting Subro...

Page 322: ...utines are called subroutine stack overflow or if more returns are executed than there are call levels subroutine stack underflow Also do not execute a JSR to a subroutine that is already active in the subroutine stack Update critical I O in subroutines using immediate input IIM and or immediate output IOM instructions especially if your application calls for nested or relatively long subroutines ...

Page 323: ...interrupt subroutine INT label The target subroutine is identified by the file number that you entered in the JSR instruction This instruction has no control bits It is always evaluated as true The instruction must be programmed as the first instruction of the first rung of a subroutine Return from Subroutine RET Output Instruction RET RET RETURN F1 F2 F3 F4 F5 ZOOM on RET RET 2 3 0 0 2 NAME RETUR...

Page 324: ...t routine chapter 29 Master Control Reset MCR Output Instruction MCR MCR F1 F2 F3 F4 F5 ZOOM on MCR MCR 2 3 0 0 2 NAME MASTER CONTROL RESET EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode The master control reset instruction is an output instruction used in pairs It lets the processor enable or inhibit a zone of a ladder program according to your ap...

Page 325: ...ND TND F1 F2 F3 F4 F5 ZOOM on TND TND 2 3 0 0 2 NAME TEMPORARY END EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode This instruction when its rung is true stops the processor from scanning the rest of the program file updates the I O services communications and resumes scanning at rung 0 of the main program file 2 If this instruction s rung is false ...

Page 326: ...end Idle mode The suspend ID is placed in word 7 S 7 of the status file The suspend file program or subroutine number identifying where the executed SUS instruction resides is placed in word 8 S 8 of the status file All outputs are de energized This instruction can be used to trap and identify specific conditions for program debugging and system troubleshooting Entering Parameters SUSPEND ID an in...

Page 327: ...Zoom Display Ladder Diagrams and APS Displays F1 F2 F3 F4 F5 ZOOM on STD STD 2 6 0 0 1 NAME SELECTABLE TIMED DISABLE EDT_DAT F1 F2 F3 F4 F5 ZOOM on STE STE 2 3 0 0 2 NAME SELECTABLE TIMED ENABLE EDT_DAT F1 F2 F3 F4 F5 ZOOM on STS STS 2 9 0 0 1 NAME SELECTABLE TIMED START FILE 2 2 TIME 30 30 EDT_DAT online monitor mode The Selectable Timed Interrupt function allows you to interrupt the scan of the ...

Page 328: ... are the STI file number and the STI setpoint SLC 5 02 Processors Only Interrupt Subroutine INT Input Instruction INT F1 F2 F3 F4 F5 ZOOM on INT INT 2 3 0 0 1 NAME I O INTERRUPT EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode INT INTERRUPT SUBROUTINE This instruction serves as a label or identifier of a program file as an interrupt subroutine INT la...

Page 329: ...ins the PID instruction All application examples shown are in the HHT zoom display SLC 5 02 Processors Only It is an output instruction that controls physical properties such as temperature pressure liquid level or flow rate of process loops Proportional Integral Derivative PID Allen Bradley Parts ...

Page 330: ...MIN OUTPUT 0 SETPOINT 500 PROCESS 14 ENTER GAIN 255 PRG NEXT PG MANUAL HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays monitor mode F1 F2 F3 F4 F5 ZOOM on PID PID 2 2 2 3 0 0 2 NAME PROP INT DERIV MODE AUTO LOOP UPDATE 50 x10ms SET PT RANGE 100 1000 EN DN PV SP LL UL DB TF SC OL CM AM TM 0 0 0 0 0 0 0 0 0 1 0 0 1 PRG PREV PG F1 F2 F3 F4 F5 ZOOM on PID PID 1 2 2 3 0 0 2 NAME PR...

Page 331: ... time the STI subroutine is scanned The STI time interval and the PID loop update rate must be the same in order for the equation to execute properly PID closed loop control holds a process variable at a desired set point A flow rate fluid level example is shown below PID Equation FFWD or Bias Control Output Level Detector Process Variable Error Set Point Flow Rate Control Valve The PID equation c...

Page 332: ... CPT MTH in the HHT instruction set menu After you select PID the following display appears F1 F2 F3 F4 F5 ZOOM on PID PID 1 3 2 0 0 0 NAME PROP INTEGRAL DERIVATIVE CONT BLK PROCESS OUTPUT CONTROL BLOCK SIZE 23 WORDS ENTER CONTROL BLK This is the first of three data entry displays The prompt line asks you to enter Control Block then Process and then Output Control Block This is a file that stores ...

Page 333: ...SETPOINT 0 DEADBAND 0 ENTER GAIN 0 You enter the following parameters at this display Gain control block word 3 This is the Proportional gain kc ranging from 0 1 to 25 5 A rule of thumb is to set this gain to one half the value needed to cause the output to oscillate when the reset and rate terms below are set to zero Entered range 1 255 Reset control block word 4 This is the Integral gain 1 TI ra...

Page 334: ...ct only after the process variable PV enters the deadband and passes through the setpoint SP Range 0 scaled max or 0 16383 when no scaling exists The display below shows typical values entered for these parameters F1 F2 F3 F4 F5 ZOOM on PID PID 2 3 2 0 0 0 NAME PROP INTEGRAL DERIVATIVE GAIN 25 10 MIN OUT 5 RESET 10 10 M R MAX OUT 95 RATE 1 100 MIN AUTO MAN AUTO SETPOINT 500 DEADBAND 5 ENTER GAIN 2...

Page 335: ... STI interrupt subroutine and the STI routine should have a time interval STI period S 30 equal to the setting of the PID loop update parameter word 13 For example if the loop update time contains the value 10 for 100 ms then the STI time interval must also equal 10 Output limit control block word 0 bit 3 Select YES if you want to limit the output to minimum and maximum values Output YES Output Li...

Page 336: ...following display shows typical values entered for these parameters F1 F2 F3 F4 F5 ZOOM on PID PID 3 3 2 0 0 0 NAME PROP INTEGRAL DERIVATIVE LOOP UPDATE 50 X10ms SET PT MIN 100 SET PT MAX 1000 MODE TIMED OUT LIMIT YES CONTROL REVERSE ENTER LOOP UPDATE 50 NEXT PG PREV PG ACCEPT Press F5 ACCEPT to complete the entry of parameters If you must change any of the parameters you can run through the entry...

Page 337: ... any PID control block value unless you fully understand its function and related effect on your process Instruction flags are in the first word of the control block They include Time mode bit TM word 0 bit 0 This bit specifies the PID mode It is set when the TIMED mode is in effect It is cleared when the STI mode is in effect This bit can be set or cleared by instructions in your ladder program A...

Page 338: ...he instruction operates with this bit set deadband range DB word 0 bit 8 This bit is set when the process variable or error is within the deadband range Output alarm upper limit UL word 0 bit 9 This bit is set when the calculated control output CV exceeds the upper CV limit Output alarm lower limit LL word 0 bit 10 This bit is set when the calculated control output CV is less than the lower CV lim...

Page 339: ...tpoint SP 16383 then during the initial execution of the PID loop this error occurs and bit 11 of word 0 of the control block is set However during subsequent execution of the PID loop if an invalid loop setpoint is entered the PID loop continues to execute using the old setpoint and bit 11 of word 0 of the control block is set If you are using setpoint scaling then change the setpoint SP to Smin ...

Page 340: ...08 Once you have scaled your analog I O ranges to from the PID instruction you can enter the minimum and maximum engineering units that apply to your application For example if the 4 to 20mA analog input range represents 0 to 300 PSI you can enter 0 and 300 as the minimum Smin and maximum Smax parameters respectively The Process Variable Error Setpoint and Deadband will be displayed in engineering...

Page 341: ...for PV Rung 3 0 Rung 3 1 Rung 3 2 Rung 3 3 Rung 3 4 These two rungs ensure the analog input value to be scaled remains within the limits of 3277 to 16384 This is necessary to prevent out of range conversion errors in both the SCL and PID instructions The latch bits can be used elsewhere in your program to identify the particular out of range condition that occurred Under range MOV MOVE Source 1638...

Page 342: ...when you are online under the monitor function You can also change data in any processor mode The following displays appear when you press the Zoom key with the cursor on the PID instruction while monitoring online Note that in the first display you can change the mode from auto to manual and vice versa In the auto mode you can also change the gain parameter F1 F2 F3 F4 F5 ZOOM on PID PID 1 2 2 0 ...

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Page 353: ...ative that you first understand the function fully The status file S consists of the following words Word Function S 0 Arithmetic Flags Words 16 through 32 are functional for the SLC 5 02 only S 1L S 1H Processor Mode Status Control Word Function S 2L S 2H STI Bits DH 485 Communications S 16 S 17 Test Single Step Start Step On Rung File S 3L Current Scan Time S 18 S 19 Test Single Step End Step Be...

Page 354: ... value of S 0 0 is restored when execution resumes S 0 1 Overflow Bit This bit is set by the processor when the result of a mathematical operation does not fit in its destination Otherwise the bit remains cleared Whenever this bit is set the overflow trap bit S 5 0 is also set refer to S 5 0 When an STI I O Slot or Fault Routine interrupts normal execution of your program the original value of S 0...

Page 355: ... bit is set by the processor if you have installed forces in a ladder program The forces may or may not be enabled Otherwise the bit remains cleared The processor Forced I O LED flashes when forces are installed but not enabled S 1 7 Communications Active Bit Read only This bit is set by the processor when at least one other node is present on the DH 485 link Otherwise the bit remains cleared When...

Page 356: ... battery or capacitor drain noise a power problem etc You must set S 1 10 in the status file of the program in the memory module When a memory module is installed that has bit S 1 10 set a processor memory error detected at power up will cause the memory module program to be transferred to the processor and the Run mode to be entered When S 1 10 is cleared in the memory module the processor remain...

Page 357: ... the Run mode regardless of what mode was in effect before cycling power Mode before Powerdown Test Program Run Fault After Powerup Run The memory module you install in the processor must have status file bit S 1 12 set Loading will take place if the master password and or password in the processor and memory module match Loading will also take place if the processor has neither a password nor mas...

Page 358: ...t code or if the routine determines that it is not desirable to continue operation exit the fault routine with bit S 1 13 set The outputs will then be placed in a safe state and indicate the program mode 0 0001 in bits S 1 0 S 1 4 When you clear bit S 1 13 using a programming device the processor mode changes from fault to program allowing you to re enter the run or test modes You can set this bit...

Page 359: ...estore program and transfer memory module are allowed regardless of this selection A device such as the DTAM is not affected by this function S 1 15 First Pass Bit Read write You can use this bit to initialize your program as the application requires When this bit is set by the processor it indicates that the first scan of the user program is in progress following power up in the Run mode or entry...

Page 360: ... 16 through S 21 are inoperative When set the program can operate in the Single Step Test mode See descriptions of S 16 through S 21 When set your program will also require 0 375 instruction words 3 bytes per rung of additional memory Note The HHT can save a SLC 5 02 program that has this option enabled but the Test Single Step mode is not available with the HHT S 2 5 DH 485 Incoming Command Pendi...

Page 361: ...ation capability of your processor S 2 8 CIF Common Interface File Addressing Mode Applies to Series C and later SLC 5 02 processors only Read write This bit controls the mode used by the SLC 5 02 processor to address elements in the CIF file data file 9 when processing a communications request Word address mode in effect when the bit is clear 0 This is the default setting compatible with other SL...

Page 362: ...and the result of an ADD SUB MUL or DIV instruction cannot be represented in the destination address underflow or overflow the overflow bit S 0 1 is set the overflow trap bit S 5 0 is set and the destination address contains 32767 if the result is positive or 32768 if the result is negative Note that the status of bit S 2 14 has no effect on the DDV instruction Also it has no effect on the math re...

Page 363: ...ion of your selection program an unconditional OTL instruction at address S 2 15 to ensure one request command operation or program an unconditional OTU instruction at address S 2 15 to ensure multiple request command operation Alternately your program may change the state of this bit using ladder logic if your application requires dynamic selection of this function Application example Suppose you...

Page 364: ...hdog major error will be declared code 0022 Resolution of the scan time value The resolution of this value is 0 to 10 milliseconds Example The value 9 indicates that 80 90 ms has elapsed since the start of the program cycle Application example Your application requires that each and every program scan execute in the same length of time You measure the maximum and minimum scan times and find them t...

Page 365: ... more than two times faster than the clock rate of the bit This is illustrated in the example below for SLC 5 02 processors Free Running Clock Discussion applies to SLC 5 02 processors only Read write All 16 bits of this word are assessed by the processor The value of this word is zeroed upon power up in the Run mode or entry into the run or test mode It is incremented every 10 ms thereafter Appli...

Page 366: ...rror 0020 will be declared To avoid this type of major error from occurring examine the state of this bit following a math instruction ADD SUB MUL DIV DDV NEG SCL TOD or FRD take appropriate action and then clear bit S 5 0 using an OTU instruction with S 5 0 or a CLR instruction with S 5 0 S 5 1 Reserved S 5 2 Control Register Error Bit Read write The LFU LFL FFU FFL BSL BSR SQO SQC and SQL instru...

Page 367: ... be set If your fault routine did not determine that S 5 3 was set major error 0020H would be declared at the end of the first scan To avoid this problem examine S 5 3 followed by S 6 prior to returning from your fault routine If S 5 3 is set take appropriate action to remedy the fault then clear S 5 3 S 5 4 M0 M1 Referenced on Disabled Slot Bit Read write This bit is set whenever any instruction ...

Page 368: ... or S 1 12 load memory module always and run to distinguish a powerup Run mode entry from a program or test mode to Run mode entry S 5 9 Memory Module Password Mismatch Bit Read write This bit is set at Run mode entry whenever loading from the memory module is specified word 1 bits 11 or 12 and the processor user program is password protected and the memory module program does not match that passw...

Page 369: ...nd then setting bit S 1 13 SLC 5 02 processor users Interrogate the value of S 6 in your fault routine to determine the type of fault that occurred If your program was saved with the test single step enabled you can also interrogate S 20 and S 21 to pinpoint the exact rung that was being executed when the fault occurred Fault Classifications Faults are classified as Non User Non Recoverable and Re...

Page 370: ...tion User Address Error Code Hex Going to Run Errors Non User Non Recov Recov 5 02 5 01 Fixed S 6 0010 Processor does not meet proper revision level X 0011 The executable file number 2 is absent X 0012 The ladder program has a memory error X 0013 The required memory module is absent or either S 1 10 or S 1 11 is not set and the program requires it X 0014 Internal file error X 0015 Configuration fi...

Page 371: ...mode error 0021 will cause the major error halted bit S 1 13 to be cleared at the next powerup of the local rack SLC 5 02 processors and FRN 5 SLC 5 01 processors Power to the local rack does not need to be cycled to resume the Run mode Once the remote rack is re powered the CPU will restart the system X 0022 User watchdog scan time exceeded X 0023 Invalid or non existent STI interrupt file X 0024...

Page 372: ... detected X 0032 Sequencer length position points past end of data file X 0033 Length of LFU LFL FFU FFL BSL or BSR points past end of data file X 0034 A negative value for a timer accumulator or preset value was detected X Fixed processors with 24 VDC inputs only A negative or zero HSC preset was detected in an HSC instruction X 0035 TND SVC or REF instruction is called within an interrupting or ...

Page 373: ...tected on an I O module X xx52 A module required for the user program is detected as missing or removed X xx53 At going to run a user program declares a slot as unused and that slot is detected as having an I O module inserted Can also mean that an I O module has reset itself X xx54 A module required for the user program is detected as being the wrong type X xx55 A module required for the user pro...

Page 374: ...dentifies an I O module specific recoverable major error Refer to the user manual supplied with the specialty module X xx70 thru xx7F Identifies an I O module specific non recoverable major error Refer to the user manual supplied with the specialty module X xx90 Interrupt problem on disabled slot X xx91 A disabled slot has faulted X xx92 Invalid or non existent module interrupt subroutine file X x...

Page 375: ...xample You believe that limit switches connected to I 1 0 and I 1 1 cannot be energized at the same time yet your application program acts as if they can be To determine if you have a limit switch problem or a ladder logic problem add the following rung to your program If your program enters the SUS idle mode for code 1 when you run the program you have a limit switch control problem if the SUS id...

Page 376: ...mage data of an input module to freeze at its last value Also the outputs of an output module will freeze at their last values regardless of values contained in the output image Outputs remain frozen until either power is removed the Run mode is exited or a major fault occurs At that time the outputs will be zeroed until the slot is again enabled set Disabled slots do not have to match the user pr...

Page 377: ...an even or odd word boundary for ease of application and viewing Also we recommend that you design document and view the contents of 32 bit signed data in either the hexadecimal or binary radix When an STI I O Slot or Fault Routine interrupts normal execution of your program the original value of the math register is restored when execution resumes S 15L Node Address Read write This byte value con...

Page 378: ...19200 use either the EDT_DAT or NODE_CFG functions of your HHT The processor uses code 1 for 1200 baud code 2 for 2400 baud code 3 for 9600 baud and code 4 for 19200 baud Example showing runtime protection of baud rate 19200 code 4 S 15H equal to 4 and S 15L equal to 3 1027 decimal 0403 hex 0000 0100 0000 0011 binary S 15H equal to 4 1024 decimal 0400 hex 0000 0100 0000 0000 binary Example showing...

Page 379: ... file word S 19 number that the processor should stop in front of when executing in the Test Single Step mode To enable this feature you must select the Test Single Step option at the time you save your program If both the rung and file number are 0 the processor will step to the next rung only otherwise the processor will continue until it finds a rung file equaling the S 18 S 19 value The proces...

Page 380: ...example Your program contains several TON instructions TON T4 6 in file 2 rung 25 occasionally obtains a negative preset Recovery from the negative preset fault is possible by placing the preset at 100 and resetting the timer Place the following rung in your fault routine to accomplish this Bit B3 0 is latched as evidence that an application recovery has been initiated Note The HHT can save a SLC ...

Page 381: ...errogate this value using a programming device data monitor function if you need to determine or verify the longest scan time of your program The I O scan processor overhead and communication servicing are not included in this measurement S 23 Average Scan Time Read write This word indicates a weighted running average time The value indicates in 10 ms increments the time elapsed in the average pro...

Page 382: ...he 30 I O slots Bit S 27 1 through S 28 14 refer to slots 1 30 Bits S 27 0 and S 28 15 are reserved The default value of each bit is 1 set The enable bit associated with an interrupting slot must be set when the interrupt occurs to allow the corresponding ISR to execute Otherwise the ISR will not execute and the associated I O slot interrupt pending bit will become set Changes made to these bits u...

Page 383: ...write You enter a program file number 3 255 to be used as the selectable timed interrupt subroutine Write a 0 value to disable the STI To provide protection from inadvertent EDT_DAT alteration of your selection program an unconditional MOV instruction containing the file number value of your STI to S 31 or program a CLR instruction at S 31 to prevent STI operation Selectable timed interrupts are d...

Page 384: ...er 3 for 9600 Enter 2 for 2400 Enter 4 for 19200 S2 15H 4 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 9 S2 10 Active Node List 1 2 3 0 0 0 0 0111 1000 0000 0000 0000 0000 0000 0000 Node 0 S2 9 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 11 S2 12 I O Slot Enables 1 2 3 0 0 0 0 1111 1111 1111 1111 1111 1111 1111 1111 Slot 0 S2 11 0 1 PR...

Page 385: ... Fault Code 0000H Desc No Error S2 3L Program Scan x10mS last 0 S2 3H Watchdog x10mS 10 S2 5 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 7 Suspend Code 0 S2 8 Suspend File 0 S2 4 Running Clock 0000 0000 0000 0000 S2 13 14 Math Register 00000000H S2 7 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 15H Communication KBaud Rate 19 2 S2 15...

Page 386: ...o automatically transfer a new non faulted program from the memory module to RAM when power is cycled Refer to chapter 27 for more information on status bits S 1 13 S 1 8 S 1 10 S 1 11 and S 1 12 Application Note You can declare your own application specific major fault by writing your own unique value to S 6 and then setting S 1 13 User Fault Routine in Effect SLC 5 02 Processors Only When you de...

Page 387: ...c Status 0000 0000 0000 0000 S2 1 Proc Status 0000 0000 1000 0001 S2 2 Proc Status 1000 0000 0000 0010 S2 0 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG SLC 5 02 Processors Fixed and SLC 5 01 Processors D C B A A B C and D in the figure above indicate the location of fault information A Word S2 1 Bit S2 1 13 in this word is the major fault bit Clear the fault bit at this display by setting S2 1...

Page 388: ...not meet the required revision level The revision level of the processor is not compatible with the revision level for which the program was developed Consult your local A B representative to purchase an upgrade kit for your processor 0011 The executable program file number 2 is absent Incompatible or corrupt program is present Reload the program or reprogram with A B approved programming device 0...

Page 389: ...for details on the operation of status bit S 1 9 Either reset bit S 1 9 if this is consistent with the application requirements and change the mode back to run or clear S 1 13 the major fault bit before the end of the first program scan is reached Error Code Hex Description Probable Cause Recommended Action 0004 Memory error occurred during the Run mode Either noise lightning improper grounding la...

Page 390: ...he fault will be cleared Fixed and FRN 1 to 4 SLC 5 01 processors Cycle power on the local rack SLC 5 02 processors and FRN 5 and higher SLC 5 01 processors Re apply power to the expansion rack 0022 The user watchdog scan time has been exceeded Either Watchdog time is set too low for the user program or user program caught in a loop Either increase the watchdog timeout in the status file S 3H or c...

Page 391: ... last data file created by the user Correct and reload the user program This problem cannot be corrected by writing to the index register word S 24 002A Indexed address reference is beyond the specific referenced data file The program is referencing through indexed addressing an element beyond a file boundary Correct the user program allocate more data space using the memory map or re save the pro...

Page 392: ...ccumulated or preset word of a timer make certain these values cannot be negative Correct the user program reload and run 0034 related to HSC instruction A negative or zero HSC preset was detected in an HSC instruction The preset value for the HSC instruction is out of the valid range Valid range is 1 32767 If the user program is moving values to the preset word of the HSC instruction make certain...

Page 393: ...le user manual for the probable cause Cycle power to the system If this does not correct the problem replace the module xx52 A module required for the user program is detected as missing or removed An I O module configured for a particular slot is missing or has been removed Either disable the slot in the status file S 11 and S 12 or Insert the required module in the slot xx53 At going to run a us...

Page 394: ...the specialty I O module You may have to replace the module xx59 A specialty I O module has not responded to a command as being completed within the required time limit A specialty I O module did not complete a command from the processor in the time allowed Refer to the user manual for the specialty I O module You may have to replace the module xx5A Hardware interrupt problem stuck If this is a di...

Page 395: ...alid or non existent module interrupt subroutine ISR file The I O configuration ISR file information for a specialty I O module is incorrect Correct the I O configuration ISR file information for the specialty I O module Refer to the user manual for the module for the correct ISR file information Then reload the program and run xx93 Unsupported I O module specific major error The processor does no...

Page 396: ...ple on page 29 6 shows All application examples shown are in the HHT zoom display Status File Data Saved Data in the following words is saved on entry to the designated subroutine and re written upon exiting the subroutine S 0 Arithmetic flags S 13 and S 14 Math register S 24 Index register Faults are classified as recoverable and non recoverable user faults and non user faults A complete list app...

Page 397: ...owerdown occurred while running RUNTIME ERRORS 0020 A minor error bit is set at the end of the scan 0029 Indexed address reference outside of entire data file space range of B3 0 through the last file INSTRUCTION ERRORS 0032 Sequencer length position points past end of data file 0033 Length of LFU LFL FFU FFL BSL or BSR points past end of data file 0034 A negative value for a timer accumulator or ...

Page 398: ...the user program is detected as having the wrong I O count or wrong I O driver xx57 A specialty I O module has not responded to a lock shared memory command within the required time limit xx59 A specialty I O module has not responded to a command as being completed within the required time limit xx5A Hardware interrupt problem xx5B G file configuration error User program G file size exceeds capaci...

Page 399: ...ttempt was made to jump to one too many nested subroutine files Can also mean that a program has potentially recursive routines 0031 Unsupported instruction reference was detected 0035 TND SVC or REF instruction is called within an interrupting or user fault routine I O ERRORS xx51 A stuck runtime error is detected on an I O module xx58 A specialty I O module has generated a generic fault The modu...

Page 400: ...down if the overflow trap bit S 5 0 is set Permit a processor shutdown when S 5 0 is set more than five times Prevent a processor shutdown if the accumulator value of timer T4 0 becomes negative Reset the negative accumulator value to zero Energize an output to indicate that the accumulator has gone negative one or more times Allow a processor shutdown for all other user faults A possible method o...

Page 401: ...ser faults except two 0020 MINOR ERROR AT END OF SCAN 0034 NEGATIVE VALUE IN TIMER PRE OR ACC If the fault code S 6 is 0020H subroutine file 4 is executed If the fault code is 0034H subroutine file 5 is executed END EQU EQUAL Source A S 6 0 Source B 32 Fault code 0020H 0000 0000 0010 0000 binary 32 decimal JSR JUMP TO SUBROUTINE SBR file number 4 JSR JUMP TO SUBROUTINE SBR file number 5 EQU EQUAL ...

Page 402: ...s case the processor is placed in the fault mode Fault code and description are indicated S 1 13 Cleared S 5 0 Cleared Status File Display At 1st through 5th overflow S 5 0 occurrences END SBR SUBROUTINE RET RETURN GRT GREATER THAN Source A C5 0 ACC 0 Source B 5 CU DN CTU COUNT UP Counter C5 0 Preset 120 Accum 0 U S 5 0 S 5 0 U C5 0 CU U S 1 13 RET RETURN S 5 0 F1 F2 F3 F4 F5 Status File S2 5 Mino...

Page 403: ...e of any other timer in the program is negative S 1 13 will be set and the processor will enter the fault mode O 3 0 3 will be reset if previously set Status File Display T4 0 ACC is negative END U S 1 13 RET RETURN SBR SUBROUTINE LES LESS THAN Source A T4 0 ACC 0 Source B 0 CLR CLEAR Dest T4 0 ACC 0 O 3 0 3 Fault code and description are indicated S 1 13 Cleared F1 F2 F3 F4 F5 Status File S2 5 Mi...

Page 404: ... file is discussed in chapter 7 Enter the STI subroutine file number in word S 31 of the status file See page 30 4 A file number of zero disables the STI function Enter the setpoint the time between successive interrupts in word S 30 of the status file see page 30 4 The range is 10 to 2550 milliseconds entered in 10ms increments A setpoint of zero disables the STI function Important The setpoint v...

Page 405: ...urrences STI interrupts can occur at any point in your program but not necessarily at the same point on successive interrupts Interrupts can only occur between instructions in your program inside the I O scan between slots or between the servicing of communications packets STI execution time adds directly to the overall scan time Processor Overhead Communication Output Scan Program Scan Input Scan...

Page 406: ...utine 2 STI subroutine 3 I O interrupt subroutine ISR An executing interrupt can only be interrupted by an interrupt having higher priority Status File Data Saved Data in the following words is saved on entry to the STI subroutine and re written upon exiting the STI subroutine S 0 Arithmetic flags S 13 and S 14 Math register S 24 Index register ...

Page 407: ...3 and 255 is present in word S 31 and a setpoint value between 1 and 255 is present in word S 30 a set enable bit allows scanning of the STI file If the bit is reset by an STD instruction scanning of the STI file no longer occurs If the bit is set by an STE or STS instruction scanning is again allowed The enable bit only enables disables the scanning of the STI subroutine It does not affect the ST...

Page 408: ...G PREV PG F1 F2 F3 F4 F5 Status File Selectable Timed Interrupt S2 31 Subroutine File 0 S2 30 Frequency x10mS 0 Enabled 1 Executing 0 Pending 0 S2 31 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG A B C D E F G H I A Word S 2 Bits 0 1 and 2 are the STI pending enabled and executing bits respectively These bits also appear in the Selectable Timed Interrupt display See G H I B Word S 5 Bit S 5 10 is ...

Page 409: ...NABLE EDT_DAT STD Selectable Timed Disable This instruction when true will reset the STI enable bit and prevent the STI subroutine from executing When the rung goes false the STI enable bit remains reset until a true STS or STE instruction is executed The STI timer continues to operate while the enable bit is reset STE Selectable Timed Enable This instruction upon a false true transition of the ru...

Page 410: ...sets the enable bit again The STI timer increments and may time out in the STD zone setting the pending bit S 2 0 and overrun bit S 5 10 The first pass bit S 1 15 and the STE instruction in rung 0 are included to insure that the STI function is initialized following a power cycle You should include this rung any time your program contains an STD STE zone or an STD instruction S 1 15 STI interrupt ...

Page 411: ... Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays monitor mode F1 F2 F3 F4 F5 ZOOM on STS STS 2 9 0 0 1 NAME SELECTABLE TIMED START FILE 3 3 TIME 30 30 EDT_DAT STS Selectable Timed Start Immediately The STS instruction requires you to enter two parameters the STI file number and the STI setpoint Upon a true execution of the rung this instruction will enter the file number and setpo...

Page 412: ...regular subroutine Use of the instruction is optional Interrupt Subroutine INT INT F1 F2 F3 F4 F5 ZOOM on INT INT 2 3 0 0 1 NAME I O INTERRUPT EDT_DAT HHT Ladder Display HHT Zoom Display Ladder Diagrams and APS Displays online monitor mode INT INTERRUPT SUBROUTINE Interrupt Subroutine This instruction has no control bits and is always evaluated as true When used the INT should be programmed as the...

Page 413: ...described in the user s manual for the module I O event driven interrupts cannot be accomplished using standard discrete I O modules Basic Programming Procedure for the I O Interrupt Function Specialty I O modules which create interrupts should be configured in the lowest numbered I O slots When you are configuring the specialty I O module slot with the HHT select the ADV_SET and INT_SBR function ...

Page 414: ...ubroutine The ISR will contain the rungs of your application logic You can program any instruction inside an ISR except a TND REF or SVC instruction IIM or IOM instructions are needed in an ISR if your application requires immediate update of input or output points Terminate the ISR with an RET return instruction JSR stack depth is limited to 3 That is you may call other subroutines to a level 3 d...

Page 415: ... Note It is important to understand that the I O Pending bit associated with the interrupting slot remains clear during the time that the processor is waiting for the fault routine or STI subroutine to finish If a major fault occurs while executing the I O interrupt subroutine execution will immediately switch to the fault routine If the fault was recovered by the fault routine execution will resu...

Page 416: ... 1 through 30 Bits S 27 0 and S 28 15 are reserved The enable bit associated with an interrupting slot must be set when the interrupt occurs to allow the corresponding ISR to execute Otherwise the ISR will not execute and the associated I O slot interrupt pending bit will be set Changes made to these bits using the EDT_DAT function take effect at the next end of scan S 25 and S 26 I O Interrupt Pe...

Page 417: ...EXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 27 S2 28 I O Interrupt Enables 1 2 3 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 S2 27 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 Status File S2 25 S2 26 I O Interrupt Pending 1 2 3 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 S2 25 0 0 PRG ADDRESS NEXT FL PREV FL NEXT PG PREV PG A B C A Words S 11 and S 12 I O...

Page 418: ...AME I O INTERRUPT DISABLE 1 2 3 0 0 0 0 0100 1111 1111 1111 1111 1111 1111 1111 EDT_DAT HHT Ladder Display HHT Zoom Display F1 F2 F3 F4 F5 ZOOM on IIE IIE 2 0 0 0 1 NAME I O INTERRUPT ENABLE 1 2 3 0 0 0 0 0011 0000 0000 0000 0000 0000 0000 0001 EDT_DAT IID I O INTERRUPT DISABLE Slots 2 3 IIE I O INTERRUPT ENABLE Slots 2 3 Ladder Diagrams and APS Displays I O Interrupt Disable IID Output Instructio...

Page 419: ...a programming device or standard instruction such as MVM takes effect at the END of the scan only Parameter Enter a 0 reset in a slot position to indicate a disabled I O interrupt IIE I O Interrupt Enable When true this instruction sets the I O interrupt enable bits S 27 1 through S 28 14 corresponding to the slots parameter of the instruction slots 1 2 7 in the following example Interrupt subrout...

Page 420: ...wing a power cycle You should include a rung such as this any time your program contains an IID IIE zone or an IID instruction The IID instruction in rung 6 clears the I O interrupt enable bits associated with slots 1 2 and 7 S 27 1 S 27 2 and S 27 7 The IIE instruction in rung 12 sets these same bits If an I O interrupt is detected by the processor while the processor is executing rungs 7 11 the ...

Page 421: ... This instruction does not affect the I O slot interrupt enable bits S 27 1 through S 28 14 Parameter Enter a 0 reset in a slot position to indicate that the pending status of an I O interrupt is reset aborted Reset Pending Interrupt RPI Output Instruction RPI HHT Ladder Display HHT Zoom Display F1 F2 F3 F4 F5 ZOOM on RPI RPI 2 0 0 0 1 NAME RESET PENDING INTERRUPT 1 2 3 0 0 0 0 0000 0000 0000 0000...

Page 422: ...eparate rung for the additional branches BRANCH WILL EXCEED NEST LIMIT You are attempting to begin a branch within an existing branch for 500 or 5 01 Or you are attempting to exceed the nest level for a 5 02 Referring to page 5 7 in this manual The processor is in a fault condition and try to enter the Run mode Correcting the fault CANNOT GENERATE You are trying to enable forces where none exist I...

Page 423: ...d to contain only one HSC instruction processor must be DC type Removing duplicate HSC instructions ERROR EXPANDING THE DATA TABLE The length parameter of an instruction is trying to create a data file larger than 256 elements Entering a smaller length ERROR INVALID FORCE The cursored instruction is not an input or output instruction Choosing the correct type of instruction or abandoning this atte...

Page 424: ... procedure INCOMPATIBLE PROCESSOR The HHT is attempting to communicate with an invalid processor type Aborting the procedure or changing the configuration PROCESSOR TYPE The processor that you have configured in your program does not match the processor your HHT is communicating with Going offline and changing the processor type in the Processor Configuration INCORRECT PASSWORD You have tried to e...

Page 425: ...ion in the rung Removing the other instructions in that rung MISSING DESTINATION There is an internal compiler error Contacting your A B service representative MODULE ID CODE NOT SUPPORTED When you are configuring I O and the HHT is unable to find a slot configuration which matches this ID number Entering a valid ID number MULTIPLE OSR INSTRUCTIONS When you attempt to enter multiple OSR instructio...

Page 426: ...During a search the entered instruction address or force is not present in the ladder program Aborting the search or entering the correct information NOT IMMEDIATE Data file addresses are not allowed Entering an immediate value NOT IN A BRANCH You are attempting to extend or close a branch without first beginning the branch Beginning a branch NOT INDEXED The address entered is not an indexed addre...

Page 427: ...or in slot 0 is not configured correctly Configuring the slot RESET RST USED ON A TIMER OFF DELAY TOF A reset RST instruction has been used to reset a Timer Off Delay instruction TOF You cannot use a RST to reset a TOF Remove the RST instruction ROM TEST FAILED FATAL ERROR The memory pak of the HHT has failed The HHT is inoperable Replacing the memory pak RUNG HAS NO OUTPUT INSTRUCTION You attempt...

Page 428: ...O EDIT FILE The file number entered does not exist in this ladder program Choosing the correct file number UNABLE TO INSERT INSTRUCTION Inserting this instruction results in an illegal rung structure Aborting the procedure UNABLE TO MONITOR FILE The file number entered either does not exist in the processor ladder program or it is a file type not capable of being monitored Choosing a different fil...

Page 429: ...TS The program data changes you have entered are stored only in the processor program If you wish to save the data changes in the HHT you must upload the program Uploading the ladder program to the HHT WARNING PRG REFERNCES UNDEFINED You are attempting to delete a rack or reduce the slot size of a rack where the ladder program indicates there are input or output instructions referencing slots in t...

Page 430: ...alue of the position The equivalent decimal value of the binary number is the sum of the position values Positive Decimal Values The far left position is always 0 for positive values As indicated in the figure below this limits the maximum positive decimal value to 32767 All positions are 1 except the far left position 1x214 16384 1x213 8192 1x212 4096 1x211 2048 1x210 1024 1x29 512 1x28 256 1x27 ...

Page 431: ...m of the values of the other positions In the figure below all positions are 1 and the value is 32767 32768 1 1x214 16384 1x213 8192 1x212 4096 1x211 2048 1x210 1024 1x29 512 1x28 256 1x27 128 1x26 64 1x25 32 1x24 16 1x23 8 1x22 4 1x21 2 1x20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 32767 1x215 32768 This position is always 1 for negative numbers The...

Page 432: ...o the right of that position For example 16 bit pattern 1111 1111 0001 10102 24 23 21 28 16 8 2 256 230 Binary Coded Decimal numbers use a 4 bit binary code to represent decimal values ranging from 0 to 9 as shown below BCD Value 0 1 2 3 4 5 6 7 8 9 Binary Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Thumbwheels and LED displays are two types of I O devices that use BCD numbers The posi...

Page 433: ...l number 9862 Position Values 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 9 8 6 2 Binary Pattern Thousands Hundreds Tens Ones 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 Decimal value Hexadecimal numbers use single characters 0 to 9 and A to F to represent decimal values ranging from 0 to 15 1 0 2 3 5 4 6 7 9 8 A B D C E F 1 0 2 3 5 4 6 7 9 8 10 11 13 12 14 15 HEX Decimal The position values of hexadecimal numbers are po...

Page 434: ...eeds the maximum positive value of 32767 To calculate its value subtract 164 the next higher power of 16 from 56950 56950 65536 8586 This is a 4 character code entered as a parameter in SQO SQC and other instructions to exclude selected bits of a word from being operated on by the instruction The hex values are used in their binary equivalent form as indicated in the figure below The figure also s...

Page 435: ...of the source word is passed to the destination word Data in bits 8 15 of the source word is not passed to the destination word Destination bits 8 15 are not affected they are left in their last state 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 0 Source Word 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Mask Word 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 Destination Word all bits 0 initially Allen Bradley Parts ...

Page 436: ...ory Capacity Fixed and SLC 5 01 Fixed I O Controllers 1024 instruction words Fixed and SLC 5 01 Modular Controllers 1747 L511 1024 instruction words SLC 5 02 Modular Controllers 1747 L524 4096 instruction words Definition 1 instruction word 4 data words 8 bytes The number of instruction words used by the individual instructions is indicated in the following table Since the program is compiled by t...

Page 437: ...D 1 5 DDV 1 DIV 1 5 EQU 1 5 FLL 1 5 FRD 1 GEQ 1 5 GRT 1 5 HSC 1 IIM 1 5 IOM 1 5 JMP 1 JSR 1 LBL 0 5 LEQ 1 5 LES 1 5 Instruction Instruction Words approx MCR 0 5 MEQ 1 5 MOV 1 5 MUL 1 5 MVM 1 5 NEG 1 5 NEQ 1 5 NOT 1 OR 1 5 OSR 1 OTE 0 75 OTL 0 75 OTU 0 75 RES 1 RET 0 5 RTO 1 SBR 0 5 SQC 2 SQO 2 SUB 1 5 SUS 1 5 TND 0 5 TOD 1 TOF 1 TON 1 XIC 1 XIO 1 XOR 1 5 Fixed and SLC 5 01 Processors Allen Bradley...

Page 438: ...er the result 7 Multiply the total number of I O slots used or unused by 75 and enter the result 8 To account for processor overhead enter 65 if you are using a fixed controller enter 67 if you are using a 1747 L511 or 1747 L514 9 Total steps 1 through 8 This is the estimated total memory usage of your application system Remember this is an estimate actual compiled programs may differ by 12 Total ...

Page 439: ... 15 1746 IA16 10 1746 OA8 1 1747 DCM full configuration 1 1746 NI4 1 1746 NIO4I 50 XIC and XIO 50 x 1 00 50 00 15 OTE instructions 15 x 0 75 11 25 5 TON instructions 5 x 1 00 5 00 3 GRT instructions 3 x 1 50 4 50 1 SCL instruction 1 x 1 75 1 75 1 TOD instruction 1 x 1 00 1 00 3 MOV instructions 3 x 1 50 4 50 10 CTU instructions 10 x 1 00 10 00 10 RES instructions 10 x 1 00 10 00 Instruction Usage ...

Page 440: ... 75 MOV 12 20 MUL 12 230 MVM 12 115 NEG 12 110 NEQ 12 60 NOT 12 66 OR 12 87 OSR 12 34 OTE 18 18 OTL 19 19 OTU 19 19 RES 12 40 RET 12 34 RTO 12 140 SBR 2 2 SQC 12 225 SQO 12 225 SUB 12 125 SUS 12 12 TND 12 32 TOD 12 200 TOF 12 140 TON 12 135 XIC 4 4 XIO 4 4 XOR 12 87 For the rung example at the right 1 If instruction 1 is false instructions 2 3 4 5 6 7 take zero execution time Execution time 4 18 2...

Page 441: ...ruction Words approx ADD 1 5 AND 1 5 BSL 2 BSR 2 CLR 1 COP 1 5 CTD 1 CTU 1 DCD 1 5 DDV 1 DIV 1 5 EQU 1 5 FFL 1 5 FFU 1 5 FLL 1 5 FRD 1 GEQ 1 5 GRT 1 5 HSC 1 IID 1 25 IIE 1 25 IIM 1 5 INT 0 5 IOM 1 5 Instruction Instruction Words approx JMP 1 JSR 1 LBL 0 5 LEQ 1 5 LES 1 5 LFL 1 5 LFU 1 5 LIM 1 5 MCR 0 5 MEQ 1 5 MOV 1 5 MSG 34 75 MUL 1 5 MVM 1 5 NEG 1 5 NEQ 1 5 NOT 1 OR 1 5 OSR 1 OTE 0 75 OTL 0 75 O...

Page 442: ...the result Refer to the table on page C 6 2 Multiply the total number of rungs by 375 and enter the result 3 If you are using a 1747 L524 and have enabled the Single Step Test mode multiply the total number of rungs by 375 and enter the result 4 Multiply the total number of data words excluding the status file and I O data words by 25 and enter the result 5 Add 1 word for each data table file used...

Page 443: ...ution time Execution time 4 4 4 18 30 microseconds Execution Time in Microseconds approx False True ADD 12 126 AND 12 91 BSL 12 148 24 per word BSR 12 138 24 per word CLR 12 44 COP 12 49 21 per word CTD 12 115 CTU 12 115 DCD 12 84 DDV 12 654 DIV 12 404 EQU 12 64 FFL 85 250 FFU 85 250 18 x position value FLL 12 41 14 per word FRD 12 227 GEQ 12 64 GRT 12 64 IID 12 65 IIE 12 70 IIM 12 552 INT 0 0 IOM...

Page 444: ...ses For each bit or word instruction add 1928 microseconds to the execution time For each multiple word instruction add 1583 microseconds plus 667 microseconds per word M1 3 1 1 M0 2 1 1 M0 2 1 10 MOV MOVE Source M1 10 7 Dest N7 10 Example COP COPY FILE Source B3 0 Dest M0 1 0 Length 34 For the multi word instruction above add 1583 microseconds plus 667 microseconds per word In this example 34 wor...

Page 445: ...9 13 per word CTD 7 69 CTU 7 69 DCD 7 50 DDV 7 392 DIV 7 242 EQU 38 38 FFL 51 150 FFU 51 150 11 x position value FLL 7 25 8 per word FRD 7 136 GEQ 38 38 GRT 38 38 IID 7 39 IIE 7 42 IIM 7 340 INT 0 0 IOM 7 465 JMP 7 23 JSR 7 28 LBL 1 4 LEQ 38 38 LES 38 38 LFL 51 150 LFU 51 180 LIM 7 45 MCR 6 6 MEQ 7 47 MOV 7 14 Execution Time in Microseconds approx False True Instruction Series C SLC 5 02 For the r...

Page 446: ...5 1 75 1 TOD instruction 1 x 1 00 1 00 3 MOV instructions 3 x 1 50 4 50 10 CTU instructions 10 x 1 00 10 00 10 RES instructions 10 x 1 00 10 00 Instruction Usage 98 00 30 rungs 30 x 0 375 11 25 100 data words 100 x 0 25 25 00 10 is highest data table file number 10 x 1 10 00 4 is highest program file number 4 x 2 8 00 User Program Total 163 50 49 I O data words 49 x 0 75 36 75 30 slot 30 x 0 75 22...

Page 447: ...ach bit or word instruction add 1157 microseconds to the execution time For each multiple word instruction add 950 microseconds plus 400 microseconds per word M1 3 1 1 M0 2 1 1 M0 2 1 10 MOV MOVE Source M1 10 7 Dest N7 10 Example COP COPY FILE Source B3 0 Dest M0 1 0 Length 34 For the multi word instruction above add 950 microseconds plus 400 microseconds per word In this example 34 words are copi...

Page 448: ...can Events in the processor operating cycle Event Description Input Scan The status of input modules is read and the input image in the processor is updated with this information Program Scan The ladder program is executed The input image table is evaluated ladder rungs are solved and the output image is updated The information is not yet transferred to the output modules Output Scan The output im...

Page 449: ...active DH 485 network During this event the processor accepts characters from the network and places them into a packet buffer Foreground Communications Occurs only when another node is attached or when another processor sends an MSG instruction to your processor During this event the processor performs the communication commands contained in completed packets built during background communication...

Page 450: ...dules Number of 1 4 DCM or analog combo ________ x 620 e ________ Number of 1 2 DCM analog output or 1746 HS ________ x 1028 f ________ Number of 3 4 DCM ________ x 1436 g ________ Number of full DCM BASIC or 1747 DSN ________ x 1844 h ________ D Add lines a through h Place this value on line i Add 129 to the value on line i This sum is your minimum output scan time i ________ 129 E Calculate your...

Page 451: ...______ Number of full DCM BASIC or 1747 DSN ________ x 1844 g ________ C Add lines a through g Place this value on line h Add 129 to the value on line h This sum is your minimum output scan time h ________ 129 D Calculate your maximum output scan time Maximum output scan time Minimum scan time Number of specialty I O modules x 50 E Calculate the Forced Output Overhead Forced Output Overhead Number...

Page 452: ...of BASIC Lg config 1746 HSCE ________ x 1399 h ________ Number of RI O Scanner or 30 block DSN ________ x 4367 i ________ D Add lines a through i Place this value on line j Add 138 to the value on line j This sum is your minimum output scan time j ________ 138 E Calculate your maximum output scan time Minimum scan time Number of specialty I O modules in part B x 30 Number of specialty I O modules ...

Page 453: ... page D 7 The ladder program below is used in this application The execution times for the instructions true state are from appendix C The total execution time 465 microseconds is entered in the worksheet on page D 7 The worksheet indicates that the total estimated scan time is 3 85 milliseconds minimum and 8 9 milliseconds maximum END B3 1 O 1 0 0 EN DN TON TIMER ON DELAY Timer T4 0 Time Base 0 0...

Page 454: ...747 DSN 0 x 1844 g 0 C Add lines a through g Place this value on line h Add 138 to the value on line h This sum is your minimum output scan time h 1609 138 D Calculate your maximum output scan time Maximum output scan time Minimum scan time Number of specialty I O modules x 50 E Calculate the Forced Output Overhead Forced Output Overhead Number of output modules x 172 140 per additional word for m...

Page 455: ...ift 1 9 B battery installing 1 3 specifications 1 1 BCD convert from FRD 15 5 20 15 convert to TOD 15 5 20 12 ladder logic filtering of 20 16 mnemonic for converting from 2 14 number systems B 3 bit data file display 12 8 bit instructions 15 1 16 1 examine if closed XIC 15 1 16 2 examine if open XIO 15 1 16 3 one shot rising OSR 15 1 16 7 output energize OTE 15 1 16 4 output latch OTL 15 1 16 5 ou...

Page 456: ...convert to BCD TOD 5 02 processor example 20 13 fixed 5 01 and 5 02 processor example 20 14 math instruction 15 5 20 12 mnemonic listing 2 15 COP file copy and file fill instruction 22 2 copying an instruction 7 30 count down CTD mnemonic listing 2 14 timer and counter instructions 15 2 17 7 count up CTU mnemonic listing 2 14 timer and counter instructions 15 2 17 7 counter data file display 12 8 ...

Page 457: ... copying rungs 7 31 deleting data 4 20 dimensions 1 1 display area example of 1 2 1 8 divide DIV math instruction 15 5 20 8 mnemonic listing 2 14 double divide DDV math instruction 15 5 20 9 mnemonic listing 2 14 downloading a program from the HHT to a processor 10 1 downloading program from HHT to processor 3 3 E editing a program file 7 4 abandoning edits 7 34 adding a rung 7 9 adding an instruc...

Page 458: ...ill instruction 15 6 22 2 mnemonic listing 2 14 file copy and file fill instructions 15 6 22 1 file copy COP 15 6 22 2 file fill FLL 15 6 22 4 file fill FLL file copy and file fill instruction 15 6 22 4 mnemonic listing 2 14 fixed processor instruction words C 2 status file displays 27 33 FLL file copy and file fill instruction 22 4 force function FORCED I O LED 13 3 13 4 13 5 forces carried offli...

Page 459: ...ons instructions 15 3 18 15 mnemonic listing 2 14 immediate output with mask IOM I O message and communications instructions 15 3 18 16 mnemonic listing 2 14 indexed addressing for 5 02 processors 4 13 creating data 4 14 crossing file boundaries 4 14 effects of file instructions on 4 15 monitoring 4 15 input branching 5 5 input data file display 12 5 inserting an instruction within a branch 7 12 i...

Page 460: ...O instruction 15 7 23 8 mnemonic listing 2 14 LIFO unload LFU 5 02 processor 23 8 LIFO instruction 15 7 23 8 mnemonic listing 2 14 limit test LIM 5 02 processor 19 9 comparison instruction 15 4 19 9 mnemonic listing 2 14 logical continuity 5 3 M manuals related P 4 masked comparison for equal MEQ comparison instruction 15 4 19 8 mnemonic listing 2 14 masked move MVM mnemonic listing 2 14 move and ...

Page 461: ...uctions 15 6 21 8 not equal NEQ comparison instruction 15 4 19 3 mnemonic listing 2 15 number systems B 1 BCD B 3 binary B 1 hex mask B 5 hexadecimal B 4 O one shot rising OSR bit instruction 15 1 16 7 mnemonic listing 2 15 operating cycle 5 11 or OR mnemonic listing 2 15 move and logical instructions 15 6 21 6 OSR one shot rising bit instruction 16 7 OTE output energize bit instruction 16 4 OTL o...

Page 462: ...ection 7 41 searching for an address 7 38 searching for an instruction 7 37 searching for an instruction within an address 7 40 searching for forced I O 7 42 13 6 searching for rungs 7 44 searching for an address 7 38 searching for an address within an instruction 7 40 searching for an instruction 7 37 searching for forced I O 7 42 13 6 searching for rungs 7 44 selectable timed disable STD 5 02 pr...

Page 463: ... 11 2 single scan 11 2 the file indicator 4 16 timer and counter instructions 15 2 17 1 count down CTD 15 2 17 7 count up CTU 15 2 17 7 high speed counter HSC 15 2 17 9 reset RES 15 2 17 13 retentive timer RTO 15 2 17 5 timer off delay TOF 15 2 17 4 timer on delay TON 15 2 17 3 timer data file display 12 8 timer off delay TOF mnemonic listing 2 15 timer and counter instructions 15 2 17 4 timer on ...

Page 464: ...ing the file indicator 4 16 UVPROMs 3 4 program loading with 14 6 V viewing program memory layout 8 5 W WHO function 9 4 attach 9 7 diagnostics 9 6 node configuration 9 8 set and clear ownership 9 10 when using DH 485 devices 9 12 X XIC examine if closed bit instruction 16 2 XIO examine if open bit instruction 16 3 Z ZOOM key 1 12 ...

Page 465: ...tugal Puerto Rico Qatar Romania Russia CIS Saudi Arabia Singapore Slovakia Slovenia South Africa Republic Spain Switzerland Taiwan Thailand The Netherlands Turkey United Arab Emirates United Kingdom United States Uruguay Venezuela Yugoslavia World Headquarters Allen Bradley 1201 South Second Street Milwaukee WI 53204 USA Tel 1 414 382 2000 Fax 1 414 382 4444 Allen Bradley has been helping its cust...

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