Alinx ZYNQ UltraScale+ AXU2CG-E, User Manual, Page: 49 / 56

ZYNQ Ultr FPGA Board AXU2CG-E User Manual
49 / 56
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MIPI interface pin assignment
Signal Name ZYNQ Pin Name ZYNQ Pin
Number
Description
MIPI_CLK_P B65_L1_P W8 MIPI Input Clock Positive
MIPI_CLK_N B65_L1_N Y8 MIPI Input Clock Negative
MIPI_LAN0_P B65_L2_P U9 MIPI Input Date LANE0 Positive
MIPI_LAN0_N B65_L2_N V9 MIPI Input Date LANE0 Negative
MIPI_LAN1_P B65_L3_P U8 MIPI Input Date LANE1 Positive
MIPI_LAN1_N B65_L3_N V8 MIPI Input Date LANE1 Negative
CAM_GPIO B43_L4_P AE10 GPIO Control of Camera
CAM_CLK B43_L4_N AF10 Clock Input of Camera
CAM_SCL B43_L11_P Y9 I2C Clock of Camera
CAM_SDA B43_L11_N AA8 I2C Data of Camera
Part 3.12: JTAG Debug Port
The JTAG interface is reserved on the AXU3EG expansion board for
downloading ZYNQ Ult programs or firmware programs to FLASH. In
order to not damage the ZYNQ Ult chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ Ult chip.