ZYNQ Ultr FPGA Board AXU2CG-E User Manual
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JTAG debugging interface
1-Channel temperature sensor
1-Channel EEPROM
1-Channel RTC real-
3 LED lights
3 Key
Part 3.2: M.2 Interface
The AXU3EG development board is equipped with a PCIE x1 standard
M.2 interface for connecting M.2 SSD solid state drives, with a communication
speed of up to 6Gbps. The M.2 interface uses the M key slot, which only
supports PCI-E, not SATA. When users choose SSD solid state drives, they
need to choose PCIE type SSD solid state drives.
The PCIE signal is directly connected to the BANK505 PS MGT
transceiver of ZU3EG, and the TX signal and RX signal of one channel are
connected to the LANE1 of MGT in a differential signal mode. The PCIE clock
is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic
diagram of the M.2 circuit design is shown in Figure 3-2-1:
ZYNQ
Ultra
Scale+
PCIE_TX_P
U1
BANK
505
MGT
PCIE_TX_C_P
PCIE_TX_N
PCIE_TX_C_N
PCIE_RX_P
PCIE_RX_N
Si5332
505_PCIE_REFCLK_P
505_PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_REFCLK_N
M2_PCIE_RST_N
电平转换
PCIE_RSTn_MIO37
Figure 3-2-1: M.2 Interface Schematic