manualshive.com logo in svg

Alinx ZYNQ UltraScale+ AXU2CG-E, User Manual, Page: 38 / 56

Share
Download
Alinx ZYNQ UltraScale+ AXU2CG-E User Manual Download Page 38

 

 

 

 

ZYNQ Ultr FPGA Board AXU2CG-E User Manual 

 

  38 / 56

 

 

 

 

www.alinx.com 

ZYNQ

Ultra

Scale+

GT0_DP_TX_P

U1

BANK

505
MGT

GT0_DP_TX_C_P

GT0_DP_TX_N

GT0_DP_TX_C_N

Si5332

DP

参考时钟

GT1_DP_TX_P

GT1_DP_TX_C_P

GT1_DP_TX_N

GT1_DP_TX_C_N

BANK

501

电平

转换

DP_AUX_OUT

DP_AUX_IN

DP_OE

DP_HPD

DP_AUX_OUT_LS

DP_AUX_IN_LS

DP_OE_LS

DP_HPD_LS

单端转

差分

DPAUX_P

DPAUX_N

U46

U37

27Mhz

 

Figure 3-3-1: DP interface design Schematic 

 

The DisplayPort interface ZYNQ pin assignment is as follows: 

Signal Name 

ZYNQ Pin Number 

ZYNQ Pin Number  Description 

GT0_DP_TX_P 

505_TX3_P 

B23 

Low bits of DP Data 

Transmit Positive 

GT0_DP_TX_N 

505_TX3_N 

B24 

Low bits of DP Data 

Transmit Negative 

GT1_DP_TX_P 

505_TX2_P 

C25 

High bits of DP Data 

Transmit Positive 

GT1_DP_TX_N 

505_TX2_N 

C26 

High bits of DP Data 

Transmit Negative 

505_CLK1_P 

505_CLK2_P 

C21 

DP Reference Clock 

Positive 

505_CLK1_N 

505_CLK2_N 

C22 

DP Reference Clock 

Negative 

DP_AUX_OUT 

PS_MIO27 

J15 

DP Auxiliary Data Output 

DP_AUX_IN 

PS_MIO30 

F16 

DP Auxiliary Data Input 

DP_OE 

PS_MIO29 

G16 

DP Auxiliary Data Output Enable 

DP_HPD 

PS_MIO28 

K15 

DP Insertion Signal Detection 

 

Summary of Contents for ZYNQ UltraScale+ AXU2CG-E

Page 1: ...ZYNQ UltraScale FPGA Development Board AXU2CG E User Manual...

Page 2: ...ZYNQ Ultrascale FPGA Board AXU2CG E User Manual 2 56 www alinx com Version Record Version Date Release By Description Rev 1 0 2021 09 11 Rachel Zhou First Release...

Page 3: ...Power Supply 24 Part 2 9 ACU2EG Core Board Form Factor 25 Part 2 10 Board to Board Connectors pin assignment 25 Part 3 Carrier Board 35 Part 3 1 Carrier Board Introduction 35 Part 3 2 M 2 Interface 3...

Page 4: ...al 4 56 www alinx com Part 3 14 EEPROM and Temperature sensor 51 Part 3 15 User LEDs 52 Part 3 16 Keys 53 Part 3 17 DIP Switch Configuration 53 Part 3 18 Power Supply 54 Part 3 19 ALINX Customized Fan...

Page 5: ...1 piece of 256Mb QSPI FLASH chip In the design of carrier board we have extended a wealth of interfaces for users such as 1 SATA M 2 interface 1 DP interface 4 USB 3 0 Interface 2 Gigabit Ethernet int...

Page 6: ...o processor system part Processor System PS and programmable logic part Programmable Logic PL On the PS side of the ZU2CG chip there are 4 DDR4 each with a capacity of up to 512MB The 8GB eMMC FLASH m...

Page 7: ...QSPI FLASH and there are 2 crystal oscillators to provide the clock a single ended 33 3333MHz crystal oscillator for the PS system and a differential 200MHz crystal oscillator for the PL logic DDR ref...

Page 8: ...Silicon Labs CP2102GM s USB UAR chip and the USB interface adopts MINI USB interface SD Card Slot Interface 1 Micro SD card holder used to store operating system image and file system 40 pin expansio...

Page 9: ...chip LM75 used to detect the temperature and humidity of the surrounding environment around the FPGA development board EEPROM One EEPROM 24LC04 with IIC interface Real Time Clock RTC 1 built in RTC re...

Page 10: ...400Mbps In addition a 256MBit QSPI FLASH and an 8GB eMMC FLASH chip are also integrated on the core board to start storage configuration and system files In order to connect with the carrier board the...

Page 11: ...ex A53 processors with a speed of up to 1 2Ghz and supports Level 2 Cache it also contains 2 Cortex R5 processors with a speed of up to 500Mhz The ZU2CG chip supports 32 bit or 64 bit DDR4 LPDDR4 DDR3...

Page 12: ...art are as follows ARM quad core Cortex A53 processor speed up to 1 2GHz each CPU 32KB level 1 instruction and data cache 1MB level 2 cache shared by 2 CPUs ARM dual core Cortex R5 processor speed up...

Page 13: ...d SHA System monitoring 10 bit 1Mbps AD sampling for temperature and voltage detection The main parameters of the PL logic part are as follows Logic Cells 103K Flip flops 94K Look up tables LUTs 47K B...

Page 14: ...is shown in Table 2 3 1 below Bit Number Chip Model Capacity Factory U12 U14 U15 U16 CXDQ2BFAM CG 256M x 16bit PANGO Table 2 3 1 DDR4 SDRAM Configuration The hardware design of DDR4 requires strict co...

Page 15: ..._DDR_DQS_P5_504 L23 PS_DDR4_DQS5_N PS_DDR_DQS_N5_504 K23 PS_DDR4_DQS6_P PS_DDR_DQS_P6_504 N26 PS_DDR4_DQS6_N PS_DDR_DQS_N6_504 N27 PS_DDR4_DQS7_P PS_DDR_DQS_P7_504 J26 PS_DDR4_DQS7_N PS_DDR_DQS_N7_504...

Page 16: ...Q29 PS_DDR_DQ29_504 AD27 PS_DDR4_DQ30 PS_DDR_DQ30_504 AD28 PS_DDR4_DQ31 PS_DDR_DQ31_504 AC28 PS_DDR4_DQ32 PS_DDR_DQ32_504 T22 PS_DDR4_DQ33 PS_DDR_DQ33_504 R22 PS_DDR4_DQ34 PS_DDR_DQ34_504 P22 PS_DDR4_...

Page 17: ...63_504 J25 PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM1_504 AE23 PS_DDR4_DM2 PS_DDR_DM2_504 AE25 PS_DDR4_DM3 PS_DDR_DM3_504 AE28 PS_DDR4_DM4 PS_DDR_DM4_504 R23 PS_DDR4_DM5 PS_DDR_DM5_504 H23...

Page 18: ...e FPGA core board ACU2CG is equipped with one 256MBit Quad SPI FLASH chip to form an 8 bit bandwidth data bus the flash model is MT25QU256ABA1EW9 which uses the 1 8V CMOS voltage standard Due to the n...

Page 19: ...4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 Part 2 5 eMMC Flash The ACU2CG core board is equipped with a large capacity 8GB eMMC FLASH chip the model is FEMDRM008G 58A39 Compatible with MTFC8GAKAJCN 4...

Page 20: ...necessary to configure the GPIO port function of the PS side as an EMMC interface Figure 2 5 1 shows the part of eMMC Flash in the schematic diagram Figure 2 5 1 QSPI Flash in the schematic Configura...

Page 21: ...m and PL logic can work independently The schematic diagram of the clock circuit design is shown in Figure 2 6 1 Figure 2 6 1 Core Board Clock Source PS System RTC Real Time Clock The passive crystal...

Page 22: ...hip The schematic diagram is shown in Figure 2 6 3 Figure 2 6 3 Active Crystal in PS part Clock pin assignment Signal Name Pin PS_CLK R16 PL System Clock Source The core board provides a differential...

Page 23: ..._N AF5 Part 2 7 LED There is a red power indicator PWR and a configuration LED DONE on the ACU2CG core board When the core board is powered on the power indicator will light up after the FPGA configur...

Page 24: ...tage of the ACU2CG core board is DC12V which is supplied by connecting the carrier board The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU2CG chip For the TPS65...

Page 25: ...cannot exceed 1 8V Part 2 9 ACU2EG Core Board Form Factor Figure 2 9 1 ACU2EG Core Board Form Factor Part 2 10 Board to Board Connectors pin assignment The core board has a total of four high speed e...

Page 26: ...supply of the carrier board but cannot exceed 1 8V the level standard of MIO is also 1 8V Pin assignment of board to board connector J29 J29 Pin Signal Name Pin Number J29 Pin Signal Name Pin Number...

Page 27: ...GND 61 B66_L3_P F2 62 B65_L12_P L3 63 B66_L3_N E2 64 B65_L12_N L2 65 GND 66 GND 67 B66_L1_P G1 68 B65_L13_N L6 69 B66_L1_N F1 70 B65_L13_P L7 71 GND 72 GND 73 B66_L6_P G5 74 B65_L21_P J7 75 B66_L6_N F...

Page 28: ...30 J30 Pin Signal Name Pin Number J30 Pin Signal Name Pin Number 1 B66_L14_P E5 2 FPGA_TDI R18 3 B66_L14_N D5 4 FPGA_TCK R19 5 GND 6 GND 7 B66_L22_P C8 8 FPGA_TDO T21 9 B66_L22_N B8 10 FPGA_TMS N21 11...

Page 29: ...7_N F13 62 B26_L3_N A13 63 B26_L7_P G13 64 B26_L3_P B13 65 GND 66 GND 67 B26_L9_N G14 68 B26_L2_N A14 69 B26_L9_P G15 70 B26_L2_P B14 71 GND 72 GND 73 B26_L5_N D14 74 B26_L4_N C13 79 B26_L5_P D15 76 B...

Page 30: ...connector J31 J31 Pin Signal Name Pin Number J31 Pin Signal Name Pin Number 1 B24_L10_P Y14 2 B24_L7_P AA13 3 B24_L10_N Y13 4 B24_L7_N AB13 5 GND 6 GND 7 B24_L6_P AC14 8 B44_L6_P AC12 9 B24_L6_N AC13...

Page 31: ...E13 57 B24_L9_P W14 58 B24_L4_N AF13 59 GND 60 GND 61 B24_L8_P AB15 62 B44_L5_P AE12 63 B24_L8_N AB14 64 B44_L5_N AF12 65 GND 66 GND 67 B44_L2_N AG11 68 B44_L4_N AF10 69 B44_L2_P AF11 70 B44_L4_P AE10...

Page 32: ...oard to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number 1 PS_MIO35 H17 2 PS_MIO30 F16 3 PS_MIO29 G16 4 PS_MIO31 H16 5 GND GND 7 8 PS_MIO58 F18 9 10 PS_MIO53 D16 11 GN...

Page 33: ...0 GND 61 PS_MIO47 H21 62 PS_MIO64 E19 63 PS_MIO48 J21 64 PS_MIO69 D19 65 GND 66 GND 67 PS_MIO41 J19 68 PS_MIO74 D20 69 PS_MIO32 J16 70 PS_MIO73 G21 71 GND 72 GND 73 PS_MIO46 L20 74 PS_MIO72 G20 75 PS_...

Page 34: ...scale FPGA Board AXU2CG E User Manual 34 56 www alinx com 103 VCCO_65 104 VCCO_66 105 GND 106 GND 107 12V 108 12V 109 12V 110 12V 111 12V 112 12V 113 12V 114 12V 115 12V 116 12V 117 12V 118 12V 119 12...

Page 35: ...roduction you can understand the 1 Channel M 2 interface 1 Channel DP output interface 4 USB 3 0 Interfaces 2 Channel 10 100M 1000M Ethernet RJ 45 interface 2 Channel USB Uart Interfaces 1 Channel Mic...

Page 36: ...e SSD solid state drives they need to choose PCIE type SSD solid state drives The PCIE signal is directly connected to the BANK505 PS MGT transceiver of ZU3EG and the TX signal and RX signal of one ch...

Page 37: ...PS_MIO37_501 J17 PCIE Reset Signal Part 3 3 DP Interface The AXU3EG development board has a standard DisplayPort output display interface for video image display The interface supports VESA DisplayPo...

Page 38: ...follows Signal Name ZYNQ Pin Number ZYNQ Pin Number Description GT0_DP_TX_P 505_TX3_P B23 Low bits of DP Data Transmit Positive GT0_DP_TX_N 505_TX3_N B24 Low bits of DP Data Transmit Negative GT1_DP_...

Page 39: ...as USB mouse keyboard or U disk at the same time The schematic diagram of USB3 0 connection is shown as 3 4 1 USB_SSTXP U1 USB_SSTXN Si5332 USB3 0 USB_SSRXP USB_SSRXN ZYNQ Ultra Scale USB PHY USB3320...

Page 40: ...icrel s KSZ9031RNX Ethernet PHY chip to provide users with network communication services The KSZ9031RNX chip supports 10 100 1000 Mbps network transmission rate and communicates with the MAC layer of...

Page 41: ...d on the rising edge and falling samples of the clock ZYNQ Ultra Scale GPHY KSZ9031RNX U4 U1 BANK 502 RGMII TX RGMII RX GPHY KSZ9031RNX U22 BANK 66 RGMII TX RGMII RX J6 J11 Figure 3 5 1 ZYNQ PS system...

Page 42: ...Data Bit3 PHY1_RXCTL PS_MIO75 A19 Ethernet 1 Receive Enable Signal PHY1_MDC PS_MIO76 B20 Ethernet 1 MDIO Clock Management PHY1_MDIO PS_MIO77 F20 Ethernet 1 MDIO Management Data PHY2_TXCK B66_L17_N E8...

Page 43: ...rface to provide user access to the SD card memory the BOOT program for the ZU3EG chip the Linux operating system kernel the file system and other user data files The SDIO signal is connected to the I...

Page 44: ...J21 SD Data2 SD_D3 PS_MIO49 M18 SD Data3 SD_CD PS_MIO45 K20 SD card insertion signal Part 3 8 Expansion Header The AXU3EG board is reserved with two 0 1 inch standard pitch 40 pin expansion ports J45...

Page 45: ...45_L4_P J12 25 B46_L11_N J14 26 B46_L11_P K14 27 B46_L10_N H13 28 B46_L10_P H14 29 B46_L7_N F13 30 B46_L7_P G13 31 B46_L9_N G14 32 B46_L9_P G15 33 B46_L5_N D14 34 B46_L5_P D15 35 B46_L1_N A15 36 B46_L...

Page 46: ...ommunication interface There are 2 CAN communication interfaces on the AXU3EG carrier board which are connected to the MIO interface of the BANK501 on the PS system side The CAN transceiver chip selec...

Page 47: ...ard The 485 communication port 1 is connected to the IO interface of BANK43 45 on the PL system The 485 transceiver chip selects the MAX3485 chip from MAXIM for the user s 485 communication service Fi...

Page 48: ...rrier board includes a MIPI camera interface which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641 MIPI interface 15PIN FPC connector 2 LANE data and 1 pair of clock conne...

Page 49: ...B65_L3_N V8 MIPI Input Date LANE1 Negative CAM_GPIO B43_L4_P AE10 GPIO Control of Camera CAM_CLK B43_L4_N AF10 Clock Input of Camera CAM_SCL B43_L11_P Y9 I2C Clock of Camera CAM_SDA B43_L11_N AA8 I2C...

Page 50: ...vide an accurate clock source to the internal clock circuit so that the RTC can accurately provide clock information At the same time in order for the real time clock to operate normally after the pro...

Page 51: ...rough the IIC bus A high precision low power digital temperature sensor chip is installed on the AXU3EG FPGA development board and the model is LM75 from ON Semiconductor The temperature accuracy of t...

Page 52: ...ser can control the user LED on and off through the program When the IO voltage of the connected user LED light is low the user LED light is off and when the connected IO voltage is high the user LED...

Page 53: ...active The connection diagram of the user key is shown in Figure 3 16 1 ZYNQ Ultra Scale BANK 501 PS KEY PS_KEY1 PL KEY PL_KEY1 U1 BANK 43 Figure 3 16 1 Rest keys connection diagram ZYNQ pin assignmen...

Page 54: ...t mode ON ON ON ON 0000 PS JTAG ON ON OFF ON 0010 QSPI FLASH ON OFF ON OFF 0101 SD Card ON OFF OFF ON 0110 EMMC Part 3 18 Power Supply The power input voltage of the AXU3EG development board is DC12V...

Page 55: ...e Board 3 3V Ethernet USB2 0 SD DP CAN RS485 1 2V BANK65 of Core Board Part 3 19 ALINX Customized Fan Because AXU3EG generates a lot of heat when it works normally we add a heat sink and fan to the ch...

Page 56: ...16 1 Fan Design Schematic The fan has been screwed to the AXUEG FPGA development board before leaving the factory The power of the fan is connected to the socket of J24 The red is positive and the bla...

Reviews:

No comments